| blob | 33b5257e1bc6e7dc0aebd41ce365143355a07833 |
1 ; RUN: llc -mtriple=riscv32 -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | \
2 ; RUN: grep -v "Verify generated machine code" | \
3 ; RUN: FileCheck %s --check-prefixes=CHECK
4 ; RUN: llc -mtriple=riscv64 -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | \
5 ; RUN: grep -v "Verify generated machine code" | \
6 ; RUN: FileCheck %s --check-prefixes=CHECK,RV64
8 ; REQUIRES: asserts
10 ; CHECK-LABEL: Pass Arguments:
11 ; CHECK-NEXT: Target Library Information
12 ; CHECK-NEXT: Target Pass Configuration
13 ; CHECK-NEXT: Machine Module Information
14 ; CHECK-NEXT: Target Transform Information
15 ; CHECK-NEXT: Type-Based Alias Analysis
16 ; CHECK-NEXT: Scoped NoAlias Alias Analysis
17 ; CHECK-NEXT: Assumption Cache Tracker
18 ; CHECK-NEXT: Profile summary info
19 ; CHECK-NEXT: Create Garbage Collector Module Metadata
20 ; CHECK-NEXT: Machine Branch Probability Analysis
21 ; CHECK-NEXT: Default Regalloc Eviction Advisor
22 ; CHECK-NEXT: ModulePass Manager
23 ; CHECK-NEXT: Pre-ISel Intrinsic Lowering
24 ; CHECK-NEXT: FunctionPass Manager
25 ; CHECK-NEXT: Expand Atomic instructions
26 ; CHECK-NEXT: Dominator Tree Construction
27 ; CHECK-NEXT: Natural Loop Information
28 ; CHECK-NEXT: RISCV gather/scatter lowering
29 ; CHECK-NEXT: RISCV CodeGenPrepare
30 ; CHECK-NEXT: Module Verifier
31 ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
32 ; CHECK-NEXT: Canonicalize natural loops
33 ; CHECK-NEXT: Scalar Evolution Analysis
34 ; CHECK-NEXT: Loop Pass Manager
35 ; CHECK-NEXT: Canonicalize Freeze Instructions in Loops
36 ; CHECK-NEXT: Induction Variable Users
37 ; CHECK-NEXT: Loop Strength Reduction
38 ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
39 ; CHECK-NEXT: Function Alias Analysis Results
40 ; CHECK-NEXT: Merge contiguous icmps into a memcmp
41 ; CHECK-NEXT: Natural Loop Information
42 ; CHECK-NEXT: Lazy Branch Probability Analysis
43 ; CHECK-NEXT: Lazy Block Frequency Analysis
44 ; CHECK-NEXT: Expand memcmp() to load/stores
45 ; CHECK-NEXT: Lower Garbage Collection Instructions
46 ; CHECK-NEXT: Shadow Stack GC Lowering
47 ; CHECK-NEXT: Lower constant intrinsics
48 ; CHECK-NEXT: Remove unreachable blocks from the CFG
49 ; CHECK-NEXT: Natural Loop Information
50 ; CHECK-NEXT: Post-Dominator Tree Construction
51 ; CHECK-NEXT: Branch Probability Analysis
52 ; CHECK-NEXT: Block Frequency Analysis
53 ; CHECK-NEXT: Constant Hoisting
54 ; CHECK-NEXT: Replace intrinsics with calls to vector library
55 ; CHECK-NEXT: Partially inline calls to library functions
56 ; CHECK-NEXT: Expand vector predication intrinsics
57 ; CHECK-NEXT: Scalarize Masked Memory Intrinsics
58 ; CHECK-NEXT: Expand reduction intrinsics
59 ; CHECK-NEXT: Natural Loop Information
60 ; CHECK-NEXT: TLS Variable Hoist
61 ; CHECK-NEXT: CodeGen Prepare
62 ; CHECK-NEXT: Dominator Tree Construction
63 ; CHECK-NEXT: Exception handling preparation
64 ; CHECK-NEXT: A No-Op Barrier Pass
65 ; CHECK-NEXT: FunctionPass Manager
66 ; CHECK-NEXT: Safe Stack instrumentation pass
67 ; CHECK-NEXT: Insert stack protectors
68 ; CHECK-NEXT: Module Verifier
69 ; CHECK-NEXT: Dominator Tree Construction
70 ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
71 ; CHECK-NEXT: Function Alias Analysis Results
72 ; CHECK-NEXT: Natural Loop Information
73 ; CHECK-NEXT: Post-Dominator Tree Construction
74 ; CHECK-NEXT: Branch Probability Analysis
75 ; CHECK-NEXT: Lazy Branch Probability Analysis
76 ; CHECK-NEXT: Lazy Block Frequency Analysis
77 ; CHECK-NEXT: RISCV DAG->DAG Pattern Instruction Selection
78 ; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
79 ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
80 ; CHECK-NEXT: Early Tail Duplication
81 ; CHECK-NEXT: Optimize machine instruction PHIs
82 ; CHECK-NEXT: Slot index numbering
83 ; CHECK-NEXT: Merge disjoint stack slots
84 ; CHECK-NEXT: Local Stack Slot Allocation
85 ; CHECK-NEXT: Remove dead machine instructions
86 ; CHECK-NEXT: MachineDominator Tree Construction
87 ; CHECK-NEXT: Machine Natural Loop Construction
88 ; CHECK-NEXT: Machine Block Frequency Analysis
89 ; CHECK-NEXT: Early Machine Loop Invariant Code Motion
90 ; CHECK-NEXT: MachineDominator Tree Construction
91 ; CHECK-NEXT: Machine Block Frequency Analysis
92 ; CHECK-NEXT: Machine Common Subexpression Elimination
93 ; CHECK-NEXT: MachinePostDominator Tree Construction
94 ; CHECK-NEXT: Machine Cycle Info Analysis
95 ; CHECK-NEXT: Machine code sinking
96 ; CHECK-NEXT: Peephole Optimizations
97 ; CHECK-NEXT: Remove dead machine instructions
98 ; RV64-NEXT: RISCV sext.w Removal
99 ; CHECK-NEXT: RISCV Pre-RA pseudo instruction expansion pass
100 ; CHECK-NEXT: RISCV Merge Base Offset
101 ; CHECK-NEXT: RISCV Insert VSETVLI pass
102 ; CHECK-NEXT: Detect Dead Lanes
103 ; CHECK-NEXT: Process Implicit Definitions
104 ; CHECK-NEXT: Remove unreachable machine basic blocks
105 ; CHECK-NEXT: Live Variable Analysis
106 ; CHECK-NEXT: Eliminate PHI nodes for register allocation
107 ; CHECK-NEXT: Two-Address instruction pass
108 ; CHECK-NEXT: MachineDominator Tree Construction
109 ; CHECK-NEXT: Slot index numbering
110 ; CHECK-NEXT: Live Interval Analysis
111 ; CHECK-NEXT: Simple Register Coalescing
112 ; CHECK-NEXT: Rename Disconnected Subregister Components
113 ; CHECK-NEXT: Machine Instruction Scheduler
114 ; CHECK-NEXT: Machine Block Frequency Analysis
115 ; CHECK-NEXT: Debug Variable Analysis
116 ; CHECK-NEXT: Live Stack Slot Analysis
117 ; CHECK-NEXT: Virtual Register Map
118 ; CHECK-NEXT: Live Register Matrix
119 ; CHECK-NEXT: Bundle Machine CFG Edges
120 ; CHECK-NEXT: Spill Code Placement Analysis
121 ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
122 ; CHECK-NEXT: Machine Optimization Remark Emitter
123 ; CHECK-NEXT: Greedy Register Allocator
124 ; CHECK-NEXT: Virtual Register Rewriter
125 ; CHECK-NEXT: Register Allocation Pass Scoring
126 ; CHECK-NEXT: Stack Slot Coloring
127 ; CHECK-NEXT: Machine Copy Propagation Pass
128 ; CHECK-NEXT: Machine Loop Invariant Code Motion
129 ; CHECK-NEXT: RISCV Redundant Copy Elimination
130 ; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis
131 ; CHECK-NEXT: Fixup Statepoint Caller Saved
132 ; CHECK-NEXT: PostRA Machine Sink
133 ; CHECK-NEXT: MachineDominator Tree Construction
134 ; CHECK-NEXT: Machine Natural Loop Construction
135 ; CHECK-NEXT: Machine Block Frequency Analysis
136 ; CHECK-NEXT: MachinePostDominator Tree Construction
137 ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
138 ; CHECK-NEXT: Machine Optimization Remark Emitter
139 ; CHECK-NEXT: Shrink Wrapping analysis
140 ; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization
141 ; CHECK-NEXT: Control Flow Optimizer
142 ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
143 ; CHECK-NEXT: Tail Duplication
144 ; CHECK-NEXT: Machine Copy Propagation Pass
145 ; CHECK-NEXT: Post-RA pseudo instruction expansion pass
146 ; CHECK-NEXT: MachineDominator Tree Construction
147 ; CHECK-NEXT: Machine Natural Loop Construction
148 ; CHECK-NEXT: Post RA top-down list latency scheduler
149 ; CHECK-NEXT: Analyze Machine Code For Garbage Collection
150 ; CHECK-NEXT: Machine Block Frequency Analysis
151 ; CHECK-NEXT: MachinePostDominator Tree Construction
152 ; CHECK-NEXT: Branch Probability Basic Block Placement
153 ; CHECK-NEXT: Insert fentry calls
154 ; CHECK-NEXT: Insert XRay ops
155 ; CHECK-NEXT: Implement the 'patchable-function' attribute
156 ; CHECK-NEXT: Branch relaxation pass
157 ; CHECK-NEXT: RISCV Make Compressible
158 ; CHECK-NEXT: Contiguously Lay Out Funclets
159 ; CHECK-NEXT: StackMap Liveness Analysis
160 ; CHECK-NEXT: Live DEBUG_VALUE analysis
161 ; CHECK-NEXT: Machine Outliner
162 ; CHECK-NEXT: FunctionPass Manager
163 ; CHECK-NEXT: RISCV pseudo instruction expansion pass
164 ; CHECK-NEXT: RISCV atomic pseudo instruction expansion pass
165 ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
166 ; CHECK-NEXT: Machine Optimization Remark Emitter
167 ; CHECK-NEXT: RISCV Assembly Printer
168 ; CHECK-NEXT: Free MachineFunction