| blob | b66d156abbee767be676e412e4c76f6ac6d5aaec |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
3 ; RUN: -verify-machineinstrs -target-abi=ilp32d \
4 ; RUN: | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
5 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
6 ; RUN: -verify-machineinstrs -target-abi=lp64d \
7 ; RUN: | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
8 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
9 ; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV32I %s
10 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
11 ; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64I %s
13 declare double @llvm.sqrt.f64(double)
15 define double @sqrt_f64(double %a) nounwind {
16 ; CHECKIFD-LABEL: sqrt_f64:
17 ; CHECKIFD: # %bb.0:
18 ; CHECKIFD-NEXT: fsqrt.d fa0, fa0
19 ; CHECKIFD-NEXT: ret
20 ;
21 ; RV32I-LABEL: sqrt_f64:
22 ; RV32I: # %bb.0:
23 ; RV32I-NEXT: addi sp, sp, -16
24 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
25 ; RV32I-NEXT: call sqrt@plt
26 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
27 ; RV32I-NEXT: addi sp, sp, 16
28 ; RV32I-NEXT: ret
29 ;
30 ; RV64I-LABEL: sqrt_f64:
31 ; RV64I: # %bb.0:
32 ; RV64I-NEXT: addi sp, sp, -16
33 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
34 ; RV64I-NEXT: call sqrt@plt
35 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
36 ; RV64I-NEXT: addi sp, sp, 16
37 ; RV64I-NEXT: ret
38 %1 = call double @llvm.sqrt.f64(double %a)
39 ret double %1
40 }
42 declare double @llvm.powi.f64.i32(double, i32)
44 define double @powi_f64(double %a, i32 %b) nounwind {
45 ; RV32IFD-LABEL: powi_f64:
46 ; RV32IFD: # %bb.0:
47 ; RV32IFD-NEXT: tail __powidf2@plt
48 ;
49 ; RV64IFD-LABEL: powi_f64:
50 ; RV64IFD: # %bb.0:
51 ; RV64IFD-NEXT: addi sp, sp, -16
52 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
53 ; RV64IFD-NEXT: sext.w a0, a0
54 ; RV64IFD-NEXT: call __powidf2@plt
55 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
56 ; RV64IFD-NEXT: addi sp, sp, 16
57 ; RV64IFD-NEXT: ret
58 ;
59 ; RV32I-LABEL: powi_f64:
60 ; RV32I: # %bb.0:
61 ; RV32I-NEXT: addi sp, sp, -16
62 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
63 ; RV32I-NEXT: call __powidf2@plt
64 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
65 ; RV32I-NEXT: addi sp, sp, 16
66 ; RV32I-NEXT: ret
67 ;
68 ; RV64I-LABEL: powi_f64:
69 ; RV64I: # %bb.0:
70 ; RV64I-NEXT: addi sp, sp, -16
71 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
72 ; RV64I-NEXT: sext.w a1, a1
73 ; RV64I-NEXT: call __powidf2@plt
74 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
75 ; RV64I-NEXT: addi sp, sp, 16
76 ; RV64I-NEXT: ret
77 %1 = call double @llvm.powi.f64.i32(double %a, i32 %b)
78 ret double %1
79 }
81 declare double @llvm.sin.f64(double)
83 define double @sin_f64(double %a) nounwind {
84 ; CHECKIFD-LABEL: sin_f64:
85 ; CHECKIFD: # %bb.0:
86 ; CHECKIFD-NEXT: tail sin@plt
87 ;
88 ; RV32I-LABEL: sin_f64:
89 ; RV32I: # %bb.0:
90 ; RV32I-NEXT: addi sp, sp, -16
91 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
92 ; RV32I-NEXT: call sin@plt
93 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
94 ; RV32I-NEXT: addi sp, sp, 16
95 ; RV32I-NEXT: ret
96 ;
97 ; RV64I-LABEL: sin_f64:
98 ; RV64I: # %bb.0:
99 ; RV64I-NEXT: addi sp, sp, -16
100 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
101 ; RV64I-NEXT: call sin@plt
102 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
103 ; RV64I-NEXT: addi sp, sp, 16
104 ; RV64I-NEXT: ret
105 %1 = call double @llvm.sin.f64(double %a)
106 ret double %1
107 }
109 declare double @llvm.cos.f64(double)
111 define double @cos_f64(double %a) nounwind {
112 ; CHECKIFD-LABEL: cos_f64:
113 ; CHECKIFD: # %bb.0:
114 ; CHECKIFD-NEXT: tail cos@plt
115 ;
116 ; RV32I-LABEL: cos_f64:
117 ; RV32I: # %bb.0:
118 ; RV32I-NEXT: addi sp, sp, -16
119 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
120 ; RV32I-NEXT: call cos@plt
121 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
122 ; RV32I-NEXT: addi sp, sp, 16
123 ; RV32I-NEXT: ret
124 ;
125 ; RV64I-LABEL: cos_f64:
126 ; RV64I: # %bb.0:
127 ; RV64I-NEXT: addi sp, sp, -16
128 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
129 ; RV64I-NEXT: call cos@plt
130 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
131 ; RV64I-NEXT: addi sp, sp, 16
132 ; RV64I-NEXT: ret
133 %1 = call double @llvm.cos.f64(double %a)
134 ret double %1
135 }
137 ; The sin+cos combination results in an FSINCOS SelectionDAG node.
138 define double @sincos_f64(double %a) nounwind {
139 ; RV32IFD-LABEL: sincos_f64:
140 ; RV32IFD: # %bb.0:
141 ; RV32IFD-NEXT: addi sp, sp, -32
142 ; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
143 ; RV32IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill
144 ; RV32IFD-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill
145 ; RV32IFD-NEXT: fmv.d fs0, fa0
146 ; RV32IFD-NEXT: call sin@plt
147 ; RV32IFD-NEXT: fmv.d fs1, fa0
148 ; RV32IFD-NEXT: fmv.d fa0, fs0
149 ; RV32IFD-NEXT: call cos@plt
150 ; RV32IFD-NEXT: fadd.d fa0, fs1, fa0
151 ; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
152 ; RV32IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
153 ; RV32IFD-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload
154 ; RV32IFD-NEXT: addi sp, sp, 32
155 ; RV32IFD-NEXT: ret
156 ;
157 ; RV64IFD-LABEL: sincos_f64:
158 ; RV64IFD: # %bb.0:
159 ; RV64IFD-NEXT: addi sp, sp, -32
160 ; RV64IFD-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
161 ; RV64IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill
162 ; RV64IFD-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill
163 ; RV64IFD-NEXT: fmv.d fs0, fa0
164 ; RV64IFD-NEXT: call sin@plt
165 ; RV64IFD-NEXT: fmv.d fs1, fa0
166 ; RV64IFD-NEXT: fmv.d fa0, fs0
167 ; RV64IFD-NEXT: call cos@plt
168 ; RV64IFD-NEXT: fadd.d fa0, fs1, fa0
169 ; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
170 ; RV64IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
171 ; RV64IFD-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload
172 ; RV64IFD-NEXT: addi sp, sp, 32
173 ; RV64IFD-NEXT: ret
174 ;
175 ; RV32I-LABEL: sincos_f64:
176 ; RV32I: # %bb.0:
177 ; RV32I-NEXT: addi sp, sp, -32
178 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
179 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
180 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
181 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
182 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
183 ; RV32I-NEXT: mv s0, a1
184 ; RV32I-NEXT: mv s1, a0
185 ; RV32I-NEXT: call sin@plt
186 ; RV32I-NEXT: mv s2, a0
187 ; RV32I-NEXT: mv s3, a1
188 ; RV32I-NEXT: mv a0, s1
189 ; RV32I-NEXT: mv a1, s0
190 ; RV32I-NEXT: call cos@plt
191 ; RV32I-NEXT: mv a2, a0
192 ; RV32I-NEXT: mv a3, a1
193 ; RV32I-NEXT: mv a0, s2
194 ; RV32I-NEXT: mv a1, s3
195 ; RV32I-NEXT: call __adddf3@plt
196 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
197 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
198 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
199 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
200 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
201 ; RV32I-NEXT: addi sp, sp, 32
202 ; RV32I-NEXT: ret
203 ;
204 ; RV64I-LABEL: sincos_f64:
205 ; RV64I: # %bb.0:
206 ; RV64I-NEXT: addi sp, sp, -32
207 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
208 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
209 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
210 ; RV64I-NEXT: mv s0, a0
211 ; RV64I-NEXT: call sin@plt
212 ; RV64I-NEXT: mv s1, a0
213 ; RV64I-NEXT: mv a0, s0
214 ; RV64I-NEXT: call cos@plt
215 ; RV64I-NEXT: mv a1, a0
216 ; RV64I-NEXT: mv a0, s1
217 ; RV64I-NEXT: call __adddf3@plt
218 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
219 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
220 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
221 ; RV64I-NEXT: addi sp, sp, 32
222 ; RV64I-NEXT: ret
223 %1 = call double @llvm.sin.f64(double %a)
224 %2 = call double @llvm.cos.f64(double %a)
225 %3 = fadd double %1, %2
226 ret double %3
227 }
229 declare double @llvm.pow.f64(double, double)
231 define double @pow_f64(double %a, double %b) nounwind {
232 ; CHECKIFD-LABEL: pow_f64:
233 ; CHECKIFD: # %bb.0:
234 ; CHECKIFD-NEXT: tail pow@plt
235 ;
236 ; RV32I-LABEL: pow_f64:
237 ; RV32I: # %bb.0:
238 ; RV32I-NEXT: addi sp, sp, -16
239 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
240 ; RV32I-NEXT: call pow@plt
241 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
242 ; RV32I-NEXT: addi sp, sp, 16
243 ; RV32I-NEXT: ret
244 ;
245 ; RV64I-LABEL: pow_f64:
246 ; RV64I: # %bb.0:
247 ; RV64I-NEXT: addi sp, sp, -16
248 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
249 ; RV64I-NEXT: call pow@plt
250 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
251 ; RV64I-NEXT: addi sp, sp, 16
252 ; RV64I-NEXT: ret
253 %1 = call double @llvm.pow.f64(double %a, double %b)
254 ret double %1
255 }
257 declare double @llvm.exp.f64(double)
259 define double @exp_f64(double %a) nounwind {
260 ; CHECKIFD-LABEL: exp_f64:
261 ; CHECKIFD: # %bb.0:
262 ; CHECKIFD-NEXT: tail exp@plt
263 ;
264 ; RV32I-LABEL: exp_f64:
265 ; RV32I: # %bb.0:
266 ; RV32I-NEXT: addi sp, sp, -16
267 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
268 ; RV32I-NEXT: call exp@plt
269 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
270 ; RV32I-NEXT: addi sp, sp, 16
271 ; RV32I-NEXT: ret
272 ;
273 ; RV64I-LABEL: exp_f64:
274 ; RV64I: # %bb.0:
275 ; RV64I-NEXT: addi sp, sp, -16
276 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
277 ; RV64I-NEXT: call exp@plt
278 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
279 ; RV64I-NEXT: addi sp, sp, 16
280 ; RV64I-NEXT: ret
281 %1 = call double @llvm.exp.f64(double %a)
282 ret double %1
283 }
285 declare double @llvm.exp2.f64(double)
287 define double @exp2_f64(double %a) nounwind {
288 ; CHECKIFD-LABEL: exp2_f64:
289 ; CHECKIFD: # %bb.0:
290 ; CHECKIFD-NEXT: tail exp2@plt
291 ;
292 ; RV32I-LABEL: exp2_f64:
293 ; RV32I: # %bb.0:
294 ; RV32I-NEXT: addi sp, sp, -16
295 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
296 ; RV32I-NEXT: call exp2@plt
297 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
298 ; RV32I-NEXT: addi sp, sp, 16
299 ; RV32I-NEXT: ret
300 ;
301 ; RV64I-LABEL: exp2_f64:
302 ; RV64I: # %bb.0:
303 ; RV64I-NEXT: addi sp, sp, -16
304 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
305 ; RV64I-NEXT: call exp2@plt
306 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
307 ; RV64I-NEXT: addi sp, sp, 16
308 ; RV64I-NEXT: ret
309 %1 = call double @llvm.exp2.f64(double %a)
310 ret double %1
311 }
313 declare double @llvm.log.f64(double)
315 define double @log_f64(double %a) nounwind {
316 ; CHECKIFD-LABEL: log_f64:
317 ; CHECKIFD: # %bb.0:
318 ; CHECKIFD-NEXT: tail log@plt
319 ;
320 ; RV32I-LABEL: log_f64:
321 ; RV32I: # %bb.0:
322 ; RV32I-NEXT: addi sp, sp, -16
323 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
324 ; RV32I-NEXT: call log@plt
325 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
326 ; RV32I-NEXT: addi sp, sp, 16
327 ; RV32I-NEXT: ret
328 ;
329 ; RV64I-LABEL: log_f64:
330 ; RV64I: # %bb.0:
331 ; RV64I-NEXT: addi sp, sp, -16
332 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
333 ; RV64I-NEXT: call log@plt
334 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
335 ; RV64I-NEXT: addi sp, sp, 16
336 ; RV64I-NEXT: ret
337 %1 = call double @llvm.log.f64(double %a)
338 ret double %1
339 }
341 declare double @llvm.log10.f64(double)
343 define double @log10_f64(double %a) nounwind {
344 ; CHECKIFD-LABEL: log10_f64:
345 ; CHECKIFD: # %bb.0:
346 ; CHECKIFD-NEXT: tail log10@plt
347 ;
348 ; RV32I-LABEL: log10_f64:
349 ; RV32I: # %bb.0:
350 ; RV32I-NEXT: addi sp, sp, -16
351 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
352 ; RV32I-NEXT: call log10@plt
353 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
354 ; RV32I-NEXT: addi sp, sp, 16
355 ; RV32I-NEXT: ret
356 ;
357 ; RV64I-LABEL: log10_f64:
358 ; RV64I: # %bb.0:
359 ; RV64I-NEXT: addi sp, sp, -16
360 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
361 ; RV64I-NEXT: call log10@plt
362 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
363 ; RV64I-NEXT: addi sp, sp, 16
364 ; RV64I-NEXT: ret
365 %1 = call double @llvm.log10.f64(double %a)
366 ret double %1
367 }
369 declare double @llvm.log2.f64(double)
371 define double @log2_f64(double %a) nounwind {
372 ; CHECKIFD-LABEL: log2_f64:
373 ; CHECKIFD: # %bb.0:
374 ; CHECKIFD-NEXT: tail log2@plt
375 ;
376 ; RV32I-LABEL: log2_f64:
377 ; RV32I: # %bb.0:
378 ; RV32I-NEXT: addi sp, sp, -16
379 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
380 ; RV32I-NEXT: call log2@plt
381 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
382 ; RV32I-NEXT: addi sp, sp, 16
383 ; RV32I-NEXT: ret
384 ;
385 ; RV64I-LABEL: log2_f64:
386 ; RV64I: # %bb.0:
387 ; RV64I-NEXT: addi sp, sp, -16
388 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
389 ; RV64I-NEXT: call log2@plt
390 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
391 ; RV64I-NEXT: addi sp, sp, 16
392 ; RV64I-NEXT: ret
393 %1 = call double @llvm.log2.f64(double %a)
394 ret double %1
395 }
397 declare double @llvm.fma.f64(double, double, double)
399 define double @fma_f64(double %a, double %b, double %c) nounwind {
400 ; CHECKIFD-LABEL: fma_f64:
401 ; CHECKIFD: # %bb.0:
402 ; CHECKIFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
403 ; CHECKIFD-NEXT: ret
404 ;
405 ; RV32I-LABEL: fma_f64:
406 ; RV32I: # %bb.0:
407 ; RV32I-NEXT: addi sp, sp, -16
408 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
409 ; RV32I-NEXT: call fma@plt
410 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
411 ; RV32I-NEXT: addi sp, sp, 16
412 ; RV32I-NEXT: ret
413 ;
414 ; RV64I-LABEL: fma_f64:
415 ; RV64I: # %bb.0:
416 ; RV64I-NEXT: addi sp, sp, -16
417 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
418 ; RV64I-NEXT: call fma@plt
419 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
420 ; RV64I-NEXT: addi sp, sp, 16
421 ; RV64I-NEXT: ret
422 %1 = call double @llvm.fma.f64(double %a, double %b, double %c)
423 ret double %1
424 }
426 declare double @llvm.fmuladd.f64(double, double, double)
428 define double @fmuladd_f64(double %a, double %b, double %c) nounwind {
429 ; CHECKIFD-LABEL: fmuladd_f64:
430 ; CHECKIFD: # %bb.0:
431 ; CHECKIFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
432 ; CHECKIFD-NEXT: ret
433 ;
434 ; RV32I-LABEL: fmuladd_f64:
435 ; RV32I: # %bb.0:
436 ; RV32I-NEXT: addi sp, sp, -16
437 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
438 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
439 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
440 ; RV32I-NEXT: mv s0, a5
441 ; RV32I-NEXT: mv s1, a4
442 ; RV32I-NEXT: call __muldf3@plt
443 ; RV32I-NEXT: mv a2, s1
444 ; RV32I-NEXT: mv a3, s0
445 ; RV32I-NEXT: call __adddf3@plt
446 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
447 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
448 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
449 ; RV32I-NEXT: addi sp, sp, 16
450 ; RV32I-NEXT: ret
451 ;
452 ; RV64I-LABEL: fmuladd_f64:
453 ; RV64I: # %bb.0:
454 ; RV64I-NEXT: addi sp, sp, -16
455 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
456 ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
457 ; RV64I-NEXT: mv s0, a2
458 ; RV64I-NEXT: call __muldf3@plt
459 ; RV64I-NEXT: mv a1, s0
460 ; RV64I-NEXT: call __adddf3@plt
461 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
462 ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
463 ; RV64I-NEXT: addi sp, sp, 16
464 ; RV64I-NEXT: ret
465 %1 = call double @llvm.fmuladd.f64(double %a, double %b, double %c)
466 ret double %1
467 }
469 declare double @llvm.fabs.f64(double)
471 define double @fabs_f64(double %a) nounwind {
472 ; CHECKIFD-LABEL: fabs_f64:
473 ; CHECKIFD: # %bb.0:
474 ; CHECKIFD-NEXT: fabs.d fa0, fa0
475 ; CHECKIFD-NEXT: ret
476 ;
477 ; RV32I-LABEL: fabs_f64:
478 ; RV32I: # %bb.0:
479 ; RV32I-NEXT: slli a1, a1, 1
480 ; RV32I-NEXT: srli a1, a1, 1
481 ; RV32I-NEXT: ret
482 ;
483 ; RV64I-LABEL: fabs_f64:
484 ; RV64I: # %bb.0:
485 ; RV64I-NEXT: slli a0, a0, 1
486 ; RV64I-NEXT: srli a0, a0, 1
487 ; RV64I-NEXT: ret
488 %1 = call double @llvm.fabs.f64(double %a)
489 ret double %1
490 }
492 declare double @llvm.minnum.f64(double, double)
494 define double @minnum_f64(double %a, double %b) nounwind {
495 ; CHECKIFD-LABEL: minnum_f64:
496 ; CHECKIFD: # %bb.0:
497 ; CHECKIFD-NEXT: fmin.d fa0, fa0, fa1
498 ; CHECKIFD-NEXT: ret
499 ;
500 ; RV32I-LABEL: minnum_f64:
501 ; RV32I: # %bb.0:
502 ; RV32I-NEXT: addi sp, sp, -16
503 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
504 ; RV32I-NEXT: call fmin@plt
505 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
506 ; RV32I-NEXT: addi sp, sp, 16
507 ; RV32I-NEXT: ret
508 ;
509 ; RV64I-LABEL: minnum_f64:
510 ; RV64I: # %bb.0:
511 ; RV64I-NEXT: addi sp, sp, -16
512 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
513 ; RV64I-NEXT: call fmin@plt
514 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
515 ; RV64I-NEXT: addi sp, sp, 16
516 ; RV64I-NEXT: ret
517 %1 = call double @llvm.minnum.f64(double %a, double %b)
518 ret double %1
519 }
521 declare double @llvm.maxnum.f64(double, double)
523 define double @maxnum_f64(double %a, double %b) nounwind {
524 ; CHECKIFD-LABEL: maxnum_f64:
525 ; CHECKIFD: # %bb.0:
526 ; CHECKIFD-NEXT: fmax.d fa0, fa0, fa1
527 ; CHECKIFD-NEXT: ret
528 ;
529 ; RV32I-LABEL: maxnum_f64:
530 ; RV32I: # %bb.0:
531 ; RV32I-NEXT: addi sp, sp, -16
532 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
533 ; RV32I-NEXT: call fmax@plt
534 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
535 ; RV32I-NEXT: addi sp, sp, 16
536 ; RV32I-NEXT: ret
537 ;
538 ; RV64I-LABEL: maxnum_f64:
539 ; RV64I: # %bb.0:
540 ; RV64I-NEXT: addi sp, sp, -16
541 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
542 ; RV64I-NEXT: call fmax@plt
543 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
544 ; RV64I-NEXT: addi sp, sp, 16
545 ; RV64I-NEXT: ret
546 %1 = call double @llvm.maxnum.f64(double %a, double %b)
547 ret double %1
548 }
550 ; TODO: FMINNAN and FMAXNAN aren't handled in
551 ; SelectionDAGLegalize::ExpandNode.
553 ; declare double @llvm.minimum.f64(double, double)
555 ; define double @fminimum_f64(double %a, double %b) nounwind {
556 ; %1 = call double @llvm.minimum.f64(double %a, double %b)
557 ; ret double %1
558 ; }
560 ; declare double @llvm.maximum.f64(double, double)
562 ; define double @fmaximum_f64(double %a, double %b) nounwind {
563 ; %1 = call double @llvm.maximum.f64(double %a, double %b)
564 ; ret double %1
565 ; }
567 declare double @llvm.copysign.f64(double, double)
569 define double @copysign_f64(double %a, double %b) nounwind {
570 ; CHECKIFD-LABEL: copysign_f64:
571 ; CHECKIFD: # %bb.0:
572 ; CHECKIFD-NEXT: fsgnj.d fa0, fa0, fa1
573 ; CHECKIFD-NEXT: ret
574 ;
575 ; RV32I-LABEL: copysign_f64:
576 ; RV32I: # %bb.0:
577 ; RV32I-NEXT: lui a2, 524288
578 ; RV32I-NEXT: and a2, a3, a2
579 ; RV32I-NEXT: slli a1, a1, 1
580 ; RV32I-NEXT: srli a1, a1, 1
581 ; RV32I-NEXT: or a1, a1, a2
582 ; RV32I-NEXT: ret
583 ;
584 ; RV64I-LABEL: copysign_f64:
585 ; RV64I: # %bb.0:
586 ; RV64I-NEXT: srli a1, a1, 63
587 ; RV64I-NEXT: slli a1, a1, 63
588 ; RV64I-NEXT: slli a0, a0, 1
589 ; RV64I-NEXT: srli a0, a0, 1
590 ; RV64I-NEXT: or a0, a0, a1
591 ; RV64I-NEXT: ret
592 %1 = call double @llvm.copysign.f64(double %a, double %b)
593 ret double %1
594 }
596 declare double @llvm.floor.f64(double)
598 define double @floor_f64(double %a) nounwind {
599 ; CHECKIFD-LABEL: floor_f64:
600 ; CHECKIFD: # %bb.0:
601 ; CHECKIFD-NEXT: tail floor@plt
602 ;
603 ; RV32I-LABEL: floor_f64:
604 ; RV32I: # %bb.0:
605 ; RV32I-NEXT: addi sp, sp, -16
606 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
607 ; RV32I-NEXT: call floor@plt
608 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
609 ; RV32I-NEXT: addi sp, sp, 16
610 ; RV32I-NEXT: ret
611 ;
612 ; RV64I-LABEL: floor_f64:
613 ; RV64I: # %bb.0:
614 ; RV64I-NEXT: addi sp, sp, -16
615 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
616 ; RV64I-NEXT: call floor@plt
617 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
618 ; RV64I-NEXT: addi sp, sp, 16
619 ; RV64I-NEXT: ret
620 %1 = call double @llvm.floor.f64(double %a)
621 ret double %1
622 }
624 declare double @llvm.ceil.f64(double)
626 define double @ceil_f64(double %a) nounwind {
627 ; CHECKIFD-LABEL: ceil_f64:
628 ; CHECKIFD: # %bb.0:
629 ; CHECKIFD-NEXT: tail ceil@plt
630 ;
631 ; RV32I-LABEL: ceil_f64:
632 ; RV32I: # %bb.0:
633 ; RV32I-NEXT: addi sp, sp, -16
634 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
635 ; RV32I-NEXT: call ceil@plt
636 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
637 ; RV32I-NEXT: addi sp, sp, 16
638 ; RV32I-NEXT: ret
639 ;
640 ; RV64I-LABEL: ceil_f64:
641 ; RV64I: # %bb.0:
642 ; RV64I-NEXT: addi sp, sp, -16
643 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
644 ; RV64I-NEXT: call ceil@plt
645 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
646 ; RV64I-NEXT: addi sp, sp, 16
647 ; RV64I-NEXT: ret
648 %1 = call double @llvm.ceil.f64(double %a)
649 ret double %1
650 }
652 declare double @llvm.trunc.f64(double)
654 define double @trunc_f64(double %a) nounwind {
655 ; CHECKIFD-LABEL: trunc_f64:
656 ; CHECKIFD: # %bb.0:
657 ; CHECKIFD-NEXT: tail trunc@plt
658 ;
659 ; RV32I-LABEL: trunc_f64:
660 ; RV32I: # %bb.0:
661 ; RV32I-NEXT: addi sp, sp, -16
662 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
663 ; RV32I-NEXT: call trunc@plt
664 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
665 ; RV32I-NEXT: addi sp, sp, 16
666 ; RV32I-NEXT: ret
667 ;
668 ; RV64I-LABEL: trunc_f64:
669 ; RV64I: # %bb.0:
670 ; RV64I-NEXT: addi sp, sp, -16
671 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
672 ; RV64I-NEXT: call trunc@plt
673 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
674 ; RV64I-NEXT: addi sp, sp, 16
675 ; RV64I-NEXT: ret
676 %1 = call double @llvm.trunc.f64(double %a)
677 ret double %1
678 }
680 declare double @llvm.rint.f64(double)
682 define double @rint_f64(double %a) nounwind {
683 ; CHECKIFD-LABEL: rint_f64:
684 ; CHECKIFD: # %bb.0:
685 ; CHECKIFD-NEXT: tail rint@plt
686 ;
687 ; RV32I-LABEL: rint_f64:
688 ; RV32I: # %bb.0:
689 ; RV32I-NEXT: addi sp, sp, -16
690 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
691 ; RV32I-NEXT: call rint@plt
692 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
693 ; RV32I-NEXT: addi sp, sp, 16
694 ; RV32I-NEXT: ret
695 ;
696 ; RV64I-LABEL: rint_f64:
697 ; RV64I: # %bb.0:
698 ; RV64I-NEXT: addi sp, sp, -16
699 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
700 ; RV64I-NEXT: call rint@plt
701 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
702 ; RV64I-NEXT: addi sp, sp, 16
703 ; RV64I-NEXT: ret
704 %1 = call double @llvm.rint.f64(double %a)
705 ret double %1
706 }
708 declare double @llvm.nearbyint.f64(double)
710 define double @nearbyint_f64(double %a) nounwind {
711 ; CHECKIFD-LABEL: nearbyint_f64:
712 ; CHECKIFD: # %bb.0:
713 ; CHECKIFD-NEXT: tail nearbyint@plt
714 ;
715 ; RV32I-LABEL: nearbyint_f64:
716 ; RV32I: # %bb.0:
717 ; RV32I-NEXT: addi sp, sp, -16
718 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
719 ; RV32I-NEXT: call nearbyint@plt
720 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
721 ; RV32I-NEXT: addi sp, sp, 16
722 ; RV32I-NEXT: ret
723 ;
724 ; RV64I-LABEL: nearbyint_f64:
725 ; RV64I: # %bb.0:
726 ; RV64I-NEXT: addi sp, sp, -16
727 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
728 ; RV64I-NEXT: call nearbyint@plt
729 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
730 ; RV64I-NEXT: addi sp, sp, 16
731 ; RV64I-NEXT: ret
732 %1 = call double @llvm.nearbyint.f64(double %a)
733 ret double %1
734 }
736 declare double @llvm.round.f64(double)
738 define double @round_f64(double %a) nounwind {
739 ; CHECKIFD-LABEL: round_f64:
740 ; CHECKIFD: # %bb.0:
741 ; CHECKIFD-NEXT: tail round@plt
742 ;
743 ; RV32I-LABEL: round_f64:
744 ; RV32I: # %bb.0:
745 ; RV32I-NEXT: addi sp, sp, -16
746 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
747 ; RV32I-NEXT: call round@plt
748 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
749 ; RV32I-NEXT: addi sp, sp, 16
750 ; RV32I-NEXT: ret
751 ;
752 ; RV64I-LABEL: round_f64:
753 ; RV64I: # %bb.0:
754 ; RV64I-NEXT: addi sp, sp, -16
755 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
756 ; RV64I-NEXT: call round@plt
757 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
758 ; RV64I-NEXT: addi sp, sp, 16
759 ; RV64I-NEXT: ret
760 %1 = call double @llvm.round.f64(double %a)
761 ret double %1
762 }
764 declare double @llvm.roundeven.f64(double)
766 define double @roundeven_f64(double %a) nounwind {
767 ; CHECKIFD-LABEL: roundeven_f64:
768 ; CHECKIFD: # %bb.0:
769 ; CHECKIFD-NEXT: tail roundeven@plt
770 ;
771 ; RV32I-LABEL: roundeven_f64:
772 ; RV32I: # %bb.0:
773 ; RV32I-NEXT: addi sp, sp, -16
774 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
775 ; RV32I-NEXT: call roundeven@plt
776 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
777 ; RV32I-NEXT: addi sp, sp, 16
778 ; RV32I-NEXT: ret
779 ;
780 ; RV64I-LABEL: roundeven_f64:
781 ; RV64I: # %bb.0:
782 ; RV64I-NEXT: addi sp, sp, -16
783 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
784 ; RV64I-NEXT: call roundeven@plt
785 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
786 ; RV64I-NEXT: addi sp, sp, 16
787 ; RV64I-NEXT: ret
788 %1 = call double @llvm.roundeven.f64(double %a)
789 ret double %1
790 }
792 declare iXLen @llvm.lrint.iXLen.f64(double)
794 define iXLen @lrint_f64(double %a) nounwind {
795 ; RV32IFD-LABEL: lrint_f64:
796 ; RV32IFD: # %bb.0:
797 ; RV32IFD-NEXT: fcvt.w.d a0, fa0
798 ; RV32IFD-NEXT: ret
799 ;
800 ; RV64IFD-LABEL: lrint_f64:
801 ; RV64IFD: # %bb.0:
802 ; RV64IFD-NEXT: fcvt.l.d a0, fa0
803 ; RV64IFD-NEXT: ret
804 ;
805 ; RV32I-LABEL: lrint_f64:
806 ; RV32I: # %bb.0:
807 ; RV32I-NEXT: addi sp, sp, -16
808 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
809 ; RV32I-NEXT: call lrint@plt
810 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
811 ; RV32I-NEXT: addi sp, sp, 16
812 ; RV32I-NEXT: ret
813 ;
814 ; RV64I-LABEL: lrint_f64:
815 ; RV64I: # %bb.0:
816 ; RV64I-NEXT: addi sp, sp, -16
817 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
818 ; RV64I-NEXT: call lrint@plt
819 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
820 ; RV64I-NEXT: addi sp, sp, 16
821 ; RV64I-NEXT: ret
822 %1 = call iXLen @llvm.lrint.iXLen.f64(double %a)
823 ret iXLen %1
824 }
826 declare iXLen @llvm.lround.iXLen.f64(double)
828 define iXLen @lround_f64(double %a) nounwind {
829 ; RV32IFD-LABEL: lround_f64:
830 ; RV32IFD: # %bb.0:
831 ; RV32IFD-NEXT: fcvt.w.d a0, fa0, rmm
832 ; RV32IFD-NEXT: ret
833 ;
834 ; RV64IFD-LABEL: lround_f64:
835 ; RV64IFD: # %bb.0:
836 ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rmm
837 ; RV64IFD-NEXT: ret
838 ;
839 ; RV32I-LABEL: lround_f64:
840 ; RV32I: # %bb.0:
841 ; RV32I-NEXT: addi sp, sp, -16
842 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
843 ; RV32I-NEXT: call lround@plt
844 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
845 ; RV32I-NEXT: addi sp, sp, 16
846 ; RV32I-NEXT: ret
847 ;
848 ; RV64I-LABEL: lround_f64:
849 ; RV64I: # %bb.0:
850 ; RV64I-NEXT: addi sp, sp, -16
851 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
852 ; RV64I-NEXT: call lround@plt
853 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
854 ; RV64I-NEXT: addi sp, sp, 16
855 ; RV64I-NEXT: ret
856 %1 = call iXLen @llvm.lround.iXLen.f64(double %a)
857 ret iXLen %1
858 }
860 declare i64 @llvm.llrint.i64.f64(double)
862 define i64 @llrint_f64(double %a) nounwind {
863 ; RV32IFD-LABEL: llrint_f64:
864 ; RV32IFD: # %bb.0:
865 ; RV32IFD-NEXT: addi sp, sp, -16
866 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
867 ; RV32IFD-NEXT: call llrint@plt
868 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
869 ; RV32IFD-NEXT: addi sp, sp, 16
870 ; RV32IFD-NEXT: ret
871 ;
872 ; RV64IFD-LABEL: llrint_f64:
873 ; RV64IFD: # %bb.0:
874 ; RV64IFD-NEXT: fcvt.l.d a0, fa0
875 ; RV64IFD-NEXT: ret
876 ;
877 ; RV32I-LABEL: llrint_f64:
878 ; RV32I: # %bb.0:
879 ; RV32I-NEXT: addi sp, sp, -16
880 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
881 ; RV32I-NEXT: call llrint@plt
882 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
883 ; RV32I-NEXT: addi sp, sp, 16
884 ; RV32I-NEXT: ret
885 ;
886 ; RV64I-LABEL: llrint_f64:
887 ; RV64I: # %bb.0:
888 ; RV64I-NEXT: addi sp, sp, -16
889 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
890 ; RV64I-NEXT: call llrint@plt
891 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
892 ; RV64I-NEXT: addi sp, sp, 16
893 ; RV64I-NEXT: ret
894 %1 = call i64 @llvm.llrint.i64.f64(double %a)
895 ret i64 %1
896 }
898 declare i64 @llvm.llround.i64.f64(double)
900 define i64 @llround_f64(double %a) nounwind {
901 ; RV32IFD-LABEL: llround_f64:
902 ; RV32IFD: # %bb.0:
903 ; RV32IFD-NEXT: addi sp, sp, -16
904 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
905 ; RV32IFD-NEXT: call llround@plt
906 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
907 ; RV32IFD-NEXT: addi sp, sp, 16
908 ; RV32IFD-NEXT: ret
909 ;
910 ; RV64IFD-LABEL: llround_f64:
911 ; RV64IFD: # %bb.0:
912 ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rmm
913 ; RV64IFD-NEXT: ret
914 ;
915 ; RV32I-LABEL: llround_f64:
916 ; RV32I: # %bb.0:
917 ; RV32I-NEXT: addi sp, sp, -16
918 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
919 ; RV32I-NEXT: call llround@plt
920 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
921 ; RV32I-NEXT: addi sp, sp, 16
922 ; RV32I-NEXT: ret
923 ;
924 ; RV64I-LABEL: llround_f64:
925 ; RV64I: # %bb.0:
926 ; RV64I-NEXT: addi sp, sp, -16
927 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
928 ; RV64I-NEXT: call llround@plt
929 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
930 ; RV64I-NEXT: addi sp, sp, 16
931 ; RV64I-NEXT: ret
932 %1 = call i64 @llvm.llround.i64.f64(double %a)
933 ret i64 %1
934 }