| blob | 787269f71950ad6212b3282d2284bafdc9b34c73 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
3 ; RUN: -target-abi=ilp32d | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
4 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
5 ; RUN: -target-abi=lp64d | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
7 define signext i32 @test_floor_si32(double %x) {
8 ; CHECKIFD-LABEL: test_floor_si32:
9 ; CHECKIFD: # %bb.0:
10 ; CHECKIFD-NEXT: feq.d a0, fa0, fa0
11 ; CHECKIFD-NEXT: beqz a0, .LBB0_2
12 ; CHECKIFD-NEXT: # %bb.1:
13 ; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rdn
14 ; CHECKIFD-NEXT: .LBB0_2:
15 ; CHECKIFD-NEXT: ret
16 %a = call double @llvm.floor.f64(double %x)
17 %b = call i32 @llvm.fptosi.sat.i32.f64(double %a)
18 ret i32 %b
19 }
21 define i64 @test_floor_si64(double %x) nounwind {
22 ; RV32IFD-LABEL: test_floor_si64:
23 ; RV32IFD: # %bb.0:
24 ; RV32IFD-NEXT: addi sp, sp, -16
25 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
26 ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
27 ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
28 ; RV32IFD-NEXT: call floor@plt
29 ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
30 ; RV32IFD-NEXT: fld ft0, %lo(.LCPI1_0)(a0)
31 ; RV32IFD-NEXT: fmv.d fs0, fa0
32 ; RV32IFD-NEXT: fle.d s0, ft0, fa0
33 ; RV32IFD-NEXT: call __fixdfdi@plt
34 ; RV32IFD-NEXT: mv a2, a0
35 ; RV32IFD-NEXT: bnez s0, .LBB1_2
36 ; RV32IFD-NEXT: # %bb.1:
37 ; RV32IFD-NEXT: li a2, 0
38 ; RV32IFD-NEXT: .LBB1_2:
39 ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1)
40 ; RV32IFD-NEXT: fld ft0, %lo(.LCPI1_1)(a0)
41 ; RV32IFD-NEXT: flt.d a3, ft0, fs0
42 ; RV32IFD-NEXT: li a0, -1
43 ; RV32IFD-NEXT: beqz a3, .LBB1_9
44 ; RV32IFD-NEXT: # %bb.3:
45 ; RV32IFD-NEXT: feq.d a2, fs0, fs0
46 ; RV32IFD-NEXT: beqz a2, .LBB1_10
47 ; RV32IFD-NEXT: .LBB1_4:
48 ; RV32IFD-NEXT: lui a4, 524288
49 ; RV32IFD-NEXT: beqz s0, .LBB1_11
50 ; RV32IFD-NEXT: .LBB1_5:
51 ; RV32IFD-NEXT: bnez a3, .LBB1_12
52 ; RV32IFD-NEXT: .LBB1_6:
53 ; RV32IFD-NEXT: bnez a2, .LBB1_8
54 ; RV32IFD-NEXT: .LBB1_7:
55 ; RV32IFD-NEXT: li a1, 0
56 ; RV32IFD-NEXT: .LBB1_8:
57 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
58 ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
59 ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
60 ; RV32IFD-NEXT: addi sp, sp, 16
61 ; RV32IFD-NEXT: ret
62 ; RV32IFD-NEXT: .LBB1_9:
63 ; RV32IFD-NEXT: mv a0, a2
64 ; RV32IFD-NEXT: feq.d a2, fs0, fs0
65 ; RV32IFD-NEXT: bnez a2, .LBB1_4
66 ; RV32IFD-NEXT: .LBB1_10:
67 ; RV32IFD-NEXT: li a0, 0
68 ; RV32IFD-NEXT: lui a4, 524288
69 ; RV32IFD-NEXT: bnez s0, .LBB1_5
70 ; RV32IFD-NEXT: .LBB1_11:
71 ; RV32IFD-NEXT: lui a1, 524288
72 ; RV32IFD-NEXT: beqz a3, .LBB1_6
73 ; RV32IFD-NEXT: .LBB1_12:
74 ; RV32IFD-NEXT: addi a1, a4, -1
75 ; RV32IFD-NEXT: beqz a2, .LBB1_7
76 ; RV32IFD-NEXT: j .LBB1_8
77 ;
78 ; RV64IFD-LABEL: test_floor_si64:
79 ; RV64IFD: # %bb.0:
80 ; RV64IFD-NEXT: feq.d a0, fa0, fa0
81 ; RV64IFD-NEXT: beqz a0, .LBB1_2
82 ; RV64IFD-NEXT: # %bb.1:
83 ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rdn
84 ; RV64IFD-NEXT: .LBB1_2:
85 ; RV64IFD-NEXT: ret
86 %a = call double @llvm.floor.f64(double %x)
87 %b = call i64 @llvm.fptosi.sat.i64.f64(double %a)
88 ret i64 %b
89 }
91 define signext i32 @test_floor_ui32(double %x) {
92 ; CHECKIFD-LABEL: test_floor_ui32:
93 ; CHECKIFD: # %bb.0:
94 ; CHECKIFD-NEXT: feq.d a0, fa0, fa0
95 ; CHECKIFD-NEXT: beqz a0, .LBB2_2
96 ; CHECKIFD-NEXT: # %bb.1:
97 ; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rdn
98 ; CHECKIFD-NEXT: .LBB2_2:
99 ; CHECKIFD-NEXT: ret
100 %a = call double @llvm.floor.f64(double %x)
101 %b = call i32 @llvm.fptoui.sat.i32.f64(double %a)
102 ret i32 %b
103 }
105 define i64 @test_floor_ui64(double %x) nounwind {
106 ; RV32IFD-LABEL: test_floor_ui64:
107 ; RV32IFD: # %bb.0:
108 ; RV32IFD-NEXT: addi sp, sp, -16
109 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
110 ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
111 ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
112 ; RV32IFD-NEXT: call floor@plt
113 ; RV32IFD-NEXT: fmv.d fs0, fa0
114 ; RV32IFD-NEXT: fcvt.d.w ft0, zero
115 ; RV32IFD-NEXT: fle.d s0, ft0, fa0
116 ; RV32IFD-NEXT: call __fixunsdfdi@plt
117 ; RV32IFD-NEXT: mv a3, a0
118 ; RV32IFD-NEXT: bnez s0, .LBB3_2
119 ; RV32IFD-NEXT: # %bb.1:
120 ; RV32IFD-NEXT: li a3, 0
121 ; RV32IFD-NEXT: .LBB3_2:
122 ; RV32IFD-NEXT: lui a0, %hi(.LCPI3_0)
123 ; RV32IFD-NEXT: fld ft0, %lo(.LCPI3_0)(a0)
124 ; RV32IFD-NEXT: flt.d a4, ft0, fs0
125 ; RV32IFD-NEXT: li a2, -1
126 ; RV32IFD-NEXT: li a0, -1
127 ; RV32IFD-NEXT: beqz a4, .LBB3_7
128 ; RV32IFD-NEXT: # %bb.3:
129 ; RV32IFD-NEXT: beqz s0, .LBB3_8
130 ; RV32IFD-NEXT: .LBB3_4:
131 ; RV32IFD-NEXT: bnez a4, .LBB3_6
132 ; RV32IFD-NEXT: .LBB3_5:
133 ; RV32IFD-NEXT: mv a2, a1
134 ; RV32IFD-NEXT: .LBB3_6:
135 ; RV32IFD-NEXT: mv a1, a2
136 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
137 ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
138 ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
139 ; RV32IFD-NEXT: addi sp, sp, 16
140 ; RV32IFD-NEXT: ret
141 ; RV32IFD-NEXT: .LBB3_7:
142 ; RV32IFD-NEXT: mv a0, a3
143 ; RV32IFD-NEXT: bnez s0, .LBB3_4
144 ; RV32IFD-NEXT: .LBB3_8:
145 ; RV32IFD-NEXT: li a1, 0
146 ; RV32IFD-NEXT: beqz a4, .LBB3_5
147 ; RV32IFD-NEXT: j .LBB3_6
148 ;
149 ; RV64IFD-LABEL: test_floor_ui64:
150 ; RV64IFD: # %bb.0:
151 ; RV64IFD-NEXT: feq.d a0, fa0, fa0
152 ; RV64IFD-NEXT: beqz a0, .LBB3_2
153 ; RV64IFD-NEXT: # %bb.1:
154 ; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rdn
155 ; RV64IFD-NEXT: .LBB3_2:
156 ; RV64IFD-NEXT: ret
157 %a = call double @llvm.floor.f64(double %x)
158 %b = call i64 @llvm.fptoui.sat.i64.f64(double %a)
159 ret i64 %b
160 }
162 define signext i32 @test_ceil_si32(double %x) {
163 ; CHECKIFD-LABEL: test_ceil_si32:
164 ; CHECKIFD: # %bb.0:
165 ; CHECKIFD-NEXT: feq.d a0, fa0, fa0
166 ; CHECKIFD-NEXT: beqz a0, .LBB4_2
167 ; CHECKIFD-NEXT: # %bb.1:
168 ; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rup
169 ; CHECKIFD-NEXT: .LBB4_2:
170 ; CHECKIFD-NEXT: ret
171 %a = call double @llvm.ceil.f64(double %x)
172 %b = call i32 @llvm.fptosi.sat.i32.f64(double %a)
173 ret i32 %b
174 }
176 define i64 @test_ceil_si64(double %x) nounwind {
177 ; RV32IFD-LABEL: test_ceil_si64:
178 ; RV32IFD: # %bb.0:
179 ; RV32IFD-NEXT: addi sp, sp, -16
180 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
181 ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
182 ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
183 ; RV32IFD-NEXT: call ceil@plt
184 ; RV32IFD-NEXT: lui a0, %hi(.LCPI5_0)
185 ; RV32IFD-NEXT: fld ft0, %lo(.LCPI5_0)(a0)
186 ; RV32IFD-NEXT: fmv.d fs0, fa0
187 ; RV32IFD-NEXT: fle.d s0, ft0, fa0
188 ; RV32IFD-NEXT: call __fixdfdi@plt
189 ; RV32IFD-NEXT: mv a2, a0
190 ; RV32IFD-NEXT: bnez s0, .LBB5_2
191 ; RV32IFD-NEXT: # %bb.1:
192 ; RV32IFD-NEXT: li a2, 0
193 ; RV32IFD-NEXT: .LBB5_2:
194 ; RV32IFD-NEXT: lui a0, %hi(.LCPI5_1)
195 ; RV32IFD-NEXT: fld ft0, %lo(.LCPI5_1)(a0)
196 ; RV32IFD-NEXT: flt.d a3, ft0, fs0
197 ; RV32IFD-NEXT: li a0, -1
198 ; RV32IFD-NEXT: beqz a3, .LBB5_9
199 ; RV32IFD-NEXT: # %bb.3:
200 ; RV32IFD-NEXT: feq.d a2, fs0, fs0
201 ; RV32IFD-NEXT: beqz a2, .LBB5_10
202 ; RV32IFD-NEXT: .LBB5_4:
203 ; RV32IFD-NEXT: lui a4, 524288
204 ; RV32IFD-NEXT: beqz s0, .LBB5_11
205 ; RV32IFD-NEXT: .LBB5_5:
206 ; RV32IFD-NEXT: bnez a3, .LBB5_12
207 ; RV32IFD-NEXT: .LBB5_6:
208 ; RV32IFD-NEXT: bnez a2, .LBB5_8
209 ; RV32IFD-NEXT: .LBB5_7:
210 ; RV32IFD-NEXT: li a1, 0
211 ; RV32IFD-NEXT: .LBB5_8:
212 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
213 ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
214 ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
215 ; RV32IFD-NEXT: addi sp, sp, 16
216 ; RV32IFD-NEXT: ret
217 ; RV32IFD-NEXT: .LBB5_9:
218 ; RV32IFD-NEXT: mv a0, a2
219 ; RV32IFD-NEXT: feq.d a2, fs0, fs0
220 ; RV32IFD-NEXT: bnez a2, .LBB5_4
221 ; RV32IFD-NEXT: .LBB5_10:
222 ; RV32IFD-NEXT: li a0, 0
223 ; RV32IFD-NEXT: lui a4, 524288
224 ; RV32IFD-NEXT: bnez s0, .LBB5_5
225 ; RV32IFD-NEXT: .LBB5_11:
226 ; RV32IFD-NEXT: lui a1, 524288
227 ; RV32IFD-NEXT: beqz a3, .LBB5_6
228 ; RV32IFD-NEXT: .LBB5_12:
229 ; RV32IFD-NEXT: addi a1, a4, -1
230 ; RV32IFD-NEXT: beqz a2, .LBB5_7
231 ; RV32IFD-NEXT: j .LBB5_8
232 ;
233 ; RV64IFD-LABEL: test_ceil_si64:
234 ; RV64IFD: # %bb.0:
235 ; RV64IFD-NEXT: feq.d a0, fa0, fa0
236 ; RV64IFD-NEXT: beqz a0, .LBB5_2
237 ; RV64IFD-NEXT: # %bb.1:
238 ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rup
239 ; RV64IFD-NEXT: .LBB5_2:
240 ; RV64IFD-NEXT: ret
241 %a = call double @llvm.ceil.f64(double %x)
242 %b = call i64 @llvm.fptosi.sat.i64.f64(double %a)
243 ret i64 %b
244 }
246 define signext i32 @test_ceil_ui32(double %x) {
247 ; CHECKIFD-LABEL: test_ceil_ui32:
248 ; CHECKIFD: # %bb.0:
249 ; CHECKIFD-NEXT: feq.d a0, fa0, fa0
250 ; CHECKIFD-NEXT: beqz a0, .LBB6_2
251 ; CHECKIFD-NEXT: # %bb.1:
252 ; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rup
253 ; CHECKIFD-NEXT: .LBB6_2:
254 ; CHECKIFD-NEXT: ret
255 %a = call double @llvm.ceil.f64(double %x)
256 %b = call i32 @llvm.fptoui.sat.i32.f64(double %a)
257 ret i32 %b
258 }
260 define i64 @test_ceil_ui64(double %x) nounwind {
261 ; RV32IFD-LABEL: test_ceil_ui64:
262 ; RV32IFD: # %bb.0:
263 ; RV32IFD-NEXT: addi sp, sp, -16
264 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
265 ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
266 ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
267 ; RV32IFD-NEXT: call ceil@plt
268 ; RV32IFD-NEXT: fmv.d fs0, fa0
269 ; RV32IFD-NEXT: fcvt.d.w ft0, zero
270 ; RV32IFD-NEXT: fle.d s0, ft0, fa0
271 ; RV32IFD-NEXT: call __fixunsdfdi@plt
272 ; RV32IFD-NEXT: mv a3, a0
273 ; RV32IFD-NEXT: bnez s0, .LBB7_2
274 ; RV32IFD-NEXT: # %bb.1:
275 ; RV32IFD-NEXT: li a3, 0
276 ; RV32IFD-NEXT: .LBB7_2:
277 ; RV32IFD-NEXT: lui a0, %hi(.LCPI7_0)
278 ; RV32IFD-NEXT: fld ft0, %lo(.LCPI7_0)(a0)
279 ; RV32IFD-NEXT: flt.d a4, ft0, fs0
280 ; RV32IFD-NEXT: li a2, -1
281 ; RV32IFD-NEXT: li a0, -1
282 ; RV32IFD-NEXT: beqz a4, .LBB7_7
283 ; RV32IFD-NEXT: # %bb.3:
284 ; RV32IFD-NEXT: beqz s0, .LBB7_8
285 ; RV32IFD-NEXT: .LBB7_4:
286 ; RV32IFD-NEXT: bnez a4, .LBB7_6
287 ; RV32IFD-NEXT: .LBB7_5:
288 ; RV32IFD-NEXT: mv a2, a1
289 ; RV32IFD-NEXT: .LBB7_6:
290 ; RV32IFD-NEXT: mv a1, a2
291 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
292 ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
293 ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
294 ; RV32IFD-NEXT: addi sp, sp, 16
295 ; RV32IFD-NEXT: ret
296 ; RV32IFD-NEXT: .LBB7_7:
297 ; RV32IFD-NEXT: mv a0, a3
298 ; RV32IFD-NEXT: bnez s0, .LBB7_4
299 ; RV32IFD-NEXT: .LBB7_8:
300 ; RV32IFD-NEXT: li a1, 0
301 ; RV32IFD-NEXT: beqz a4, .LBB7_5
302 ; RV32IFD-NEXT: j .LBB7_6
303 ;
304 ; RV64IFD-LABEL: test_ceil_ui64:
305 ; RV64IFD: # %bb.0:
306 ; RV64IFD-NEXT: feq.d a0, fa0, fa0
307 ; RV64IFD-NEXT: beqz a0, .LBB7_2
308 ; RV64IFD-NEXT: # %bb.1:
309 ; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rup
310 ; RV64IFD-NEXT: .LBB7_2:
311 ; RV64IFD-NEXT: ret
312 %a = call double @llvm.ceil.f64(double %x)
313 %b = call i64 @llvm.fptoui.sat.i64.f64(double %a)
314 ret i64 %b
315 }
317 define signext i32 @test_trunc_si32(double %x) {
318 ; CHECKIFD-LABEL: test_trunc_si32:
319 ; CHECKIFD: # %bb.0:
320 ; CHECKIFD-NEXT: feq.d a0, fa0, fa0
321 ; CHECKIFD-NEXT: beqz a0, .LBB8_2
322 ; CHECKIFD-NEXT: # %bb.1:
323 ; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rtz
324 ; CHECKIFD-NEXT: .LBB8_2:
325 ; CHECKIFD-NEXT: ret
326 %a = call double @llvm.trunc.f64(double %x)
327 %b = call i32 @llvm.fptosi.sat.i32.f64(double %a)
328 ret i32 %b
329 }
331 define i64 @test_trunc_si64(double %x) nounwind {
332 ; RV32IFD-LABEL: test_trunc_si64:
333 ; RV32IFD: # %bb.0:
334 ; RV32IFD-NEXT: addi sp, sp, -16
335 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
336 ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
337 ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
338 ; RV32IFD-NEXT: call trunc@plt
339 ; RV32IFD-NEXT: lui a0, %hi(.LCPI9_0)
340 ; RV32IFD-NEXT: fld ft0, %lo(.LCPI9_0)(a0)
341 ; RV32IFD-NEXT: fmv.d fs0, fa0
342 ; RV32IFD-NEXT: fle.d s0, ft0, fa0
343 ; RV32IFD-NEXT: call __fixdfdi@plt
344 ; RV32IFD-NEXT: mv a2, a0
345 ; RV32IFD-NEXT: bnez s0, .LBB9_2
346 ; RV32IFD-NEXT: # %bb.1:
347 ; RV32IFD-NEXT: li a2, 0
348 ; RV32IFD-NEXT: .LBB9_2:
349 ; RV32IFD-NEXT: lui a0, %hi(.LCPI9_1)
350 ; RV32IFD-NEXT: fld ft0, %lo(.LCPI9_1)(a0)
351 ; RV32IFD-NEXT: flt.d a3, ft0, fs0
352 ; RV32IFD-NEXT: li a0, -1
353 ; RV32IFD-NEXT: beqz a3, .LBB9_9
354 ; RV32IFD-NEXT: # %bb.3:
355 ; RV32IFD-NEXT: feq.d a2, fs0, fs0
356 ; RV32IFD-NEXT: beqz a2, .LBB9_10
357 ; RV32IFD-NEXT: .LBB9_4:
358 ; RV32IFD-NEXT: lui a4, 524288
359 ; RV32IFD-NEXT: beqz s0, .LBB9_11
360 ; RV32IFD-NEXT: .LBB9_5:
361 ; RV32IFD-NEXT: bnez a3, .LBB9_12
362 ; RV32IFD-NEXT: .LBB9_6:
363 ; RV32IFD-NEXT: bnez a2, .LBB9_8
364 ; RV32IFD-NEXT: .LBB9_7:
365 ; RV32IFD-NEXT: li a1, 0
366 ; RV32IFD-NEXT: .LBB9_8:
367 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
368 ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
369 ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
370 ; RV32IFD-NEXT: addi sp, sp, 16
371 ; RV32IFD-NEXT: ret
372 ; RV32IFD-NEXT: .LBB9_9:
373 ; RV32IFD-NEXT: mv a0, a2
374 ; RV32IFD-NEXT: feq.d a2, fs0, fs0
375 ; RV32IFD-NEXT: bnez a2, .LBB9_4
376 ; RV32IFD-NEXT: .LBB9_10:
377 ; RV32IFD-NEXT: li a0, 0
378 ; RV32IFD-NEXT: lui a4, 524288
379 ; RV32IFD-NEXT: bnez s0, .LBB9_5
380 ; RV32IFD-NEXT: .LBB9_11:
381 ; RV32IFD-NEXT: lui a1, 524288
382 ; RV32IFD-NEXT: beqz a3, .LBB9_6
383 ; RV32IFD-NEXT: .LBB9_12:
384 ; RV32IFD-NEXT: addi a1, a4, -1
385 ; RV32IFD-NEXT: beqz a2, .LBB9_7
386 ; RV32IFD-NEXT: j .LBB9_8
387 ;
388 ; RV64IFD-LABEL: test_trunc_si64:
389 ; RV64IFD: # %bb.0:
390 ; RV64IFD-NEXT: feq.d a0, fa0, fa0
391 ; RV64IFD-NEXT: beqz a0, .LBB9_2
392 ; RV64IFD-NEXT: # %bb.1:
393 ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz
394 ; RV64IFD-NEXT: .LBB9_2:
395 ; RV64IFD-NEXT: ret
396 %a = call double @llvm.trunc.f64(double %x)
397 %b = call i64 @llvm.fptosi.sat.i64.f64(double %a)
398 ret i64 %b
399 }
401 define signext i32 @test_trunc_ui32(double %x) {
402 ; CHECKIFD-LABEL: test_trunc_ui32:
403 ; CHECKIFD: # %bb.0:
404 ; CHECKIFD-NEXT: feq.d a0, fa0, fa0
405 ; CHECKIFD-NEXT: beqz a0, .LBB10_2
406 ; CHECKIFD-NEXT: # %bb.1:
407 ; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rtz
408 ; CHECKIFD-NEXT: .LBB10_2:
409 ; CHECKIFD-NEXT: ret
410 %a = call double @llvm.trunc.f64(double %x)
411 %b = call i32 @llvm.fptoui.sat.i32.f64(double %a)
412 ret i32 %b
413 }
415 define i64 @test_trunc_ui64(double %x) nounwind {
416 ; RV32IFD-LABEL: test_trunc_ui64:
417 ; RV32IFD: # %bb.0:
418 ; RV32IFD-NEXT: addi sp, sp, -16
419 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
420 ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
421 ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
422 ; RV32IFD-NEXT: call trunc@plt
423 ; RV32IFD-NEXT: fmv.d fs0, fa0
424 ; RV32IFD-NEXT: fcvt.d.w ft0, zero
425 ; RV32IFD-NEXT: fle.d s0, ft0, fa0
426 ; RV32IFD-NEXT: call __fixunsdfdi@plt
427 ; RV32IFD-NEXT: mv a3, a0
428 ; RV32IFD-NEXT: bnez s0, .LBB11_2
429 ; RV32IFD-NEXT: # %bb.1:
430 ; RV32IFD-NEXT: li a3, 0
431 ; RV32IFD-NEXT: .LBB11_2:
432 ; RV32IFD-NEXT: lui a0, %hi(.LCPI11_0)
433 ; RV32IFD-NEXT: fld ft0, %lo(.LCPI11_0)(a0)
434 ; RV32IFD-NEXT: flt.d a4, ft0, fs0
435 ; RV32IFD-NEXT: li a2, -1
436 ; RV32IFD-NEXT: li a0, -1
437 ; RV32IFD-NEXT: beqz a4, .LBB11_7
438 ; RV32IFD-NEXT: # %bb.3:
439 ; RV32IFD-NEXT: beqz s0, .LBB11_8
440 ; RV32IFD-NEXT: .LBB11_4:
441 ; RV32IFD-NEXT: bnez a4, .LBB11_6
442 ; RV32IFD-NEXT: .LBB11_5:
443 ; RV32IFD-NEXT: mv a2, a1
444 ; RV32IFD-NEXT: .LBB11_6:
445 ; RV32IFD-NEXT: mv a1, a2
446 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
447 ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
448 ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
449 ; RV32IFD-NEXT: addi sp, sp, 16
450 ; RV32IFD-NEXT: ret
451 ; RV32IFD-NEXT: .LBB11_7:
452 ; RV32IFD-NEXT: mv a0, a3
453 ; RV32IFD-NEXT: bnez s0, .LBB11_4
454 ; RV32IFD-NEXT: .LBB11_8:
455 ; RV32IFD-NEXT: li a1, 0
456 ; RV32IFD-NEXT: beqz a4, .LBB11_5
457 ; RV32IFD-NEXT: j .LBB11_6
458 ;
459 ; RV64IFD-LABEL: test_trunc_ui64:
460 ; RV64IFD: # %bb.0:
461 ; RV64IFD-NEXT: feq.d a0, fa0, fa0
462 ; RV64IFD-NEXT: beqz a0, .LBB11_2
463 ; RV64IFD-NEXT: # %bb.1:
464 ; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rtz
465 ; RV64IFD-NEXT: .LBB11_2:
466 ; RV64IFD-NEXT: ret
467 %a = call double @llvm.trunc.f64(double %x)
468 %b = call i64 @llvm.fptoui.sat.i64.f64(double %a)
469 ret i64 %b
470 }
472 define signext i32 @test_round_si32(double %x) {
473 ; CHECKIFD-LABEL: test_round_si32:
474 ; CHECKIFD: # %bb.0:
475 ; CHECKIFD-NEXT: feq.d a0, fa0, fa0
476 ; CHECKIFD-NEXT: beqz a0, .LBB12_2
477 ; CHECKIFD-NEXT: # %bb.1:
478 ; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rmm
479 ; CHECKIFD-NEXT: .LBB12_2:
480 ; CHECKIFD-NEXT: ret
481 %a = call double @llvm.round.f64(double %x)
482 %b = call i32 @llvm.fptosi.sat.i32.f64(double %a)
483 ret i32 %b
484 }
486 define i64 @test_round_si64(double %x) nounwind {
487 ; RV32IFD-LABEL: test_round_si64:
488 ; RV32IFD: # %bb.0:
489 ; RV32IFD-NEXT: addi sp, sp, -16
490 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
491 ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
492 ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
493 ; RV32IFD-NEXT: call round@plt
494 ; RV32IFD-NEXT: lui a0, %hi(.LCPI13_0)
495 ; RV32IFD-NEXT: fld ft0, %lo(.LCPI13_0)(a0)
496 ; RV32IFD-NEXT: fmv.d fs0, fa0
497 ; RV32IFD-NEXT: fle.d s0, ft0, fa0
498 ; RV32IFD-NEXT: call __fixdfdi@plt
499 ; RV32IFD-NEXT: mv a2, a0
500 ; RV32IFD-NEXT: bnez s0, .LBB13_2
501 ; RV32IFD-NEXT: # %bb.1:
502 ; RV32IFD-NEXT: li a2, 0
503 ; RV32IFD-NEXT: .LBB13_2:
504 ; RV32IFD-NEXT: lui a0, %hi(.LCPI13_1)
505 ; RV32IFD-NEXT: fld ft0, %lo(.LCPI13_1)(a0)
506 ; RV32IFD-NEXT: flt.d a3, ft0, fs0
507 ; RV32IFD-NEXT: li a0, -1
508 ; RV32IFD-NEXT: beqz a3, .LBB13_9
509 ; RV32IFD-NEXT: # %bb.3:
510 ; RV32IFD-NEXT: feq.d a2, fs0, fs0
511 ; RV32IFD-NEXT: beqz a2, .LBB13_10
512 ; RV32IFD-NEXT: .LBB13_4:
513 ; RV32IFD-NEXT: lui a4, 524288
514 ; RV32IFD-NEXT: beqz s0, .LBB13_11
515 ; RV32IFD-NEXT: .LBB13_5:
516 ; RV32IFD-NEXT: bnez a3, .LBB13_12
517 ; RV32IFD-NEXT: .LBB13_6:
518 ; RV32IFD-NEXT: bnez a2, .LBB13_8
519 ; RV32IFD-NEXT: .LBB13_7:
520 ; RV32IFD-NEXT: li a1, 0
521 ; RV32IFD-NEXT: .LBB13_8:
522 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
523 ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
524 ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
525 ; RV32IFD-NEXT: addi sp, sp, 16
526 ; RV32IFD-NEXT: ret
527 ; RV32IFD-NEXT: .LBB13_9:
528 ; RV32IFD-NEXT: mv a0, a2
529 ; RV32IFD-NEXT: feq.d a2, fs0, fs0
530 ; RV32IFD-NEXT: bnez a2, .LBB13_4
531 ; RV32IFD-NEXT: .LBB13_10:
532 ; RV32IFD-NEXT: li a0, 0
533 ; RV32IFD-NEXT: lui a4, 524288
534 ; RV32IFD-NEXT: bnez s0, .LBB13_5
535 ; RV32IFD-NEXT: .LBB13_11:
536 ; RV32IFD-NEXT: lui a1, 524288
537 ; RV32IFD-NEXT: beqz a3, .LBB13_6
538 ; RV32IFD-NEXT: .LBB13_12:
539 ; RV32IFD-NEXT: addi a1, a4, -1
540 ; RV32IFD-NEXT: beqz a2, .LBB13_7
541 ; RV32IFD-NEXT: j .LBB13_8
542 ;
543 ; RV64IFD-LABEL: test_round_si64:
544 ; RV64IFD: # %bb.0:
545 ; RV64IFD-NEXT: feq.d a0, fa0, fa0
546 ; RV64IFD-NEXT: beqz a0, .LBB13_2
547 ; RV64IFD-NEXT: # %bb.1:
548 ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rmm
549 ; RV64IFD-NEXT: .LBB13_2:
550 ; RV64IFD-NEXT: ret
551 %a = call double @llvm.round.f64(double %x)
552 %b = call i64 @llvm.fptosi.sat.i64.f64(double %a)
553 ret i64 %b
554 }
556 define signext i32 @test_round_ui32(double %x) {
557 ; CHECKIFD-LABEL: test_round_ui32:
558 ; CHECKIFD: # %bb.0:
559 ; CHECKIFD-NEXT: feq.d a0, fa0, fa0
560 ; CHECKIFD-NEXT: beqz a0, .LBB14_2
561 ; CHECKIFD-NEXT: # %bb.1:
562 ; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rmm
563 ; CHECKIFD-NEXT: .LBB14_2:
564 ; CHECKIFD-NEXT: ret
565 %a = call double @llvm.round.f64(double %x)
566 %b = call i32 @llvm.fptoui.sat.i32.f64(double %a)
567 ret i32 %b
568 }
570 define i64 @test_round_ui64(double %x) nounwind {
571 ; RV32IFD-LABEL: test_round_ui64:
572 ; RV32IFD: # %bb.0:
573 ; RV32IFD-NEXT: addi sp, sp, -16
574 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
575 ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
576 ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
577 ; RV32IFD-NEXT: call round@plt
578 ; RV32IFD-NEXT: fmv.d fs0, fa0
579 ; RV32IFD-NEXT: fcvt.d.w ft0, zero
580 ; RV32IFD-NEXT: fle.d s0, ft0, fa0
581 ; RV32IFD-NEXT: call __fixunsdfdi@plt
582 ; RV32IFD-NEXT: mv a3, a0
583 ; RV32IFD-NEXT: bnez s0, .LBB15_2
584 ; RV32IFD-NEXT: # %bb.1:
585 ; RV32IFD-NEXT: li a3, 0
586 ; RV32IFD-NEXT: .LBB15_2:
587 ; RV32IFD-NEXT: lui a0, %hi(.LCPI15_0)
588 ; RV32IFD-NEXT: fld ft0, %lo(.LCPI15_0)(a0)
589 ; RV32IFD-NEXT: flt.d a4, ft0, fs0
590 ; RV32IFD-NEXT: li a2, -1
591 ; RV32IFD-NEXT: li a0, -1
592 ; RV32IFD-NEXT: beqz a4, .LBB15_7
593 ; RV32IFD-NEXT: # %bb.3:
594 ; RV32IFD-NEXT: beqz s0, .LBB15_8
595 ; RV32IFD-NEXT: .LBB15_4:
596 ; RV32IFD-NEXT: bnez a4, .LBB15_6
597 ; RV32IFD-NEXT: .LBB15_5:
598 ; RV32IFD-NEXT: mv a2, a1
599 ; RV32IFD-NEXT: .LBB15_6:
600 ; RV32IFD-NEXT: mv a1, a2
601 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
602 ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
603 ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
604 ; RV32IFD-NEXT: addi sp, sp, 16
605 ; RV32IFD-NEXT: ret
606 ; RV32IFD-NEXT: .LBB15_7:
607 ; RV32IFD-NEXT: mv a0, a3
608 ; RV32IFD-NEXT: bnez s0, .LBB15_4
609 ; RV32IFD-NEXT: .LBB15_8:
610 ; RV32IFD-NEXT: li a1, 0
611 ; RV32IFD-NEXT: beqz a4, .LBB15_5
612 ; RV32IFD-NEXT: j .LBB15_6
613 ;
614 ; RV64IFD-LABEL: test_round_ui64:
615 ; RV64IFD: # %bb.0:
616 ; RV64IFD-NEXT: feq.d a0, fa0, fa0
617 ; RV64IFD-NEXT: beqz a0, .LBB15_2
618 ; RV64IFD-NEXT: # %bb.1:
619 ; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rmm
620 ; RV64IFD-NEXT: .LBB15_2:
621 ; RV64IFD-NEXT: ret
622 %a = call double @llvm.round.f64(double %x)
623 %b = call i64 @llvm.fptoui.sat.i64.f64(double %a)
624 ret i64 %b
625 }
627 define signext i32 @test_roundeven_si32(double %x) {
628 ; CHECKIFD-LABEL: test_roundeven_si32:
629 ; CHECKIFD: # %bb.0:
630 ; CHECKIFD-NEXT: feq.d a0, fa0, fa0
631 ; CHECKIFD-NEXT: beqz a0, .LBB16_2
632 ; CHECKIFD-NEXT: # %bb.1:
633 ; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rne
634 ; CHECKIFD-NEXT: .LBB16_2:
635 ; CHECKIFD-NEXT: ret
636 %a = call double @llvm.roundeven.f64(double %x)
637 %b = call i32 @llvm.fptosi.sat.i32.f64(double %a)
638 ret i32 %b
639 }
641 define i64 @test_roundeven_si64(double %x) nounwind {
642 ; RV32IFD-LABEL: test_roundeven_si64:
643 ; RV32IFD: # %bb.0:
644 ; RV32IFD-NEXT: addi sp, sp, -16
645 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
646 ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
647 ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
648 ; RV32IFD-NEXT: call roundeven@plt
649 ; RV32IFD-NEXT: lui a0, %hi(.LCPI17_0)
650 ; RV32IFD-NEXT: fld ft0, %lo(.LCPI17_0)(a0)
651 ; RV32IFD-NEXT: fmv.d fs0, fa0
652 ; RV32IFD-NEXT: fle.d s0, ft0, fa0
653 ; RV32IFD-NEXT: call __fixdfdi@plt
654 ; RV32IFD-NEXT: mv a2, a0
655 ; RV32IFD-NEXT: bnez s0, .LBB17_2
656 ; RV32IFD-NEXT: # %bb.1:
657 ; RV32IFD-NEXT: li a2, 0
658 ; RV32IFD-NEXT: .LBB17_2:
659 ; RV32IFD-NEXT: lui a0, %hi(.LCPI17_1)
660 ; RV32IFD-NEXT: fld ft0, %lo(.LCPI17_1)(a0)
661 ; RV32IFD-NEXT: flt.d a3, ft0, fs0
662 ; RV32IFD-NEXT: li a0, -1
663 ; RV32IFD-NEXT: beqz a3, .LBB17_9
664 ; RV32IFD-NEXT: # %bb.3:
665 ; RV32IFD-NEXT: feq.d a2, fs0, fs0
666 ; RV32IFD-NEXT: beqz a2, .LBB17_10
667 ; RV32IFD-NEXT: .LBB17_4:
668 ; RV32IFD-NEXT: lui a4, 524288
669 ; RV32IFD-NEXT: beqz s0, .LBB17_11
670 ; RV32IFD-NEXT: .LBB17_5:
671 ; RV32IFD-NEXT: bnez a3, .LBB17_12
672 ; RV32IFD-NEXT: .LBB17_6:
673 ; RV32IFD-NEXT: bnez a2, .LBB17_8
674 ; RV32IFD-NEXT: .LBB17_7:
675 ; RV32IFD-NEXT: li a1, 0
676 ; RV32IFD-NEXT: .LBB17_8:
677 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
678 ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
679 ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
680 ; RV32IFD-NEXT: addi sp, sp, 16
681 ; RV32IFD-NEXT: ret
682 ; RV32IFD-NEXT: .LBB17_9:
683 ; RV32IFD-NEXT: mv a0, a2
684 ; RV32IFD-NEXT: feq.d a2, fs0, fs0
685 ; RV32IFD-NEXT: bnez a2, .LBB17_4
686 ; RV32IFD-NEXT: .LBB17_10:
687 ; RV32IFD-NEXT: li a0, 0
688 ; RV32IFD-NEXT: lui a4, 524288
689 ; RV32IFD-NEXT: bnez s0, .LBB17_5
690 ; RV32IFD-NEXT: .LBB17_11:
691 ; RV32IFD-NEXT: lui a1, 524288
692 ; RV32IFD-NEXT: beqz a3, .LBB17_6
693 ; RV32IFD-NEXT: .LBB17_12:
694 ; RV32IFD-NEXT: addi a1, a4, -1
695 ; RV32IFD-NEXT: beqz a2, .LBB17_7
696 ; RV32IFD-NEXT: j .LBB17_8
697 ;
698 ; RV64IFD-LABEL: test_roundeven_si64:
699 ; RV64IFD: # %bb.0:
700 ; RV64IFD-NEXT: feq.d a0, fa0, fa0
701 ; RV64IFD-NEXT: beqz a0, .LBB17_2
702 ; RV64IFD-NEXT: # %bb.1:
703 ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rne
704 ; RV64IFD-NEXT: .LBB17_2:
705 ; RV64IFD-NEXT: ret
706 %a = call double @llvm.roundeven.f64(double %x)
707 %b = call i64 @llvm.fptosi.sat.i64.f64(double %a)
708 ret i64 %b
709 }
711 define signext i32 @test_roundeven_ui32(double %x) {
712 ; CHECKIFD-LABEL: test_roundeven_ui32:
713 ; CHECKIFD: # %bb.0:
714 ; CHECKIFD-NEXT: feq.d a0, fa0, fa0
715 ; CHECKIFD-NEXT: beqz a0, .LBB18_2
716 ; CHECKIFD-NEXT: # %bb.1:
717 ; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rne
718 ; CHECKIFD-NEXT: .LBB18_2:
719 ; CHECKIFD-NEXT: ret
720 %a = call double @llvm.roundeven.f64(double %x)
721 %b = call i32 @llvm.fptoui.sat.i32.f64(double %a)
722 ret i32 %b
723 }
725 define i64 @test_roundeven_ui64(double %x) nounwind {
726 ; RV32IFD-LABEL: test_roundeven_ui64:
727 ; RV32IFD: # %bb.0:
728 ; RV32IFD-NEXT: addi sp, sp, -16
729 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
730 ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
731 ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
732 ; RV32IFD-NEXT: call roundeven@plt
733 ; RV32IFD-NEXT: fmv.d fs0, fa0
734 ; RV32IFD-NEXT: fcvt.d.w ft0, zero
735 ; RV32IFD-NEXT: fle.d s0, ft0, fa0
736 ; RV32IFD-NEXT: call __fixunsdfdi@plt
737 ; RV32IFD-NEXT: mv a3, a0
738 ; RV32IFD-NEXT: bnez s0, .LBB19_2
739 ; RV32IFD-NEXT: # %bb.1:
740 ; RV32IFD-NEXT: li a3, 0
741 ; RV32IFD-NEXT: .LBB19_2:
742 ; RV32IFD-NEXT: lui a0, %hi(.LCPI19_0)
743 ; RV32IFD-NEXT: fld ft0, %lo(.LCPI19_0)(a0)
744 ; RV32IFD-NEXT: flt.d a4, ft0, fs0
745 ; RV32IFD-NEXT: li a2, -1
746 ; RV32IFD-NEXT: li a0, -1
747 ; RV32IFD-NEXT: beqz a4, .LBB19_7
748 ; RV32IFD-NEXT: # %bb.3:
749 ; RV32IFD-NEXT: beqz s0, .LBB19_8
750 ; RV32IFD-NEXT: .LBB19_4:
751 ; RV32IFD-NEXT: bnez a4, .LBB19_6
752 ; RV32IFD-NEXT: .LBB19_5:
753 ; RV32IFD-NEXT: mv a2, a1
754 ; RV32IFD-NEXT: .LBB19_6:
755 ; RV32IFD-NEXT: mv a1, a2
756 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
757 ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
758 ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
759 ; RV32IFD-NEXT: addi sp, sp, 16
760 ; RV32IFD-NEXT: ret
761 ; RV32IFD-NEXT: .LBB19_7:
762 ; RV32IFD-NEXT: mv a0, a3
763 ; RV32IFD-NEXT: bnez s0, .LBB19_4
764 ; RV32IFD-NEXT: .LBB19_8:
765 ; RV32IFD-NEXT: li a1, 0
766 ; RV32IFD-NEXT: beqz a4, .LBB19_5
767 ; RV32IFD-NEXT: j .LBB19_6
768 ;
769 ; RV64IFD-LABEL: test_roundeven_ui64:
770 ; RV64IFD: # %bb.0:
771 ; RV64IFD-NEXT: feq.d a0, fa0, fa0
772 ; RV64IFD-NEXT: beqz a0, .LBB19_2
773 ; RV64IFD-NEXT: # %bb.1:
774 ; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rne
775 ; RV64IFD-NEXT: .LBB19_2:
776 ; RV64IFD-NEXT: ret
777 %a = call double @llvm.roundeven.f64(double %x)
778 %b = call i64 @llvm.fptoui.sat.i64.f64(double %a)
779 ret i64 %b
780 }
782 declare double @llvm.floor.f64(double)
783 declare double @llvm.ceil.f64(double)
784 declare double @llvm.trunc.f64(double)
785 declare double @llvm.round.f64(double)
786 declare double @llvm.roundeven.f64(double)
787 declare i32 @llvm.fptosi.sat.i32.f64(double)
788 declare i64 @llvm.fptosi.sat.i64.f64(double)
789 declare i32 @llvm.fptoui.sat.i32.f64(double)
790 declare i64 @llvm.fptoui.sat.i64.f64(double)