| blob | caa9f3708324670e8d636b9d3f3d9a1507c1601f |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfh \
3 ; RUN: -verify-machineinstrs -target-abi ilp32f | \
4 ; RUN: FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
5 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfh \
6 ; RUN: -verify-machineinstrs -target-abi lp64f | \
7 ; RUN: FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
8 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
9 ; RUN: -mattr=+zfh -verify-machineinstrs -target-abi ilp32d | \
10 ; RUN: FileCheck -check-prefix=RV32IDZFH %s
11 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
12 ; RUN: -mattr=+zfh -verify-machineinstrs -target-abi lp64d | \
13 ; RUN: FileCheck -check-prefix=RV64IDZFH %s
14 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
15 ; RUN: -verify-machineinstrs | \
16 ; RUN: FileCheck -check-prefix=RV32I %s
17 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
18 ; RUN: -verify-machineinstrs | \
19 ; RUN: FileCheck -check-prefix=RV64I %s
21 declare half @llvm.sqrt.f16(half)
23 define half @sqrt_f16(half %a) nounwind {
24 ; CHECKIZFH-LABEL: sqrt_f16:
25 ; CHECKIZFH: # %bb.0:
26 ; CHECKIZFH-NEXT: fsqrt.h fa0, fa0
27 ; CHECKIZFH-NEXT: ret
28 ;
29 ; RV32IDZFH-LABEL: sqrt_f16:
30 ; RV32IDZFH: # %bb.0:
31 ; RV32IDZFH-NEXT: fsqrt.h fa0, fa0
32 ; RV32IDZFH-NEXT: ret
33 ;
34 ; RV64IDZFH-LABEL: sqrt_f16:
35 ; RV64IDZFH: # %bb.0:
36 ; RV64IDZFH-NEXT: fsqrt.h fa0, fa0
37 ; RV64IDZFH-NEXT: ret
38 ;
39 ; RV32I-LABEL: sqrt_f16:
40 ; RV32I: # %bb.0:
41 ; RV32I-NEXT: addi sp, sp, -16
42 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
43 ; RV32I-NEXT: slli a0, a0, 16
44 ; RV32I-NEXT: srli a0, a0, 16
45 ; RV32I-NEXT: call __extendhfsf2@plt
46 ; RV32I-NEXT: call sqrtf@plt
47 ; RV32I-NEXT: call __truncsfhf2@plt
48 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
49 ; RV32I-NEXT: addi sp, sp, 16
50 ; RV32I-NEXT: ret
51 ;
52 ; RV64I-LABEL: sqrt_f16:
53 ; RV64I: # %bb.0:
54 ; RV64I-NEXT: addi sp, sp, -16
55 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
56 ; RV64I-NEXT: slli a0, a0, 48
57 ; RV64I-NEXT: srli a0, a0, 48
58 ; RV64I-NEXT: call __extendhfsf2@plt
59 ; RV64I-NEXT: call sqrtf@plt
60 ; RV64I-NEXT: call __truncsfhf2@plt
61 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
62 ; RV64I-NEXT: addi sp, sp, 16
63 ; RV64I-NEXT: ret
64 %1 = call half @llvm.sqrt.f16(half %a)
65 ret half %1
66 }
68 declare half @llvm.powi.f16.i32(half, i32)
70 define half @powi_f16(half %a, i32 %b) nounwind {
71 ; RV32IZFH-LABEL: powi_f16:
72 ; RV32IZFH: # %bb.0:
73 ; RV32IZFH-NEXT: addi sp, sp, -16
74 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
75 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
76 ; RV32IZFH-NEXT: call __powisf2@plt
77 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
78 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
79 ; RV32IZFH-NEXT: addi sp, sp, 16
80 ; RV32IZFH-NEXT: ret
81 ;
82 ; RV64IZFH-LABEL: powi_f16:
83 ; RV64IZFH: # %bb.0:
84 ; RV64IZFH-NEXT: addi sp, sp, -16
85 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
86 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
87 ; RV64IZFH-NEXT: sext.w a0, a0
88 ; RV64IZFH-NEXT: call __powisf2@plt
89 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
90 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
91 ; RV64IZFH-NEXT: addi sp, sp, 16
92 ; RV64IZFH-NEXT: ret
93 ;
94 ; RV32IDZFH-LABEL: powi_f16:
95 ; RV32IDZFH: # %bb.0:
96 ; RV32IDZFH-NEXT: addi sp, sp, -16
97 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
98 ; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
99 ; RV32IDZFH-NEXT: call __powisf2@plt
100 ; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
101 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
102 ; RV32IDZFH-NEXT: addi sp, sp, 16
103 ; RV32IDZFH-NEXT: ret
104 ;
105 ; RV64IDZFH-LABEL: powi_f16:
106 ; RV64IDZFH: # %bb.0:
107 ; RV64IDZFH-NEXT: addi sp, sp, -16
108 ; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
109 ; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
110 ; RV64IDZFH-NEXT: sext.w a0, a0
111 ; RV64IDZFH-NEXT: call __powisf2@plt
112 ; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
113 ; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
114 ; RV64IDZFH-NEXT: addi sp, sp, 16
115 ; RV64IDZFH-NEXT: ret
116 ;
117 ; RV32I-LABEL: powi_f16:
118 ; RV32I: # %bb.0:
119 ; RV32I-NEXT: addi sp, sp, -16
120 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
121 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
122 ; RV32I-NEXT: mv s0, a1
123 ; RV32I-NEXT: slli a0, a0, 16
124 ; RV32I-NEXT: srli a0, a0, 16
125 ; RV32I-NEXT: call __extendhfsf2@plt
126 ; RV32I-NEXT: mv a1, s0
127 ; RV32I-NEXT: call __powisf2@plt
128 ; RV32I-NEXT: call __truncsfhf2@plt
129 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
130 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
131 ; RV32I-NEXT: addi sp, sp, 16
132 ; RV32I-NEXT: ret
133 ;
134 ; RV64I-LABEL: powi_f16:
135 ; RV64I: # %bb.0:
136 ; RV64I-NEXT: addi sp, sp, -16
137 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
138 ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
139 ; RV64I-NEXT: mv s0, a1
140 ; RV64I-NEXT: slli a0, a0, 48
141 ; RV64I-NEXT: srli a0, a0, 48
142 ; RV64I-NEXT: call __extendhfsf2@plt
143 ; RV64I-NEXT: sext.w a1, s0
144 ; RV64I-NEXT: call __powisf2@plt
145 ; RV64I-NEXT: call __truncsfhf2@plt
146 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
147 ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
148 ; RV64I-NEXT: addi sp, sp, 16
149 ; RV64I-NEXT: ret
150 %1 = call half @llvm.powi.f16.i32(half %a, i32 %b)
151 ret half %1
152 }
154 declare half @llvm.sin.f16(half)
156 define half @sin_f16(half %a) nounwind {
157 ; RV32IZFH-LABEL: sin_f16:
158 ; RV32IZFH: # %bb.0:
159 ; RV32IZFH-NEXT: addi sp, sp, -16
160 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
161 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
162 ; RV32IZFH-NEXT: call sinf@plt
163 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
164 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
165 ; RV32IZFH-NEXT: addi sp, sp, 16
166 ; RV32IZFH-NEXT: ret
167 ;
168 ; RV64IZFH-LABEL: sin_f16:
169 ; RV64IZFH: # %bb.0:
170 ; RV64IZFH-NEXT: addi sp, sp, -16
171 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
172 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
173 ; RV64IZFH-NEXT: call sinf@plt
174 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
175 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
176 ; RV64IZFH-NEXT: addi sp, sp, 16
177 ; RV64IZFH-NEXT: ret
178 ;
179 ; RV32IDZFH-LABEL: sin_f16:
180 ; RV32IDZFH: # %bb.0:
181 ; RV32IDZFH-NEXT: addi sp, sp, -16
182 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
183 ; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
184 ; RV32IDZFH-NEXT: call sinf@plt
185 ; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
186 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
187 ; RV32IDZFH-NEXT: addi sp, sp, 16
188 ; RV32IDZFH-NEXT: ret
189 ;
190 ; RV64IDZFH-LABEL: sin_f16:
191 ; RV64IDZFH: # %bb.0:
192 ; RV64IDZFH-NEXT: addi sp, sp, -16
193 ; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
194 ; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
195 ; RV64IDZFH-NEXT: call sinf@plt
196 ; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
197 ; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
198 ; RV64IDZFH-NEXT: addi sp, sp, 16
199 ; RV64IDZFH-NEXT: ret
200 ;
201 ; RV32I-LABEL: sin_f16:
202 ; RV32I: # %bb.0:
203 ; RV32I-NEXT: addi sp, sp, -16
204 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
205 ; RV32I-NEXT: slli a0, a0, 16
206 ; RV32I-NEXT: srli a0, a0, 16
207 ; RV32I-NEXT: call __extendhfsf2@plt
208 ; RV32I-NEXT: call sinf@plt
209 ; RV32I-NEXT: call __truncsfhf2@plt
210 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
211 ; RV32I-NEXT: addi sp, sp, 16
212 ; RV32I-NEXT: ret
213 ;
214 ; RV64I-LABEL: sin_f16:
215 ; RV64I: # %bb.0:
216 ; RV64I-NEXT: addi sp, sp, -16
217 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
218 ; RV64I-NEXT: slli a0, a0, 48
219 ; RV64I-NEXT: srli a0, a0, 48
220 ; RV64I-NEXT: call __extendhfsf2@plt
221 ; RV64I-NEXT: call sinf@plt
222 ; RV64I-NEXT: call __truncsfhf2@plt
223 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
224 ; RV64I-NEXT: addi sp, sp, 16
225 ; RV64I-NEXT: ret
226 %1 = call half @llvm.sin.f16(half %a)
227 ret half %1
228 }
230 declare half @llvm.cos.f16(half)
232 define half @cos_f16(half %a) nounwind {
233 ; RV32IZFH-LABEL: cos_f16:
234 ; RV32IZFH: # %bb.0:
235 ; RV32IZFH-NEXT: addi sp, sp, -16
236 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
237 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
238 ; RV32IZFH-NEXT: call cosf@plt
239 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
240 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
241 ; RV32IZFH-NEXT: addi sp, sp, 16
242 ; RV32IZFH-NEXT: ret
243 ;
244 ; RV64IZFH-LABEL: cos_f16:
245 ; RV64IZFH: # %bb.0:
246 ; RV64IZFH-NEXT: addi sp, sp, -16
247 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
248 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
249 ; RV64IZFH-NEXT: call cosf@plt
250 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
251 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
252 ; RV64IZFH-NEXT: addi sp, sp, 16
253 ; RV64IZFH-NEXT: ret
254 ;
255 ; RV32IDZFH-LABEL: cos_f16:
256 ; RV32IDZFH: # %bb.0:
257 ; RV32IDZFH-NEXT: addi sp, sp, -16
258 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
259 ; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
260 ; RV32IDZFH-NEXT: call cosf@plt
261 ; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
262 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
263 ; RV32IDZFH-NEXT: addi sp, sp, 16
264 ; RV32IDZFH-NEXT: ret
265 ;
266 ; RV64IDZFH-LABEL: cos_f16:
267 ; RV64IDZFH: # %bb.0:
268 ; RV64IDZFH-NEXT: addi sp, sp, -16
269 ; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
270 ; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
271 ; RV64IDZFH-NEXT: call cosf@plt
272 ; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
273 ; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
274 ; RV64IDZFH-NEXT: addi sp, sp, 16
275 ; RV64IDZFH-NEXT: ret
276 ;
277 ; RV32I-LABEL: cos_f16:
278 ; RV32I: # %bb.0:
279 ; RV32I-NEXT: addi sp, sp, -16
280 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
281 ; RV32I-NEXT: slli a0, a0, 16
282 ; RV32I-NEXT: srli a0, a0, 16
283 ; RV32I-NEXT: call __extendhfsf2@plt
284 ; RV32I-NEXT: call cosf@plt
285 ; RV32I-NEXT: call __truncsfhf2@plt
286 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
287 ; RV32I-NEXT: addi sp, sp, 16
288 ; RV32I-NEXT: ret
289 ;
290 ; RV64I-LABEL: cos_f16:
291 ; RV64I: # %bb.0:
292 ; RV64I-NEXT: addi sp, sp, -16
293 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
294 ; RV64I-NEXT: slli a0, a0, 48
295 ; RV64I-NEXT: srli a0, a0, 48
296 ; RV64I-NEXT: call __extendhfsf2@plt
297 ; RV64I-NEXT: call cosf@plt
298 ; RV64I-NEXT: call __truncsfhf2@plt
299 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
300 ; RV64I-NEXT: addi sp, sp, 16
301 ; RV64I-NEXT: ret
302 %1 = call half @llvm.cos.f16(half %a)
303 ret half %1
304 }
306 ; The sin+cos combination results in an FSINCOS SelectionDAG node.
307 define half @sincos_f16(half %a) nounwind {
308 ; RV32IZFH-LABEL: sincos_f16:
309 ; RV32IZFH: # %bb.0:
310 ; RV32IZFH-NEXT: addi sp, sp, -16
311 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
312 ; RV32IZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
313 ; RV32IZFH-NEXT: fsw fs1, 4(sp) # 4-byte Folded Spill
314 ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0
315 ; RV32IZFH-NEXT: fmv.s fa0, fs0
316 ; RV32IZFH-NEXT: call sinf@plt
317 ; RV32IZFH-NEXT: fcvt.h.s fs1, fa0
318 ; RV32IZFH-NEXT: fmv.s fa0, fs0
319 ; RV32IZFH-NEXT: call cosf@plt
320 ; RV32IZFH-NEXT: fcvt.h.s ft0, fa0
321 ; RV32IZFH-NEXT: fadd.h fa0, fs1, ft0
322 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
323 ; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
324 ; RV32IZFH-NEXT: flw fs1, 4(sp) # 4-byte Folded Reload
325 ; RV32IZFH-NEXT: addi sp, sp, 16
326 ; RV32IZFH-NEXT: ret
327 ;
328 ; RV64IZFH-LABEL: sincos_f16:
329 ; RV64IZFH: # %bb.0:
330 ; RV64IZFH-NEXT: addi sp, sp, -16
331 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
332 ; RV64IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
333 ; RV64IZFH-NEXT: fsw fs1, 0(sp) # 4-byte Folded Spill
334 ; RV64IZFH-NEXT: fcvt.s.h fs0, fa0
335 ; RV64IZFH-NEXT: fmv.s fa0, fs0
336 ; RV64IZFH-NEXT: call sinf@plt
337 ; RV64IZFH-NEXT: fcvt.h.s fs1, fa0
338 ; RV64IZFH-NEXT: fmv.s fa0, fs0
339 ; RV64IZFH-NEXT: call cosf@plt
340 ; RV64IZFH-NEXT: fcvt.h.s ft0, fa0
341 ; RV64IZFH-NEXT: fadd.h fa0, fs1, ft0
342 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
343 ; RV64IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
344 ; RV64IZFH-NEXT: flw fs1, 0(sp) # 4-byte Folded Reload
345 ; RV64IZFH-NEXT: addi sp, sp, 16
346 ; RV64IZFH-NEXT: ret
347 ;
348 ; RV32IDZFH-LABEL: sincos_f16:
349 ; RV32IDZFH: # %bb.0:
350 ; RV32IDZFH-NEXT: addi sp, sp, -32
351 ; RV32IDZFH-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
352 ; RV32IDZFH-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill
353 ; RV32IDZFH-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill
354 ; RV32IDZFH-NEXT: fcvt.s.h fs0, fa0
355 ; RV32IDZFH-NEXT: fmv.s fa0, fs0
356 ; RV32IDZFH-NEXT: call sinf@plt
357 ; RV32IDZFH-NEXT: fcvt.h.s fs1, fa0
358 ; RV32IDZFH-NEXT: fmv.s fa0, fs0
359 ; RV32IDZFH-NEXT: call cosf@plt
360 ; RV32IDZFH-NEXT: fcvt.h.s ft0, fa0
361 ; RV32IDZFH-NEXT: fadd.h fa0, fs1, ft0
362 ; RV32IDZFH-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
363 ; RV32IDZFH-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
364 ; RV32IDZFH-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload
365 ; RV32IDZFH-NEXT: addi sp, sp, 32
366 ; RV32IDZFH-NEXT: ret
367 ;
368 ; RV64IDZFH-LABEL: sincos_f16:
369 ; RV64IDZFH: # %bb.0:
370 ; RV64IDZFH-NEXT: addi sp, sp, -32
371 ; RV64IDZFH-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
372 ; RV64IDZFH-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill
373 ; RV64IDZFH-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill
374 ; RV64IDZFH-NEXT: fcvt.s.h fs0, fa0
375 ; RV64IDZFH-NEXT: fmv.s fa0, fs0
376 ; RV64IDZFH-NEXT: call sinf@plt
377 ; RV64IDZFH-NEXT: fcvt.h.s fs1, fa0
378 ; RV64IDZFH-NEXT: fmv.s fa0, fs0
379 ; RV64IDZFH-NEXT: call cosf@plt
380 ; RV64IDZFH-NEXT: fcvt.h.s ft0, fa0
381 ; RV64IDZFH-NEXT: fadd.h fa0, fs1, ft0
382 ; RV64IDZFH-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
383 ; RV64IDZFH-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
384 ; RV64IDZFH-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload
385 ; RV64IDZFH-NEXT: addi sp, sp, 32
386 ; RV64IDZFH-NEXT: ret
387 ;
388 ; RV32I-LABEL: sincos_f16:
389 ; RV32I: # %bb.0:
390 ; RV32I-NEXT: addi sp, sp, -16
391 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
392 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
393 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
394 ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
395 ; RV32I-NEXT: lui a1, 16
396 ; RV32I-NEXT: addi s2, a1, -1
397 ; RV32I-NEXT: and a0, a0, s2
398 ; RV32I-NEXT: call __extendhfsf2@plt
399 ; RV32I-NEXT: mv s0, a0
400 ; RV32I-NEXT: call sinf@plt
401 ; RV32I-NEXT: call __truncsfhf2@plt
402 ; RV32I-NEXT: mv s1, a0
403 ; RV32I-NEXT: mv a0, s0
404 ; RV32I-NEXT: call cosf@plt
405 ; RV32I-NEXT: call __truncsfhf2@plt
406 ; RV32I-NEXT: mv s0, a0
407 ; RV32I-NEXT: and a0, s1, s2
408 ; RV32I-NEXT: call __extendhfsf2@plt
409 ; RV32I-NEXT: mv s1, a0
410 ; RV32I-NEXT: and a0, s0, s2
411 ; RV32I-NEXT: call __extendhfsf2@plt
412 ; RV32I-NEXT: mv a1, a0
413 ; RV32I-NEXT: mv a0, s1
414 ; RV32I-NEXT: call __addsf3@plt
415 ; RV32I-NEXT: call __truncsfhf2@plt
416 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
417 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
418 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
419 ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
420 ; RV32I-NEXT: addi sp, sp, 16
421 ; RV32I-NEXT: ret
422 ;
423 ; RV64I-LABEL: sincos_f16:
424 ; RV64I: # %bb.0:
425 ; RV64I-NEXT: addi sp, sp, -32
426 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
427 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
428 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
429 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
430 ; RV64I-NEXT: lui a1, 16
431 ; RV64I-NEXT: addiw s2, a1, -1
432 ; RV64I-NEXT: and a0, a0, s2
433 ; RV64I-NEXT: call __extendhfsf2@plt
434 ; RV64I-NEXT: mv s0, a0
435 ; RV64I-NEXT: call sinf@plt
436 ; RV64I-NEXT: call __truncsfhf2@plt
437 ; RV64I-NEXT: mv s1, a0
438 ; RV64I-NEXT: mv a0, s0
439 ; RV64I-NEXT: call cosf@plt
440 ; RV64I-NEXT: call __truncsfhf2@plt
441 ; RV64I-NEXT: mv s0, a0
442 ; RV64I-NEXT: and a0, s1, s2
443 ; RV64I-NEXT: call __extendhfsf2@plt
444 ; RV64I-NEXT: mv s1, a0
445 ; RV64I-NEXT: and a0, s0, s2
446 ; RV64I-NEXT: call __extendhfsf2@plt
447 ; RV64I-NEXT: mv a1, a0
448 ; RV64I-NEXT: mv a0, s1
449 ; RV64I-NEXT: call __addsf3@plt
450 ; RV64I-NEXT: call __truncsfhf2@plt
451 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
452 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
453 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
454 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
455 ; RV64I-NEXT: addi sp, sp, 32
456 ; RV64I-NEXT: ret
457 %1 = call half @llvm.sin.f16(half %a)
458 %2 = call half @llvm.cos.f16(half %a)
459 %3 = fadd half %1, %2
460 ret half %3
461 }
463 declare half @llvm.pow.f16(half, half)
465 define half @pow_f16(half %a, half %b) nounwind {
466 ; RV32IZFH-LABEL: pow_f16:
467 ; RV32IZFH: # %bb.0:
468 ; RV32IZFH-NEXT: addi sp, sp, -16
469 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
470 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
471 ; RV32IZFH-NEXT: fcvt.s.h fa1, fa1
472 ; RV32IZFH-NEXT: call powf@plt
473 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
474 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
475 ; RV32IZFH-NEXT: addi sp, sp, 16
476 ; RV32IZFH-NEXT: ret
477 ;
478 ; RV64IZFH-LABEL: pow_f16:
479 ; RV64IZFH: # %bb.0:
480 ; RV64IZFH-NEXT: addi sp, sp, -16
481 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
482 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
483 ; RV64IZFH-NEXT: fcvt.s.h fa1, fa1
484 ; RV64IZFH-NEXT: call powf@plt
485 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
486 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
487 ; RV64IZFH-NEXT: addi sp, sp, 16
488 ; RV64IZFH-NEXT: ret
489 ;
490 ; RV32IDZFH-LABEL: pow_f16:
491 ; RV32IDZFH: # %bb.0:
492 ; RV32IDZFH-NEXT: addi sp, sp, -16
493 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
494 ; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
495 ; RV32IDZFH-NEXT: fcvt.s.h fa1, fa1
496 ; RV32IDZFH-NEXT: call powf@plt
497 ; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
498 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
499 ; RV32IDZFH-NEXT: addi sp, sp, 16
500 ; RV32IDZFH-NEXT: ret
501 ;
502 ; RV64IDZFH-LABEL: pow_f16:
503 ; RV64IDZFH: # %bb.0:
504 ; RV64IDZFH-NEXT: addi sp, sp, -16
505 ; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
506 ; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
507 ; RV64IDZFH-NEXT: fcvt.s.h fa1, fa1
508 ; RV64IDZFH-NEXT: call powf@plt
509 ; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
510 ; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
511 ; RV64IDZFH-NEXT: addi sp, sp, 16
512 ; RV64IDZFH-NEXT: ret
513 ;
514 ; RV32I-LABEL: pow_f16:
515 ; RV32I: # %bb.0:
516 ; RV32I-NEXT: addi sp, sp, -16
517 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
518 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
519 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
520 ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
521 ; RV32I-NEXT: mv s0, a1
522 ; RV32I-NEXT: lui a1, 16
523 ; RV32I-NEXT: addi s2, a1, -1
524 ; RV32I-NEXT: and a0, a0, s2
525 ; RV32I-NEXT: call __extendhfsf2@plt
526 ; RV32I-NEXT: mv s1, a0
527 ; RV32I-NEXT: and a0, s0, s2
528 ; RV32I-NEXT: call __extendhfsf2@plt
529 ; RV32I-NEXT: mv a1, a0
530 ; RV32I-NEXT: mv a0, s1
531 ; RV32I-NEXT: call powf@plt
532 ; RV32I-NEXT: call __truncsfhf2@plt
533 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
534 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
535 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
536 ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
537 ; RV32I-NEXT: addi sp, sp, 16
538 ; RV32I-NEXT: ret
539 ;
540 ; RV64I-LABEL: pow_f16:
541 ; RV64I: # %bb.0:
542 ; RV64I-NEXT: addi sp, sp, -32
543 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
544 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
545 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
546 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
547 ; RV64I-NEXT: mv s0, a1
548 ; RV64I-NEXT: lui a1, 16
549 ; RV64I-NEXT: addiw s2, a1, -1
550 ; RV64I-NEXT: and a0, a0, s2
551 ; RV64I-NEXT: call __extendhfsf2@plt
552 ; RV64I-NEXT: mv s1, a0
553 ; RV64I-NEXT: and a0, s0, s2
554 ; RV64I-NEXT: call __extendhfsf2@plt
555 ; RV64I-NEXT: mv a1, a0
556 ; RV64I-NEXT: mv a0, s1
557 ; RV64I-NEXT: call powf@plt
558 ; RV64I-NEXT: call __truncsfhf2@plt
559 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
560 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
561 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
562 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
563 ; RV64I-NEXT: addi sp, sp, 32
564 ; RV64I-NEXT: ret
565 %1 = call half @llvm.pow.f16(half %a, half %b)
566 ret half %1
567 }
569 declare half @llvm.exp.f16(half)
571 define half @exp_f16(half %a) nounwind {
572 ; RV32IZFH-LABEL: exp_f16:
573 ; RV32IZFH: # %bb.0:
574 ; RV32IZFH-NEXT: addi sp, sp, -16
575 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
576 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
577 ; RV32IZFH-NEXT: call expf@plt
578 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
579 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
580 ; RV32IZFH-NEXT: addi sp, sp, 16
581 ; RV32IZFH-NEXT: ret
582 ;
583 ; RV64IZFH-LABEL: exp_f16:
584 ; RV64IZFH: # %bb.0:
585 ; RV64IZFH-NEXT: addi sp, sp, -16
586 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
587 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
588 ; RV64IZFH-NEXT: call expf@plt
589 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
590 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
591 ; RV64IZFH-NEXT: addi sp, sp, 16
592 ; RV64IZFH-NEXT: ret
593 ;
594 ; RV32IDZFH-LABEL: exp_f16:
595 ; RV32IDZFH: # %bb.0:
596 ; RV32IDZFH-NEXT: addi sp, sp, -16
597 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
598 ; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
599 ; RV32IDZFH-NEXT: call expf@plt
600 ; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
601 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
602 ; RV32IDZFH-NEXT: addi sp, sp, 16
603 ; RV32IDZFH-NEXT: ret
604 ;
605 ; RV64IDZFH-LABEL: exp_f16:
606 ; RV64IDZFH: # %bb.0:
607 ; RV64IDZFH-NEXT: addi sp, sp, -16
608 ; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
609 ; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
610 ; RV64IDZFH-NEXT: call expf@plt
611 ; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
612 ; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
613 ; RV64IDZFH-NEXT: addi sp, sp, 16
614 ; RV64IDZFH-NEXT: ret
615 ;
616 ; RV32I-LABEL: exp_f16:
617 ; RV32I: # %bb.0:
618 ; RV32I-NEXT: addi sp, sp, -16
619 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
620 ; RV32I-NEXT: slli a0, a0, 16
621 ; RV32I-NEXT: srli a0, a0, 16
622 ; RV32I-NEXT: call __extendhfsf2@plt
623 ; RV32I-NEXT: call expf@plt
624 ; RV32I-NEXT: call __truncsfhf2@plt
625 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
626 ; RV32I-NEXT: addi sp, sp, 16
627 ; RV32I-NEXT: ret
628 ;
629 ; RV64I-LABEL: exp_f16:
630 ; RV64I: # %bb.0:
631 ; RV64I-NEXT: addi sp, sp, -16
632 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
633 ; RV64I-NEXT: slli a0, a0, 48
634 ; RV64I-NEXT: srli a0, a0, 48
635 ; RV64I-NEXT: call __extendhfsf2@plt
636 ; RV64I-NEXT: call expf@plt
637 ; RV64I-NEXT: call __truncsfhf2@plt
638 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
639 ; RV64I-NEXT: addi sp, sp, 16
640 ; RV64I-NEXT: ret
641 %1 = call half @llvm.exp.f16(half %a)
642 ret half %1
643 }
645 declare half @llvm.exp2.f16(half)
647 define half @exp2_f16(half %a) nounwind {
648 ; RV32IZFH-LABEL: exp2_f16:
649 ; RV32IZFH: # %bb.0:
650 ; RV32IZFH-NEXT: addi sp, sp, -16
651 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
652 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
653 ; RV32IZFH-NEXT: call exp2f@plt
654 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
655 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
656 ; RV32IZFH-NEXT: addi sp, sp, 16
657 ; RV32IZFH-NEXT: ret
658 ;
659 ; RV64IZFH-LABEL: exp2_f16:
660 ; RV64IZFH: # %bb.0:
661 ; RV64IZFH-NEXT: addi sp, sp, -16
662 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
663 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
664 ; RV64IZFH-NEXT: call exp2f@plt
665 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
666 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
667 ; RV64IZFH-NEXT: addi sp, sp, 16
668 ; RV64IZFH-NEXT: ret
669 ;
670 ; RV32IDZFH-LABEL: exp2_f16:
671 ; RV32IDZFH: # %bb.0:
672 ; RV32IDZFH-NEXT: addi sp, sp, -16
673 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
674 ; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
675 ; RV32IDZFH-NEXT: call exp2f@plt
676 ; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
677 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
678 ; RV32IDZFH-NEXT: addi sp, sp, 16
679 ; RV32IDZFH-NEXT: ret
680 ;
681 ; RV64IDZFH-LABEL: exp2_f16:
682 ; RV64IDZFH: # %bb.0:
683 ; RV64IDZFH-NEXT: addi sp, sp, -16
684 ; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
685 ; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
686 ; RV64IDZFH-NEXT: call exp2f@plt
687 ; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
688 ; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
689 ; RV64IDZFH-NEXT: addi sp, sp, 16
690 ; RV64IDZFH-NEXT: ret
691 ;
692 ; RV32I-LABEL: exp2_f16:
693 ; RV32I: # %bb.0:
694 ; RV32I-NEXT: addi sp, sp, -16
695 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
696 ; RV32I-NEXT: slli a0, a0, 16
697 ; RV32I-NEXT: srli a0, a0, 16
698 ; RV32I-NEXT: call __extendhfsf2@plt
699 ; RV32I-NEXT: call exp2f@plt
700 ; RV32I-NEXT: call __truncsfhf2@plt
701 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
702 ; RV32I-NEXT: addi sp, sp, 16
703 ; RV32I-NEXT: ret
704 ;
705 ; RV64I-LABEL: exp2_f16:
706 ; RV64I: # %bb.0:
707 ; RV64I-NEXT: addi sp, sp, -16
708 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
709 ; RV64I-NEXT: slli a0, a0, 48
710 ; RV64I-NEXT: srli a0, a0, 48
711 ; RV64I-NEXT: call __extendhfsf2@plt
712 ; RV64I-NEXT: call exp2f@plt
713 ; RV64I-NEXT: call __truncsfhf2@plt
714 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
715 ; RV64I-NEXT: addi sp, sp, 16
716 ; RV64I-NEXT: ret
717 %1 = call half @llvm.exp2.f16(half %a)
718 ret half %1
719 }
721 declare half @llvm.log.f16(half)
723 define half @log_f16(half %a) nounwind {
724 ; RV32IZFH-LABEL: log_f16:
725 ; RV32IZFH: # %bb.0:
726 ; RV32IZFH-NEXT: addi sp, sp, -16
727 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
728 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
729 ; RV32IZFH-NEXT: call logf@plt
730 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
731 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
732 ; RV32IZFH-NEXT: addi sp, sp, 16
733 ; RV32IZFH-NEXT: ret
734 ;
735 ; RV64IZFH-LABEL: log_f16:
736 ; RV64IZFH: # %bb.0:
737 ; RV64IZFH-NEXT: addi sp, sp, -16
738 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
739 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
740 ; RV64IZFH-NEXT: call logf@plt
741 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
742 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
743 ; RV64IZFH-NEXT: addi sp, sp, 16
744 ; RV64IZFH-NEXT: ret
745 ;
746 ; RV32IDZFH-LABEL: log_f16:
747 ; RV32IDZFH: # %bb.0:
748 ; RV32IDZFH-NEXT: addi sp, sp, -16
749 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
750 ; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
751 ; RV32IDZFH-NEXT: call logf@plt
752 ; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
753 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
754 ; RV32IDZFH-NEXT: addi sp, sp, 16
755 ; RV32IDZFH-NEXT: ret
756 ;
757 ; RV64IDZFH-LABEL: log_f16:
758 ; RV64IDZFH: # %bb.0:
759 ; RV64IDZFH-NEXT: addi sp, sp, -16
760 ; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
761 ; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
762 ; RV64IDZFH-NEXT: call logf@plt
763 ; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
764 ; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
765 ; RV64IDZFH-NEXT: addi sp, sp, 16
766 ; RV64IDZFH-NEXT: ret
767 ;
768 ; RV32I-LABEL: log_f16:
769 ; RV32I: # %bb.0:
770 ; RV32I-NEXT: addi sp, sp, -16
771 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
772 ; RV32I-NEXT: slli a0, a0, 16
773 ; RV32I-NEXT: srli a0, a0, 16
774 ; RV32I-NEXT: call __extendhfsf2@plt
775 ; RV32I-NEXT: call logf@plt
776 ; RV32I-NEXT: call __truncsfhf2@plt
777 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
778 ; RV32I-NEXT: addi sp, sp, 16
779 ; RV32I-NEXT: ret
780 ;
781 ; RV64I-LABEL: log_f16:
782 ; RV64I: # %bb.0:
783 ; RV64I-NEXT: addi sp, sp, -16
784 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
785 ; RV64I-NEXT: slli a0, a0, 48
786 ; RV64I-NEXT: srli a0, a0, 48
787 ; RV64I-NEXT: call __extendhfsf2@plt
788 ; RV64I-NEXT: call logf@plt
789 ; RV64I-NEXT: call __truncsfhf2@plt
790 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
791 ; RV64I-NEXT: addi sp, sp, 16
792 ; RV64I-NEXT: ret
793 %1 = call half @llvm.log.f16(half %a)
794 ret half %1
795 }
797 declare half @llvm.log10.f16(half)
799 define half @log10_f16(half %a) nounwind {
800 ; RV32IZFH-LABEL: log10_f16:
801 ; RV32IZFH: # %bb.0:
802 ; RV32IZFH-NEXT: addi sp, sp, -16
803 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
804 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
805 ; RV32IZFH-NEXT: call log10f@plt
806 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
807 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
808 ; RV32IZFH-NEXT: addi sp, sp, 16
809 ; RV32IZFH-NEXT: ret
810 ;
811 ; RV64IZFH-LABEL: log10_f16:
812 ; RV64IZFH: # %bb.0:
813 ; RV64IZFH-NEXT: addi sp, sp, -16
814 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
815 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
816 ; RV64IZFH-NEXT: call log10f@plt
817 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
818 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
819 ; RV64IZFH-NEXT: addi sp, sp, 16
820 ; RV64IZFH-NEXT: ret
821 ;
822 ; RV32IDZFH-LABEL: log10_f16:
823 ; RV32IDZFH: # %bb.0:
824 ; RV32IDZFH-NEXT: addi sp, sp, -16
825 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
826 ; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
827 ; RV32IDZFH-NEXT: call log10f@plt
828 ; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
829 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
830 ; RV32IDZFH-NEXT: addi sp, sp, 16
831 ; RV32IDZFH-NEXT: ret
832 ;
833 ; RV64IDZFH-LABEL: log10_f16:
834 ; RV64IDZFH: # %bb.0:
835 ; RV64IDZFH-NEXT: addi sp, sp, -16
836 ; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
837 ; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
838 ; RV64IDZFH-NEXT: call log10f@plt
839 ; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
840 ; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
841 ; RV64IDZFH-NEXT: addi sp, sp, 16
842 ; RV64IDZFH-NEXT: ret
843 ;
844 ; RV32I-LABEL: log10_f16:
845 ; RV32I: # %bb.0:
846 ; RV32I-NEXT: addi sp, sp, -16
847 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
848 ; RV32I-NEXT: slli a0, a0, 16
849 ; RV32I-NEXT: srli a0, a0, 16
850 ; RV32I-NEXT: call __extendhfsf2@plt
851 ; RV32I-NEXT: call log10f@plt
852 ; RV32I-NEXT: call __truncsfhf2@plt
853 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
854 ; RV32I-NEXT: addi sp, sp, 16
855 ; RV32I-NEXT: ret
856 ;
857 ; RV64I-LABEL: log10_f16:
858 ; RV64I: # %bb.0:
859 ; RV64I-NEXT: addi sp, sp, -16
860 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
861 ; RV64I-NEXT: slli a0, a0, 48
862 ; RV64I-NEXT: srli a0, a0, 48
863 ; RV64I-NEXT: call __extendhfsf2@plt
864 ; RV64I-NEXT: call log10f@plt
865 ; RV64I-NEXT: call __truncsfhf2@plt
866 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
867 ; RV64I-NEXT: addi sp, sp, 16
868 ; RV64I-NEXT: ret
869 %1 = call half @llvm.log10.f16(half %a)
870 ret half %1
871 }
873 declare half @llvm.log2.f16(half)
875 define half @log2_f16(half %a) nounwind {
876 ; RV32IZFH-LABEL: log2_f16:
877 ; RV32IZFH: # %bb.0:
878 ; RV32IZFH-NEXT: addi sp, sp, -16
879 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
880 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
881 ; RV32IZFH-NEXT: call log2f@plt
882 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
883 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
884 ; RV32IZFH-NEXT: addi sp, sp, 16
885 ; RV32IZFH-NEXT: ret
886 ;
887 ; RV64IZFH-LABEL: log2_f16:
888 ; RV64IZFH: # %bb.0:
889 ; RV64IZFH-NEXT: addi sp, sp, -16
890 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
891 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
892 ; RV64IZFH-NEXT: call log2f@plt
893 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
894 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
895 ; RV64IZFH-NEXT: addi sp, sp, 16
896 ; RV64IZFH-NEXT: ret
897 ;
898 ; RV32IDZFH-LABEL: log2_f16:
899 ; RV32IDZFH: # %bb.0:
900 ; RV32IDZFH-NEXT: addi sp, sp, -16
901 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
902 ; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
903 ; RV32IDZFH-NEXT: call log2f@plt
904 ; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
905 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
906 ; RV32IDZFH-NEXT: addi sp, sp, 16
907 ; RV32IDZFH-NEXT: ret
908 ;
909 ; RV64IDZFH-LABEL: log2_f16:
910 ; RV64IDZFH: # %bb.0:
911 ; RV64IDZFH-NEXT: addi sp, sp, -16
912 ; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
913 ; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
914 ; RV64IDZFH-NEXT: call log2f@plt
915 ; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
916 ; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
917 ; RV64IDZFH-NEXT: addi sp, sp, 16
918 ; RV64IDZFH-NEXT: ret
919 ;
920 ; RV32I-LABEL: log2_f16:
921 ; RV32I: # %bb.0:
922 ; RV32I-NEXT: addi sp, sp, -16
923 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
924 ; RV32I-NEXT: slli a0, a0, 16
925 ; RV32I-NEXT: srli a0, a0, 16
926 ; RV32I-NEXT: call __extendhfsf2@plt
927 ; RV32I-NEXT: call log2f@plt
928 ; RV32I-NEXT: call __truncsfhf2@plt
929 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
930 ; RV32I-NEXT: addi sp, sp, 16
931 ; RV32I-NEXT: ret
932 ;
933 ; RV64I-LABEL: log2_f16:
934 ; RV64I: # %bb.0:
935 ; RV64I-NEXT: addi sp, sp, -16
936 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
937 ; RV64I-NEXT: slli a0, a0, 48
938 ; RV64I-NEXT: srli a0, a0, 48
939 ; RV64I-NEXT: call __extendhfsf2@plt
940 ; RV64I-NEXT: call log2f@plt
941 ; RV64I-NEXT: call __truncsfhf2@plt
942 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
943 ; RV64I-NEXT: addi sp, sp, 16
944 ; RV64I-NEXT: ret
945 %1 = call half @llvm.log2.f16(half %a)
946 ret half %1
947 }
949 declare half @llvm.fma.f16(half, half, half)
951 define half @fma_f16(half %a, half %b, half %c) nounwind {
952 ; CHECKIZFH-LABEL: fma_f16:
953 ; CHECKIZFH: # %bb.0:
954 ; CHECKIZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
955 ; CHECKIZFH-NEXT: ret
956 ;
957 ; RV32IDZFH-LABEL: fma_f16:
958 ; RV32IDZFH: # %bb.0:
959 ; RV32IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
960 ; RV32IDZFH-NEXT: ret
961 ;
962 ; RV64IDZFH-LABEL: fma_f16:
963 ; RV64IDZFH: # %bb.0:
964 ; RV64IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
965 ; RV64IDZFH-NEXT: ret
966 ;
967 ; RV32I-LABEL: fma_f16:
968 ; RV32I: # %bb.0:
969 ; RV32I-NEXT: addi sp, sp, -32
970 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
971 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
972 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
973 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
974 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
975 ; RV32I-NEXT: mv s0, a2
976 ; RV32I-NEXT: mv s1, a1
977 ; RV32I-NEXT: lui a1, 16
978 ; RV32I-NEXT: addi s3, a1, -1
979 ; RV32I-NEXT: and a0, a0, s3
980 ; RV32I-NEXT: call __extendhfsf2@plt
981 ; RV32I-NEXT: mv s2, a0
982 ; RV32I-NEXT: and a0, s1, s3
983 ; RV32I-NEXT: call __extendhfsf2@plt
984 ; RV32I-NEXT: mv s1, a0
985 ; RV32I-NEXT: and a0, s0, s3
986 ; RV32I-NEXT: call __extendhfsf2@plt
987 ; RV32I-NEXT: mv a2, a0
988 ; RV32I-NEXT: mv a0, s2
989 ; RV32I-NEXT: mv a1, s1
990 ; RV32I-NEXT: call fmaf@plt
991 ; RV32I-NEXT: call __truncsfhf2@plt
992 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
993 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
994 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
995 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
996 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
997 ; RV32I-NEXT: addi sp, sp, 32
998 ; RV32I-NEXT: ret
999 ;
1000 ; RV64I-LABEL: fma_f16:
1001 ; RV64I: # %bb.0:
1002 ; RV64I-NEXT: addi sp, sp, -48
1003 ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
1004 ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
1005 ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
1006 ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
1007 ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
1008 ; RV64I-NEXT: mv s0, a2
1009 ; RV64I-NEXT: mv s1, a1
1010 ; RV64I-NEXT: lui a1, 16
1011 ; RV64I-NEXT: addiw s3, a1, -1
1012 ; RV64I-NEXT: and a0, a0, s3
1013 ; RV64I-NEXT: call __extendhfsf2@plt
1014 ; RV64I-NEXT: mv s2, a0
1015 ; RV64I-NEXT: and a0, s1, s3
1016 ; RV64I-NEXT: call __extendhfsf2@plt
1017 ; RV64I-NEXT: mv s1, a0
1018 ; RV64I-NEXT: and a0, s0, s3
1019 ; RV64I-NEXT: call __extendhfsf2@plt
1020 ; RV64I-NEXT: mv a2, a0
1021 ; RV64I-NEXT: mv a0, s2
1022 ; RV64I-NEXT: mv a1, s1
1023 ; RV64I-NEXT: call fmaf@plt
1024 ; RV64I-NEXT: call __truncsfhf2@plt
1025 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
1026 ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
1027 ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
1028 ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
1029 ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
1030 ; RV64I-NEXT: addi sp, sp, 48
1031 ; RV64I-NEXT: ret
1032 %1 = call half @llvm.fma.f16(half %a, half %b, half %c)
1033 ret half %1
1034 }
1036 declare half @llvm.fmuladd.f16(half, half, half)
1038 define half @fmuladd_f16(half %a, half %b, half %c) nounwind {
1039 ; CHECKIZFH-LABEL: fmuladd_f16:
1040 ; CHECKIZFH: # %bb.0:
1041 ; CHECKIZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
1042 ; CHECKIZFH-NEXT: ret
1043 ;
1044 ; RV32IDZFH-LABEL: fmuladd_f16:
1045 ; RV32IDZFH: # %bb.0:
1046 ; RV32IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
1047 ; RV32IDZFH-NEXT: ret
1048 ;
1049 ; RV64IDZFH-LABEL: fmuladd_f16:
1050 ; RV64IDZFH: # %bb.0:
1051 ; RV64IDZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
1052 ; RV64IDZFH-NEXT: ret
1053 ;
1054 ; RV32I-LABEL: fmuladd_f16:
1055 ; RV32I: # %bb.0:
1056 ; RV32I-NEXT: addi sp, sp, -32
1057 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
1058 ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
1059 ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
1060 ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
1061 ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
1062 ; RV32I-NEXT: mv s0, a2
1063 ; RV32I-NEXT: mv s1, a1
1064 ; RV32I-NEXT: lui a1, 16
1065 ; RV32I-NEXT: addi s3, a1, -1
1066 ; RV32I-NEXT: and a0, a0, s3
1067 ; RV32I-NEXT: call __extendhfsf2@plt
1068 ; RV32I-NEXT: mv s2, a0
1069 ; RV32I-NEXT: and a0, s1, s3
1070 ; RV32I-NEXT: call __extendhfsf2@plt
1071 ; RV32I-NEXT: mv a1, a0
1072 ; RV32I-NEXT: mv a0, s2
1073 ; RV32I-NEXT: call __mulsf3@plt
1074 ; RV32I-NEXT: call __truncsfhf2@plt
1075 ; RV32I-NEXT: mv s1, a0
1076 ; RV32I-NEXT: and a0, s0, s3
1077 ; RV32I-NEXT: call __extendhfsf2@plt
1078 ; RV32I-NEXT: mv s0, a0
1079 ; RV32I-NEXT: and a0, s1, s3
1080 ; RV32I-NEXT: call __extendhfsf2@plt
1081 ; RV32I-NEXT: mv a1, s0
1082 ; RV32I-NEXT: call __addsf3@plt
1083 ; RV32I-NEXT: call __truncsfhf2@plt
1084 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
1085 ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
1086 ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
1087 ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
1088 ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
1089 ; RV32I-NEXT: addi sp, sp, 32
1090 ; RV32I-NEXT: ret
1091 ;
1092 ; RV64I-LABEL: fmuladd_f16:
1093 ; RV64I: # %bb.0:
1094 ; RV64I-NEXT: addi sp, sp, -48
1095 ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
1096 ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
1097 ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
1098 ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
1099 ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
1100 ; RV64I-NEXT: mv s0, a2
1101 ; RV64I-NEXT: mv s1, a1
1102 ; RV64I-NEXT: lui a1, 16
1103 ; RV64I-NEXT: addiw s3, a1, -1
1104 ; RV64I-NEXT: and a0, a0, s3
1105 ; RV64I-NEXT: call __extendhfsf2@plt
1106 ; RV64I-NEXT: mv s2, a0
1107 ; RV64I-NEXT: and a0, s1, s3
1108 ; RV64I-NEXT: call __extendhfsf2@plt
1109 ; RV64I-NEXT: mv a1, a0
1110 ; RV64I-NEXT: mv a0, s2
1111 ; RV64I-NEXT: call __mulsf3@plt
1112 ; RV64I-NEXT: call __truncsfhf2@plt
1113 ; RV64I-NEXT: mv s1, a0
1114 ; RV64I-NEXT: and a0, s0, s3
1115 ; RV64I-NEXT: call __extendhfsf2@plt
1116 ; RV64I-NEXT: mv s0, a0
1117 ; RV64I-NEXT: and a0, s1, s3
1118 ; RV64I-NEXT: call __extendhfsf2@plt
1119 ; RV64I-NEXT: mv a1, s0
1120 ; RV64I-NEXT: call __addsf3@plt
1121 ; RV64I-NEXT: call __truncsfhf2@plt
1122 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
1123 ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
1124 ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
1125 ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
1126 ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
1127 ; RV64I-NEXT: addi sp, sp, 48
1128 ; RV64I-NEXT: ret
1129 %1 = call half @llvm.fmuladd.f16(half %a, half %b, half %c)
1130 ret half %1
1131 }
1133 declare half @llvm.fabs.f16(half)
1135 define half @fabs_f16(half %a) nounwind {
1136 ; CHECKIZFH-LABEL: fabs_f16:
1137 ; CHECKIZFH: # %bb.0:
1138 ; CHECKIZFH-NEXT: fabs.h fa0, fa0
1139 ; CHECKIZFH-NEXT: ret
1140 ;
1141 ; RV32IDZFH-LABEL: fabs_f16:
1142 ; RV32IDZFH: # %bb.0:
1143 ; RV32IDZFH-NEXT: fabs.h fa0, fa0
1144 ; RV32IDZFH-NEXT: ret
1145 ;
1146 ; RV64IDZFH-LABEL: fabs_f16:
1147 ; RV64IDZFH: # %bb.0:
1148 ; RV64IDZFH-NEXT: fabs.h fa0, fa0
1149 ; RV64IDZFH-NEXT: ret
1150 ;
1151 ; RV32I-LABEL: fabs_f16:
1152 ; RV32I: # %bb.0:
1153 ; RV32I-NEXT: slli a0, a0, 17
1154 ; RV32I-NEXT: srli a0, a0, 17
1155 ; RV32I-NEXT: ret
1156 ;
1157 ; RV64I-LABEL: fabs_f16:
1158 ; RV64I: # %bb.0:
1159 ; RV64I-NEXT: slli a0, a0, 49
1160 ; RV64I-NEXT: srli a0, a0, 49
1161 ; RV64I-NEXT: ret
1162 %1 = call half @llvm.fabs.f16(half %a)
1163 ret half %1
1164 }
1166 declare half @llvm.minnum.f16(half, half)
1168 define half @minnum_f16(half %a, half %b) nounwind {
1169 ; CHECKIZFH-LABEL: minnum_f16:
1170 ; CHECKIZFH: # %bb.0:
1171 ; CHECKIZFH-NEXT: fmin.h fa0, fa0, fa1
1172 ; CHECKIZFH-NEXT: ret
1173 ;
1174 ; RV32IDZFH-LABEL: minnum_f16:
1175 ; RV32IDZFH: # %bb.0:
1176 ; RV32IDZFH-NEXT: fmin.h fa0, fa0, fa1
1177 ; RV32IDZFH-NEXT: ret
1178 ;
1179 ; RV64IDZFH-LABEL: minnum_f16:
1180 ; RV64IDZFH: # %bb.0:
1181 ; RV64IDZFH-NEXT: fmin.h fa0, fa0, fa1
1182 ; RV64IDZFH-NEXT: ret
1183 ;
1184 ; RV32I-LABEL: minnum_f16:
1185 ; RV32I: # %bb.0:
1186 ; RV32I-NEXT: addi sp, sp, -16
1187 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1188 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1189 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
1190 ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
1191 ; RV32I-NEXT: mv s0, a1
1192 ; RV32I-NEXT: lui a1, 16
1193 ; RV32I-NEXT: addi s2, a1, -1
1194 ; RV32I-NEXT: and a0, a0, s2
1195 ; RV32I-NEXT: call __extendhfsf2@plt
1196 ; RV32I-NEXT: mv s1, a0
1197 ; RV32I-NEXT: and a0, s0, s2
1198 ; RV32I-NEXT: call __extendhfsf2@plt
1199 ; RV32I-NEXT: mv a1, a0
1200 ; RV32I-NEXT: mv a0, s1
1201 ; RV32I-NEXT: call fminf@plt
1202 ; RV32I-NEXT: call __truncsfhf2@plt
1203 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1204 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1205 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
1206 ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
1207 ; RV32I-NEXT: addi sp, sp, 16
1208 ; RV32I-NEXT: ret
1209 ;
1210 ; RV64I-LABEL: minnum_f16:
1211 ; RV64I: # %bb.0:
1212 ; RV64I-NEXT: addi sp, sp, -32
1213 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
1214 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
1215 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
1216 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
1217 ; RV64I-NEXT: mv s0, a1
1218 ; RV64I-NEXT: lui a1, 16
1219 ; RV64I-NEXT: addiw s2, a1, -1
1220 ; RV64I-NEXT: and a0, a0, s2
1221 ; RV64I-NEXT: call __extendhfsf2@plt
1222 ; RV64I-NEXT: mv s1, a0
1223 ; RV64I-NEXT: and a0, s0, s2
1224 ; RV64I-NEXT: call __extendhfsf2@plt
1225 ; RV64I-NEXT: mv a1, a0
1226 ; RV64I-NEXT: mv a0, s1
1227 ; RV64I-NEXT: call fminf@plt
1228 ; RV64I-NEXT: call __truncsfhf2@plt
1229 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
1230 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
1231 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
1232 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
1233 ; RV64I-NEXT: addi sp, sp, 32
1234 ; RV64I-NEXT: ret
1235 %1 = call half @llvm.minnum.f16(half %a, half %b)
1236 ret half %1
1237 }
1239 declare half @llvm.maxnum.f16(half, half)
1241 define half @maxnum_f16(half %a, half %b) nounwind {
1242 ; CHECKIZFH-LABEL: maxnum_f16:
1243 ; CHECKIZFH: # %bb.0:
1244 ; CHECKIZFH-NEXT: fmax.h fa0, fa0, fa1
1245 ; CHECKIZFH-NEXT: ret
1246 ;
1247 ; RV32IDZFH-LABEL: maxnum_f16:
1248 ; RV32IDZFH: # %bb.0:
1249 ; RV32IDZFH-NEXT: fmax.h fa0, fa0, fa1
1250 ; RV32IDZFH-NEXT: ret
1251 ;
1252 ; RV64IDZFH-LABEL: maxnum_f16:
1253 ; RV64IDZFH: # %bb.0:
1254 ; RV64IDZFH-NEXT: fmax.h fa0, fa0, fa1
1255 ; RV64IDZFH-NEXT: ret
1256 ;
1257 ; RV32I-LABEL: maxnum_f16:
1258 ; RV32I: # %bb.0:
1259 ; RV32I-NEXT: addi sp, sp, -16
1260 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1261 ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1262 ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
1263 ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
1264 ; RV32I-NEXT: mv s0, a1
1265 ; RV32I-NEXT: lui a1, 16
1266 ; RV32I-NEXT: addi s2, a1, -1
1267 ; RV32I-NEXT: and a0, a0, s2
1268 ; RV32I-NEXT: call __extendhfsf2@plt
1269 ; RV32I-NEXT: mv s1, a0
1270 ; RV32I-NEXT: and a0, s0, s2
1271 ; RV32I-NEXT: call __extendhfsf2@plt
1272 ; RV32I-NEXT: mv a1, a0
1273 ; RV32I-NEXT: mv a0, s1
1274 ; RV32I-NEXT: call fmaxf@plt
1275 ; RV32I-NEXT: call __truncsfhf2@plt
1276 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1277 ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1278 ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
1279 ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
1280 ; RV32I-NEXT: addi sp, sp, 16
1281 ; RV32I-NEXT: ret
1282 ;
1283 ; RV64I-LABEL: maxnum_f16:
1284 ; RV64I: # %bb.0:
1285 ; RV64I-NEXT: addi sp, sp, -32
1286 ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
1287 ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
1288 ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
1289 ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
1290 ; RV64I-NEXT: mv s0, a1
1291 ; RV64I-NEXT: lui a1, 16
1292 ; RV64I-NEXT: addiw s2, a1, -1
1293 ; RV64I-NEXT: and a0, a0, s2
1294 ; RV64I-NEXT: call __extendhfsf2@plt
1295 ; RV64I-NEXT: mv s1, a0
1296 ; RV64I-NEXT: and a0, s0, s2
1297 ; RV64I-NEXT: call __extendhfsf2@plt
1298 ; RV64I-NEXT: mv a1, a0
1299 ; RV64I-NEXT: mv a0, s1
1300 ; RV64I-NEXT: call fmaxf@plt
1301 ; RV64I-NEXT: call __truncsfhf2@plt
1302 ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
1303 ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
1304 ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
1305 ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
1306 ; RV64I-NEXT: addi sp, sp, 32
1307 ; RV64I-NEXT: ret
1308 %1 = call half @llvm.maxnum.f16(half %a, half %b)
1309 ret half %1
1310 }
1312 ; TODO: FMINNAN and FMAXNAN aren't handled in
1313 ; SelectionDAGLegalize::ExpandNode.
1315 ; declare half @llvm.minimum.f16(half, half)
1317 ; define half @fminimum_f16(half %a, half %b) nounwind {
1318 ; %1 = call half @llvm.minimum.f16(half %a, half %b)
1319 ; ret half %1
1320 ; }
1322 ; declare half @llvm.maximum.f16(half, half)
1324 ; define half @fmaximum_f16(half %a, half %b) nounwind {
1325 ; %1 = call half @llvm.maximum.f16(half %a, half %b)
1326 ; ret half %1
1327 ; }
1329 declare half @llvm.copysign.f16(half, half)
1331 define half @copysign_f16(half %a, half %b) nounwind {
1332 ; CHECKIZFH-LABEL: copysign_f16:
1333 ; CHECKIZFH: # %bb.0:
1334 ; CHECKIZFH-NEXT: fsgnj.h fa0, fa0, fa1
1335 ; CHECKIZFH-NEXT: ret
1336 ;
1337 ; RV32IDZFH-LABEL: copysign_f16:
1338 ; RV32IDZFH: # %bb.0:
1339 ; RV32IDZFH-NEXT: fsgnj.h fa0, fa0, fa1
1340 ; RV32IDZFH-NEXT: ret
1341 ;
1342 ; RV64IDZFH-LABEL: copysign_f16:
1343 ; RV64IDZFH: # %bb.0:
1344 ; RV64IDZFH-NEXT: fsgnj.h fa0, fa0, fa1
1345 ; RV64IDZFH-NEXT: ret
1346 ;
1347 ; RV32I-LABEL: copysign_f16:
1348 ; RV32I: # %bb.0:
1349 ; RV32I-NEXT: lui a2, 1048568
1350 ; RV32I-NEXT: and a1, a1, a2
1351 ; RV32I-NEXT: slli a0, a0, 17
1352 ; RV32I-NEXT: srli a0, a0, 17
1353 ; RV32I-NEXT: or a0, a0, a1
1354 ; RV32I-NEXT: ret
1355 ;
1356 ; RV64I-LABEL: copysign_f16:
1357 ; RV64I: # %bb.0:
1358 ; RV64I-NEXT: lui a2, 1048568
1359 ; RV64I-NEXT: and a1, a1, a2
1360 ; RV64I-NEXT: slli a0, a0, 49
1361 ; RV64I-NEXT: srli a0, a0, 49
1362 ; RV64I-NEXT: or a0, a0, a1
1363 ; RV64I-NEXT: ret
1364 %1 = call half @llvm.copysign.f16(half %a, half %b)
1365 ret half %1
1366 }
1368 declare half @llvm.floor.f16(half)
1370 define half @floor_f16(half %a) nounwind {
1371 ; RV32IZFH-LABEL: floor_f16:
1372 ; RV32IZFH: # %bb.0:
1373 ; RV32IZFH-NEXT: addi sp, sp, -16
1374 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1375 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
1376 ; RV32IZFH-NEXT: call floorf@plt
1377 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
1378 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1379 ; RV32IZFH-NEXT: addi sp, sp, 16
1380 ; RV32IZFH-NEXT: ret
1381 ;
1382 ; RV64IZFH-LABEL: floor_f16:
1383 ; RV64IZFH: # %bb.0:
1384 ; RV64IZFH-NEXT: addi sp, sp, -16
1385 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1386 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
1387 ; RV64IZFH-NEXT: call floorf@plt
1388 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
1389 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1390 ; RV64IZFH-NEXT: addi sp, sp, 16
1391 ; RV64IZFH-NEXT: ret
1392 ;
1393 ; RV32IDZFH-LABEL: floor_f16:
1394 ; RV32IDZFH: # %bb.0:
1395 ; RV32IDZFH-NEXT: addi sp, sp, -16
1396 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1397 ; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
1398 ; RV32IDZFH-NEXT: call floorf@plt
1399 ; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
1400 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1401 ; RV32IDZFH-NEXT: addi sp, sp, 16
1402 ; RV32IDZFH-NEXT: ret
1403 ;
1404 ; RV64IDZFH-LABEL: floor_f16:
1405 ; RV64IDZFH: # %bb.0:
1406 ; RV64IDZFH-NEXT: addi sp, sp, -16
1407 ; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1408 ; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
1409 ; RV64IDZFH-NEXT: call floorf@plt
1410 ; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
1411 ; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1412 ; RV64IDZFH-NEXT: addi sp, sp, 16
1413 ; RV64IDZFH-NEXT: ret
1414 ;
1415 ; RV32I-LABEL: floor_f16:
1416 ; RV32I: # %bb.0:
1417 ; RV32I-NEXT: addi sp, sp, -16
1418 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1419 ; RV32I-NEXT: slli a0, a0, 16
1420 ; RV32I-NEXT: srli a0, a0, 16
1421 ; RV32I-NEXT: call __extendhfsf2@plt
1422 ; RV32I-NEXT: call floorf@plt
1423 ; RV32I-NEXT: call __truncsfhf2@plt
1424 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1425 ; RV32I-NEXT: addi sp, sp, 16
1426 ; RV32I-NEXT: ret
1427 ;
1428 ; RV64I-LABEL: floor_f16:
1429 ; RV64I: # %bb.0:
1430 ; RV64I-NEXT: addi sp, sp, -16
1431 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1432 ; RV64I-NEXT: slli a0, a0, 48
1433 ; RV64I-NEXT: srli a0, a0, 48
1434 ; RV64I-NEXT: call __extendhfsf2@plt
1435 ; RV64I-NEXT: call floorf@plt
1436 ; RV64I-NEXT: call __truncsfhf2@plt
1437 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1438 ; RV64I-NEXT: addi sp, sp, 16
1439 ; RV64I-NEXT: ret
1440 %1 = call half @llvm.floor.f16(half %a)
1441 ret half %1
1442 }
1444 declare half @llvm.ceil.f16(half)
1446 define half @ceil_f16(half %a) nounwind {
1447 ; RV32IZFH-LABEL: ceil_f16:
1448 ; RV32IZFH: # %bb.0:
1449 ; RV32IZFH-NEXT: addi sp, sp, -16
1450 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1451 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
1452 ; RV32IZFH-NEXT: call ceilf@plt
1453 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
1454 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1455 ; RV32IZFH-NEXT: addi sp, sp, 16
1456 ; RV32IZFH-NEXT: ret
1457 ;
1458 ; RV64IZFH-LABEL: ceil_f16:
1459 ; RV64IZFH: # %bb.0:
1460 ; RV64IZFH-NEXT: addi sp, sp, -16
1461 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1462 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
1463 ; RV64IZFH-NEXT: call ceilf@plt
1464 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
1465 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1466 ; RV64IZFH-NEXT: addi sp, sp, 16
1467 ; RV64IZFH-NEXT: ret
1468 ;
1469 ; RV32IDZFH-LABEL: ceil_f16:
1470 ; RV32IDZFH: # %bb.0:
1471 ; RV32IDZFH-NEXT: addi sp, sp, -16
1472 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1473 ; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
1474 ; RV32IDZFH-NEXT: call ceilf@plt
1475 ; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
1476 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1477 ; RV32IDZFH-NEXT: addi sp, sp, 16
1478 ; RV32IDZFH-NEXT: ret
1479 ;
1480 ; RV64IDZFH-LABEL: ceil_f16:
1481 ; RV64IDZFH: # %bb.0:
1482 ; RV64IDZFH-NEXT: addi sp, sp, -16
1483 ; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1484 ; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
1485 ; RV64IDZFH-NEXT: call ceilf@plt
1486 ; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
1487 ; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1488 ; RV64IDZFH-NEXT: addi sp, sp, 16
1489 ; RV64IDZFH-NEXT: ret
1490 ;
1491 ; RV32I-LABEL: ceil_f16:
1492 ; RV32I: # %bb.0:
1493 ; RV32I-NEXT: addi sp, sp, -16
1494 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1495 ; RV32I-NEXT: slli a0, a0, 16
1496 ; RV32I-NEXT: srli a0, a0, 16
1497 ; RV32I-NEXT: call __extendhfsf2@plt
1498 ; RV32I-NEXT: call ceilf@plt
1499 ; RV32I-NEXT: call __truncsfhf2@plt
1500 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1501 ; RV32I-NEXT: addi sp, sp, 16
1502 ; RV32I-NEXT: ret
1503 ;
1504 ; RV64I-LABEL: ceil_f16:
1505 ; RV64I: # %bb.0:
1506 ; RV64I-NEXT: addi sp, sp, -16
1507 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1508 ; RV64I-NEXT: slli a0, a0, 48
1509 ; RV64I-NEXT: srli a0, a0, 48
1510 ; RV64I-NEXT: call __extendhfsf2@plt
1511 ; RV64I-NEXT: call ceilf@plt
1512 ; RV64I-NEXT: call __truncsfhf2@plt
1513 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1514 ; RV64I-NEXT: addi sp, sp, 16
1515 ; RV64I-NEXT: ret
1516 %1 = call half @llvm.ceil.f16(half %a)
1517 ret half %1
1518 }
1520 declare half @llvm.trunc.f16(half)
1522 define half @trunc_f16(half %a) nounwind {
1523 ; RV32IZFH-LABEL: trunc_f16:
1524 ; RV32IZFH: # %bb.0:
1525 ; RV32IZFH-NEXT: addi sp, sp, -16
1526 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1527 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
1528 ; RV32IZFH-NEXT: call truncf@plt
1529 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
1530 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1531 ; RV32IZFH-NEXT: addi sp, sp, 16
1532 ; RV32IZFH-NEXT: ret
1533 ;
1534 ; RV64IZFH-LABEL: trunc_f16:
1535 ; RV64IZFH: # %bb.0:
1536 ; RV64IZFH-NEXT: addi sp, sp, -16
1537 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1538 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
1539 ; RV64IZFH-NEXT: call truncf@plt
1540 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
1541 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1542 ; RV64IZFH-NEXT: addi sp, sp, 16
1543 ; RV64IZFH-NEXT: ret
1544 ;
1545 ; RV32IDZFH-LABEL: trunc_f16:
1546 ; RV32IDZFH: # %bb.0:
1547 ; RV32IDZFH-NEXT: addi sp, sp, -16
1548 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1549 ; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
1550 ; RV32IDZFH-NEXT: call truncf@plt
1551 ; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
1552 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1553 ; RV32IDZFH-NEXT: addi sp, sp, 16
1554 ; RV32IDZFH-NEXT: ret
1555 ;
1556 ; RV64IDZFH-LABEL: trunc_f16:
1557 ; RV64IDZFH: # %bb.0:
1558 ; RV64IDZFH-NEXT: addi sp, sp, -16
1559 ; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1560 ; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
1561 ; RV64IDZFH-NEXT: call truncf@plt
1562 ; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
1563 ; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1564 ; RV64IDZFH-NEXT: addi sp, sp, 16
1565 ; RV64IDZFH-NEXT: ret
1566 ;
1567 ; RV32I-LABEL: trunc_f16:
1568 ; RV32I: # %bb.0:
1569 ; RV32I-NEXT: addi sp, sp, -16
1570 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1571 ; RV32I-NEXT: slli a0, a0, 16
1572 ; RV32I-NEXT: srli a0, a0, 16
1573 ; RV32I-NEXT: call __extendhfsf2@plt
1574 ; RV32I-NEXT: call truncf@plt
1575 ; RV32I-NEXT: call __truncsfhf2@plt
1576 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1577 ; RV32I-NEXT: addi sp, sp, 16
1578 ; RV32I-NEXT: ret
1579 ;
1580 ; RV64I-LABEL: trunc_f16:
1581 ; RV64I: # %bb.0:
1582 ; RV64I-NEXT: addi sp, sp, -16
1583 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1584 ; RV64I-NEXT: slli a0, a0, 48
1585 ; RV64I-NEXT: srli a0, a0, 48
1586 ; RV64I-NEXT: call __extendhfsf2@plt
1587 ; RV64I-NEXT: call truncf@plt
1588 ; RV64I-NEXT: call __truncsfhf2@plt
1589 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1590 ; RV64I-NEXT: addi sp, sp, 16
1591 ; RV64I-NEXT: ret
1592 %1 = call half @llvm.trunc.f16(half %a)
1593 ret half %1
1594 }
1596 declare half @llvm.rint.f16(half)
1598 define half @rint_f16(half %a) nounwind {
1599 ; RV32IZFH-LABEL: rint_f16:
1600 ; RV32IZFH: # %bb.0:
1601 ; RV32IZFH-NEXT: addi sp, sp, -16
1602 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1603 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
1604 ; RV32IZFH-NEXT: call rintf@plt
1605 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
1606 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1607 ; RV32IZFH-NEXT: addi sp, sp, 16
1608 ; RV32IZFH-NEXT: ret
1609 ;
1610 ; RV64IZFH-LABEL: rint_f16:
1611 ; RV64IZFH: # %bb.0:
1612 ; RV64IZFH-NEXT: addi sp, sp, -16
1613 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1614 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
1615 ; RV64IZFH-NEXT: call rintf@plt
1616 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
1617 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1618 ; RV64IZFH-NEXT: addi sp, sp, 16
1619 ; RV64IZFH-NEXT: ret
1620 ;
1621 ; RV32IDZFH-LABEL: rint_f16:
1622 ; RV32IDZFH: # %bb.0:
1623 ; RV32IDZFH-NEXT: addi sp, sp, -16
1624 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1625 ; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
1626 ; RV32IDZFH-NEXT: call rintf@plt
1627 ; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
1628 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1629 ; RV32IDZFH-NEXT: addi sp, sp, 16
1630 ; RV32IDZFH-NEXT: ret
1631 ;
1632 ; RV64IDZFH-LABEL: rint_f16:
1633 ; RV64IDZFH: # %bb.0:
1634 ; RV64IDZFH-NEXT: addi sp, sp, -16
1635 ; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1636 ; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
1637 ; RV64IDZFH-NEXT: call rintf@plt
1638 ; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
1639 ; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1640 ; RV64IDZFH-NEXT: addi sp, sp, 16
1641 ; RV64IDZFH-NEXT: ret
1642 ;
1643 ; RV32I-LABEL: rint_f16:
1644 ; RV32I: # %bb.0:
1645 ; RV32I-NEXT: addi sp, sp, -16
1646 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1647 ; RV32I-NEXT: slli a0, a0, 16
1648 ; RV32I-NEXT: srli a0, a0, 16
1649 ; RV32I-NEXT: call __extendhfsf2@plt
1650 ; RV32I-NEXT: call rintf@plt
1651 ; RV32I-NEXT: call __truncsfhf2@plt
1652 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1653 ; RV32I-NEXT: addi sp, sp, 16
1654 ; RV32I-NEXT: ret
1655 ;
1656 ; RV64I-LABEL: rint_f16:
1657 ; RV64I: # %bb.0:
1658 ; RV64I-NEXT: addi sp, sp, -16
1659 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1660 ; RV64I-NEXT: slli a0, a0, 48
1661 ; RV64I-NEXT: srli a0, a0, 48
1662 ; RV64I-NEXT: call __extendhfsf2@plt
1663 ; RV64I-NEXT: call rintf@plt
1664 ; RV64I-NEXT: call __truncsfhf2@plt
1665 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1666 ; RV64I-NEXT: addi sp, sp, 16
1667 ; RV64I-NEXT: ret
1668 %1 = call half @llvm.rint.f16(half %a)
1669 ret half %1
1670 }
1672 declare half @llvm.nearbyint.f16(half)
1674 define half @nearbyint_f16(half %a) nounwind {
1675 ; RV32IZFH-LABEL: nearbyint_f16:
1676 ; RV32IZFH: # %bb.0:
1677 ; RV32IZFH-NEXT: addi sp, sp, -16
1678 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1679 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
1680 ; RV32IZFH-NEXT: call nearbyintf@plt
1681 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
1682 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1683 ; RV32IZFH-NEXT: addi sp, sp, 16
1684 ; RV32IZFH-NEXT: ret
1685 ;
1686 ; RV64IZFH-LABEL: nearbyint_f16:
1687 ; RV64IZFH: # %bb.0:
1688 ; RV64IZFH-NEXT: addi sp, sp, -16
1689 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1690 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
1691 ; RV64IZFH-NEXT: call nearbyintf@plt
1692 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
1693 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1694 ; RV64IZFH-NEXT: addi sp, sp, 16
1695 ; RV64IZFH-NEXT: ret
1696 ;
1697 ; RV32IDZFH-LABEL: nearbyint_f16:
1698 ; RV32IDZFH: # %bb.0:
1699 ; RV32IDZFH-NEXT: addi sp, sp, -16
1700 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1701 ; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
1702 ; RV32IDZFH-NEXT: call nearbyintf@plt
1703 ; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
1704 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1705 ; RV32IDZFH-NEXT: addi sp, sp, 16
1706 ; RV32IDZFH-NEXT: ret
1707 ;
1708 ; RV64IDZFH-LABEL: nearbyint_f16:
1709 ; RV64IDZFH: # %bb.0:
1710 ; RV64IDZFH-NEXT: addi sp, sp, -16
1711 ; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1712 ; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
1713 ; RV64IDZFH-NEXT: call nearbyintf@plt
1714 ; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
1715 ; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1716 ; RV64IDZFH-NEXT: addi sp, sp, 16
1717 ; RV64IDZFH-NEXT: ret
1718 ;
1719 ; RV32I-LABEL: nearbyint_f16:
1720 ; RV32I: # %bb.0:
1721 ; RV32I-NEXT: addi sp, sp, -16
1722 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1723 ; RV32I-NEXT: slli a0, a0, 16
1724 ; RV32I-NEXT: srli a0, a0, 16
1725 ; RV32I-NEXT: call __extendhfsf2@plt
1726 ; RV32I-NEXT: call nearbyintf@plt
1727 ; RV32I-NEXT: call __truncsfhf2@plt
1728 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1729 ; RV32I-NEXT: addi sp, sp, 16
1730 ; RV32I-NEXT: ret
1731 ;
1732 ; RV64I-LABEL: nearbyint_f16:
1733 ; RV64I: # %bb.0:
1734 ; RV64I-NEXT: addi sp, sp, -16
1735 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1736 ; RV64I-NEXT: slli a0, a0, 48
1737 ; RV64I-NEXT: srli a0, a0, 48
1738 ; RV64I-NEXT: call __extendhfsf2@plt
1739 ; RV64I-NEXT: call nearbyintf@plt
1740 ; RV64I-NEXT: call __truncsfhf2@plt
1741 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1742 ; RV64I-NEXT: addi sp, sp, 16
1743 ; RV64I-NEXT: ret
1744 %1 = call half @llvm.nearbyint.f16(half %a)
1745 ret half %1
1746 }
1748 declare half @llvm.round.f16(half)
1750 define half @round_f16(half %a) nounwind {
1751 ; RV32IZFH-LABEL: round_f16:
1752 ; RV32IZFH: # %bb.0:
1753 ; RV32IZFH-NEXT: addi sp, sp, -16
1754 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1755 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
1756 ; RV32IZFH-NEXT: call roundf@plt
1757 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
1758 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1759 ; RV32IZFH-NEXT: addi sp, sp, 16
1760 ; RV32IZFH-NEXT: ret
1761 ;
1762 ; RV64IZFH-LABEL: round_f16:
1763 ; RV64IZFH: # %bb.0:
1764 ; RV64IZFH-NEXT: addi sp, sp, -16
1765 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1766 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
1767 ; RV64IZFH-NEXT: call roundf@plt
1768 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
1769 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1770 ; RV64IZFH-NEXT: addi sp, sp, 16
1771 ; RV64IZFH-NEXT: ret
1772 ;
1773 ; RV32IDZFH-LABEL: round_f16:
1774 ; RV32IDZFH: # %bb.0:
1775 ; RV32IDZFH-NEXT: addi sp, sp, -16
1776 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1777 ; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
1778 ; RV32IDZFH-NEXT: call roundf@plt
1779 ; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
1780 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1781 ; RV32IDZFH-NEXT: addi sp, sp, 16
1782 ; RV32IDZFH-NEXT: ret
1783 ;
1784 ; RV64IDZFH-LABEL: round_f16:
1785 ; RV64IDZFH: # %bb.0:
1786 ; RV64IDZFH-NEXT: addi sp, sp, -16
1787 ; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1788 ; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
1789 ; RV64IDZFH-NEXT: call roundf@plt
1790 ; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
1791 ; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1792 ; RV64IDZFH-NEXT: addi sp, sp, 16
1793 ; RV64IDZFH-NEXT: ret
1794 ;
1795 ; RV32I-LABEL: round_f16:
1796 ; RV32I: # %bb.0:
1797 ; RV32I-NEXT: addi sp, sp, -16
1798 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1799 ; RV32I-NEXT: slli a0, a0, 16
1800 ; RV32I-NEXT: srli a0, a0, 16
1801 ; RV32I-NEXT: call __extendhfsf2@plt
1802 ; RV32I-NEXT: call roundf@plt
1803 ; RV32I-NEXT: call __truncsfhf2@plt
1804 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1805 ; RV32I-NEXT: addi sp, sp, 16
1806 ; RV32I-NEXT: ret
1807 ;
1808 ; RV64I-LABEL: round_f16:
1809 ; RV64I: # %bb.0:
1810 ; RV64I-NEXT: addi sp, sp, -16
1811 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1812 ; RV64I-NEXT: slli a0, a0, 48
1813 ; RV64I-NEXT: srli a0, a0, 48
1814 ; RV64I-NEXT: call __extendhfsf2@plt
1815 ; RV64I-NEXT: call roundf@plt
1816 ; RV64I-NEXT: call __truncsfhf2@plt
1817 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1818 ; RV64I-NEXT: addi sp, sp, 16
1819 ; RV64I-NEXT: ret
1820 %1 = call half @llvm.round.f16(half %a)
1821 ret half %1
1822 }
1824 declare half @llvm.roundeven.f16(half)
1826 define half @roundeven_f16(half %a) nounwind {
1827 ; RV32IZFH-LABEL: roundeven_f16:
1828 ; RV32IZFH: # %bb.0:
1829 ; RV32IZFH-NEXT: addi sp, sp, -16
1830 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1831 ; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
1832 ; RV32IZFH-NEXT: call roundevenf@plt
1833 ; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
1834 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1835 ; RV32IZFH-NEXT: addi sp, sp, 16
1836 ; RV32IZFH-NEXT: ret
1837 ;
1838 ; RV64IZFH-LABEL: roundeven_f16:
1839 ; RV64IZFH: # %bb.0:
1840 ; RV64IZFH-NEXT: addi sp, sp, -16
1841 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1842 ; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
1843 ; RV64IZFH-NEXT: call roundevenf@plt
1844 ; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
1845 ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1846 ; RV64IZFH-NEXT: addi sp, sp, 16
1847 ; RV64IZFH-NEXT: ret
1848 ;
1849 ; RV32IDZFH-LABEL: roundeven_f16:
1850 ; RV32IDZFH: # %bb.0:
1851 ; RV32IDZFH-NEXT: addi sp, sp, -16
1852 ; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1853 ; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0
1854 ; RV32IDZFH-NEXT: call roundevenf@plt
1855 ; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0
1856 ; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1857 ; RV32IDZFH-NEXT: addi sp, sp, 16
1858 ; RV32IDZFH-NEXT: ret
1859 ;
1860 ; RV64IDZFH-LABEL: roundeven_f16:
1861 ; RV64IDZFH: # %bb.0:
1862 ; RV64IDZFH-NEXT: addi sp, sp, -16
1863 ; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1864 ; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0
1865 ; RV64IDZFH-NEXT: call roundevenf@plt
1866 ; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0
1867 ; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1868 ; RV64IDZFH-NEXT: addi sp, sp, 16
1869 ; RV64IDZFH-NEXT: ret
1870 ;
1871 ; RV32I-LABEL: roundeven_f16:
1872 ; RV32I: # %bb.0:
1873 ; RV32I-NEXT: addi sp, sp, -16
1874 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1875 ; RV32I-NEXT: slli a0, a0, 16
1876 ; RV32I-NEXT: srli a0, a0, 16
1877 ; RV32I-NEXT: call __extendhfsf2@plt
1878 ; RV32I-NEXT: call roundevenf@plt
1879 ; RV32I-NEXT: call __truncsfhf2@plt
1880 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1881 ; RV32I-NEXT: addi sp, sp, 16
1882 ; RV32I-NEXT: ret
1883 ;
1884 ; RV64I-LABEL: roundeven_f16:
1885 ; RV64I: # %bb.0:
1886 ; RV64I-NEXT: addi sp, sp, -16
1887 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1888 ; RV64I-NEXT: slli a0, a0, 48
1889 ; RV64I-NEXT: srli a0, a0, 48
1890 ; RV64I-NEXT: call __extendhfsf2@plt
1891 ; RV64I-NEXT: call roundevenf@plt
1892 ; RV64I-NEXT: call __truncsfhf2@plt
1893 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1894 ; RV64I-NEXT: addi sp, sp, 16
1895 ; RV64I-NEXT: ret
1896 %1 = call half @llvm.roundeven.f16(half %a)
1897 ret half %1
1898 }