| blob | 6a342f15762276625bfc53e887f33f95c2a37972 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=riscv32 | FileCheck %s --check-prefixes=NOZBB,RV32I
3 ; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefixes=NOZBB,RV64I
4 ; RUN: llc < %s -mtriple=riscv32 -mattr=+zbb | \
5 ; RUN: FileCheck %s --check-prefixes=ZBB,RV32ZBB
6 ; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb | \
7 ; RUN: FileCheck %s --check-prefixes=ZBB,RV64ZBB
9 ; Basic tests.
11 declare i8 @llvm.smax.i8(i8 %a, i8 %b) readnone
13 define signext i8 @smax_i8(i8 signext %a, i8 signext %b) {
14 ; NOZBB-LABEL: smax_i8:
15 ; NOZBB: # %bb.0:
16 ; NOZBB-NEXT: blt a1, a0, .LBB0_2
17 ; NOZBB-NEXT: # %bb.1:
18 ; NOZBB-NEXT: mv a0, a1
19 ; NOZBB-NEXT: .LBB0_2:
20 ; NOZBB-NEXT: ret
21 ;
22 ; ZBB-LABEL: smax_i8:
23 ; ZBB: # %bb.0:
24 ; ZBB-NEXT: max a0, a0, a1
25 ; ZBB-NEXT: ret
26 %c = call i8 @llvm.smax.i8(i8 %a, i8 %b)
27 ret i8 %c
28 }
30 declare i16 @llvm.smax.i16(i16 %a, i16 %b) readnone
32 define signext i16 @smax_i16(i16 signext %a, i16 signext %b) {
33 ; NOZBB-LABEL: smax_i16:
34 ; NOZBB: # %bb.0:
35 ; NOZBB-NEXT: blt a1, a0, .LBB1_2
36 ; NOZBB-NEXT: # %bb.1:
37 ; NOZBB-NEXT: mv a0, a1
38 ; NOZBB-NEXT: .LBB1_2:
39 ; NOZBB-NEXT: ret
40 ;
41 ; ZBB-LABEL: smax_i16:
42 ; ZBB: # %bb.0:
43 ; ZBB-NEXT: max a0, a0, a1
44 ; ZBB-NEXT: ret
45 %c = call i16 @llvm.smax.i16(i16 %a, i16 %b)
46 ret i16 %c
47 }
49 declare i32 @llvm.smax.i32(i32 %a, i32 %b) readnone
51 define signext i32 @smax_i32(i32 signext %a, i32 signext %b) {
52 ; NOZBB-LABEL: smax_i32:
53 ; NOZBB: # %bb.0:
54 ; NOZBB-NEXT: blt a1, a0, .LBB2_2
55 ; NOZBB-NEXT: # %bb.1:
56 ; NOZBB-NEXT: mv a0, a1
57 ; NOZBB-NEXT: .LBB2_2:
58 ; NOZBB-NEXT: ret
59 ;
60 ; ZBB-LABEL: smax_i32:
61 ; ZBB: # %bb.0:
62 ; ZBB-NEXT: max a0, a0, a1
63 ; ZBB-NEXT: ret
64 %c = call i32 @llvm.smax.i32(i32 %a, i32 %b)
65 ret i32 %c
66 }
68 declare i64 @llvm.smax.i64(i64 %a, i64 %b) readnone
70 define i64 @smax_i64(i64 %a, i64 %b) {
71 ; RV32I-LABEL: smax_i64:
72 ; RV32I: # %bb.0:
73 ; RV32I-NEXT: mv a4, a0
74 ; RV32I-NEXT: bge a3, a1, .LBB3_5
75 ; RV32I-NEXT: # %bb.1:
76 ; RV32I-NEXT: bgeu a2, a0, .LBB3_6
77 ; RV32I-NEXT: .LBB3_2:
78 ; RV32I-NEXT: bne a1, a3, .LBB3_7
79 ; RV32I-NEXT: .LBB3_3:
80 ; RV32I-NEXT: bge a3, a1, .LBB3_8
81 ; RV32I-NEXT: .LBB3_4:
82 ; RV32I-NEXT: ret
83 ; RV32I-NEXT: .LBB3_5:
84 ; RV32I-NEXT: mv a4, a2
85 ; RV32I-NEXT: bltu a2, a0, .LBB3_2
86 ; RV32I-NEXT: .LBB3_6:
87 ; RV32I-NEXT: mv a0, a2
88 ; RV32I-NEXT: beq a1, a3, .LBB3_3
89 ; RV32I-NEXT: .LBB3_7:
90 ; RV32I-NEXT: mv a0, a4
91 ; RV32I-NEXT: blt a3, a1, .LBB3_4
92 ; RV32I-NEXT: .LBB3_8:
93 ; RV32I-NEXT: mv a1, a3
94 ; RV32I-NEXT: ret
95 ;
96 ; RV64I-LABEL: smax_i64:
97 ; RV64I: # %bb.0:
98 ; RV64I-NEXT: blt a1, a0, .LBB3_2
99 ; RV64I-NEXT: # %bb.1:
100 ; RV64I-NEXT: mv a0, a1
101 ; RV64I-NEXT: .LBB3_2:
102 ; RV64I-NEXT: ret
103 ;
104 ; RV32ZBB-LABEL: smax_i64:
105 ; RV32ZBB: # %bb.0:
106 ; RV32ZBB-NEXT: mv a4, a0
107 ; RV32ZBB-NEXT: bge a3, a1, .LBB3_3
108 ; RV32ZBB-NEXT: # %bb.1:
109 ; RV32ZBB-NEXT: beq a1, a3, .LBB3_4
110 ; RV32ZBB-NEXT: .LBB3_2:
111 ; RV32ZBB-NEXT: max a1, a1, a3
112 ; RV32ZBB-NEXT: ret
113 ; RV32ZBB-NEXT: .LBB3_3:
114 ; RV32ZBB-NEXT: mv a0, a2
115 ; RV32ZBB-NEXT: bne a1, a3, .LBB3_2
116 ; RV32ZBB-NEXT: .LBB3_4:
117 ; RV32ZBB-NEXT: maxu a0, a4, a2
118 ; RV32ZBB-NEXT: max a1, a1, a3
119 ; RV32ZBB-NEXT: ret
120 ;
121 ; RV64ZBB-LABEL: smax_i64:
122 ; RV64ZBB: # %bb.0:
123 ; RV64ZBB-NEXT: max a0, a0, a1
124 ; RV64ZBB-NEXT: ret
125 %c = call i64 @llvm.smax.i64(i64 %a, i64 %b)
126 ret i64 %c
127 }
129 declare i8 @llvm.smin.i8(i8 %a, i8 %b) readnone
131 define signext i8 @smin_i8(i8 signext %a, i8 signext %b) {
132 ; NOZBB-LABEL: smin_i8:
133 ; NOZBB: # %bb.0:
134 ; NOZBB-NEXT: blt a0, a1, .LBB4_2
135 ; NOZBB-NEXT: # %bb.1:
136 ; NOZBB-NEXT: mv a0, a1
137 ; NOZBB-NEXT: .LBB4_2:
138 ; NOZBB-NEXT: ret
139 ;
140 ; ZBB-LABEL: smin_i8:
141 ; ZBB: # %bb.0:
142 ; ZBB-NEXT: min a0, a0, a1
143 ; ZBB-NEXT: ret
144 %c = call i8 @llvm.smin.i8(i8 %a, i8 %b)
145 ret i8 %c
146 }
148 declare i16 @llvm.smin.i16(i16 %a, i16 %b) readnone
150 define signext i16 @smin_i16(i16 signext %a, i16 signext %b) {
151 ; NOZBB-LABEL: smin_i16:
152 ; NOZBB: # %bb.0:
153 ; NOZBB-NEXT: blt a0, a1, .LBB5_2
154 ; NOZBB-NEXT: # %bb.1:
155 ; NOZBB-NEXT: mv a0, a1
156 ; NOZBB-NEXT: .LBB5_2:
157 ; NOZBB-NEXT: ret
158 ;
159 ; ZBB-LABEL: smin_i16:
160 ; ZBB: # %bb.0:
161 ; ZBB-NEXT: min a0, a0, a1
162 ; ZBB-NEXT: ret
163 %c = call i16 @llvm.smin.i16(i16 %a, i16 %b)
164 ret i16 %c
165 }
167 declare i32 @llvm.smin.i32(i32 %a, i32 %b) readnone
169 define signext i32 @smin_i32(i32 signext %a, i32 signext %b) {
170 ; NOZBB-LABEL: smin_i32:
171 ; NOZBB: # %bb.0:
172 ; NOZBB-NEXT: blt a0, a1, .LBB6_2
173 ; NOZBB-NEXT: # %bb.1:
174 ; NOZBB-NEXT: mv a0, a1
175 ; NOZBB-NEXT: .LBB6_2:
176 ; NOZBB-NEXT: ret
177 ;
178 ; ZBB-LABEL: smin_i32:
179 ; ZBB: # %bb.0:
180 ; ZBB-NEXT: min a0, a0, a1
181 ; ZBB-NEXT: ret
182 %c = call i32 @llvm.smin.i32(i32 %a, i32 %b)
183 ret i32 %c
184 }
186 declare i64 @llvm.smin.i64(i64 %a, i64 %b) readnone
188 define i64 @smin_i64(i64 %a, i64 %b) {
189 ; RV32I-LABEL: smin_i64:
190 ; RV32I: # %bb.0:
191 ; RV32I-NEXT: mv a4, a0
192 ; RV32I-NEXT: bge a1, a3, .LBB7_5
193 ; RV32I-NEXT: # %bb.1:
194 ; RV32I-NEXT: bgeu a0, a2, .LBB7_6
195 ; RV32I-NEXT: .LBB7_2:
196 ; RV32I-NEXT: bne a1, a3, .LBB7_7
197 ; RV32I-NEXT: .LBB7_3:
198 ; RV32I-NEXT: bge a1, a3, .LBB7_8
199 ; RV32I-NEXT: .LBB7_4:
200 ; RV32I-NEXT: ret
201 ; RV32I-NEXT: .LBB7_5:
202 ; RV32I-NEXT: mv a4, a2
203 ; RV32I-NEXT: bltu a0, a2, .LBB7_2
204 ; RV32I-NEXT: .LBB7_6:
205 ; RV32I-NEXT: mv a0, a2
206 ; RV32I-NEXT: beq a1, a3, .LBB7_3
207 ; RV32I-NEXT: .LBB7_7:
208 ; RV32I-NEXT: mv a0, a4
209 ; RV32I-NEXT: blt a1, a3, .LBB7_4
210 ; RV32I-NEXT: .LBB7_8:
211 ; RV32I-NEXT: mv a1, a3
212 ; RV32I-NEXT: ret
213 ;
214 ; RV64I-LABEL: smin_i64:
215 ; RV64I: # %bb.0:
216 ; RV64I-NEXT: blt a0, a1, .LBB7_2
217 ; RV64I-NEXT: # %bb.1:
218 ; RV64I-NEXT: mv a0, a1
219 ; RV64I-NEXT: .LBB7_2:
220 ; RV64I-NEXT: ret
221 ;
222 ; RV32ZBB-LABEL: smin_i64:
223 ; RV32ZBB: # %bb.0:
224 ; RV32ZBB-NEXT: mv a4, a0
225 ; RV32ZBB-NEXT: bge a1, a3, .LBB7_3
226 ; RV32ZBB-NEXT: # %bb.1:
227 ; RV32ZBB-NEXT: beq a1, a3, .LBB7_4
228 ; RV32ZBB-NEXT: .LBB7_2:
229 ; RV32ZBB-NEXT: min a1, a1, a3
230 ; RV32ZBB-NEXT: ret
231 ; RV32ZBB-NEXT: .LBB7_3:
232 ; RV32ZBB-NEXT: mv a0, a2
233 ; RV32ZBB-NEXT: bne a1, a3, .LBB7_2
234 ; RV32ZBB-NEXT: .LBB7_4:
235 ; RV32ZBB-NEXT: minu a0, a4, a2
236 ; RV32ZBB-NEXT: min a1, a1, a3
237 ; RV32ZBB-NEXT: ret
238 ;
239 ; RV64ZBB-LABEL: smin_i64:
240 ; RV64ZBB: # %bb.0:
241 ; RV64ZBB-NEXT: min a0, a0, a1
242 ; RV64ZBB-NEXT: ret
243 %c = call i64 @llvm.smin.i64(i64 %a, i64 %b)
244 ret i64 %c
245 }
247 declare i8 @llvm.umax.i8(i8 %a, i8 %b) readnone
249 define i8 @umax_i8(i8 zeroext %a, i8 zeroext %b) {
250 ; NOZBB-LABEL: umax_i8:
251 ; NOZBB: # %bb.0:
252 ; NOZBB-NEXT: bltu a1, a0, .LBB8_2
253 ; NOZBB-NEXT: # %bb.1:
254 ; NOZBB-NEXT: mv a0, a1
255 ; NOZBB-NEXT: .LBB8_2:
256 ; NOZBB-NEXT: ret
257 ;
258 ; ZBB-LABEL: umax_i8:
259 ; ZBB: # %bb.0:
260 ; ZBB-NEXT: maxu a0, a0, a1
261 ; ZBB-NEXT: ret
262 %c = call i8 @llvm.umax.i8(i8 %a, i8 %b)
263 ret i8 %c
264 }
266 declare i16 @llvm.umax.i16(i16 %a, i16 %b) readnone
268 define i16 @umax_i16(i16 zeroext %a, i16 zeroext %b) {
269 ; NOZBB-LABEL: umax_i16:
270 ; NOZBB: # %bb.0:
271 ; NOZBB-NEXT: bltu a1, a0, .LBB9_2
272 ; NOZBB-NEXT: # %bb.1:
273 ; NOZBB-NEXT: mv a0, a1
274 ; NOZBB-NEXT: .LBB9_2:
275 ; NOZBB-NEXT: ret
276 ;
277 ; ZBB-LABEL: umax_i16:
278 ; ZBB: # %bb.0:
279 ; ZBB-NEXT: maxu a0, a0, a1
280 ; ZBB-NEXT: ret
281 %c = call i16 @llvm.umax.i16(i16 %a, i16 %b)
282 ret i16 %c
283 }
285 declare i32 @llvm.umax.i32(i32 %a, i32 %b) readnone
287 define signext i32 @umax_i32(i32 signext %a, i32 signext %b) {
288 ; NOZBB-LABEL: umax_i32:
289 ; NOZBB: # %bb.0:
290 ; NOZBB-NEXT: bltu a1, a0, .LBB10_2
291 ; NOZBB-NEXT: # %bb.1:
292 ; NOZBB-NEXT: mv a0, a1
293 ; NOZBB-NEXT: .LBB10_2:
294 ; NOZBB-NEXT: ret
295 ;
296 ; ZBB-LABEL: umax_i32:
297 ; ZBB: # %bb.0:
298 ; ZBB-NEXT: maxu a0, a0, a1
299 ; ZBB-NEXT: ret
300 %c = call i32 @llvm.umax.i32(i32 %a, i32 %b)
301 ret i32 %c
302 }
304 declare i64 @llvm.umax.i64(i64 %a, i64 %b) readnone
306 define i64 @umax_i64(i64 %a, i64 %b) {
307 ; RV32I-LABEL: umax_i64:
308 ; RV32I: # %bb.0:
309 ; RV32I-NEXT: mv a4, a0
310 ; RV32I-NEXT: bgeu a3, a1, .LBB11_5
311 ; RV32I-NEXT: # %bb.1:
312 ; RV32I-NEXT: bgeu a2, a0, .LBB11_6
313 ; RV32I-NEXT: .LBB11_2:
314 ; RV32I-NEXT: bne a1, a3, .LBB11_7
315 ; RV32I-NEXT: .LBB11_3:
316 ; RV32I-NEXT: bgeu a3, a1, .LBB11_8
317 ; RV32I-NEXT: .LBB11_4:
318 ; RV32I-NEXT: ret
319 ; RV32I-NEXT: .LBB11_5:
320 ; RV32I-NEXT: mv a4, a2
321 ; RV32I-NEXT: bltu a2, a0, .LBB11_2
322 ; RV32I-NEXT: .LBB11_6:
323 ; RV32I-NEXT: mv a0, a2
324 ; RV32I-NEXT: beq a1, a3, .LBB11_3
325 ; RV32I-NEXT: .LBB11_7:
326 ; RV32I-NEXT: mv a0, a4
327 ; RV32I-NEXT: bltu a3, a1, .LBB11_4
328 ; RV32I-NEXT: .LBB11_8:
329 ; RV32I-NEXT: mv a1, a3
330 ; RV32I-NEXT: ret
331 ;
332 ; RV64I-LABEL: umax_i64:
333 ; RV64I: # %bb.0:
334 ; RV64I-NEXT: bltu a1, a0, .LBB11_2
335 ; RV64I-NEXT: # %bb.1:
336 ; RV64I-NEXT: mv a0, a1
337 ; RV64I-NEXT: .LBB11_2:
338 ; RV64I-NEXT: ret
339 ;
340 ; RV32ZBB-LABEL: umax_i64:
341 ; RV32ZBB: # %bb.0:
342 ; RV32ZBB-NEXT: mv a4, a0
343 ; RV32ZBB-NEXT: bgeu a3, a1, .LBB11_3
344 ; RV32ZBB-NEXT: # %bb.1:
345 ; RV32ZBB-NEXT: beq a1, a3, .LBB11_4
346 ; RV32ZBB-NEXT: .LBB11_2:
347 ; RV32ZBB-NEXT: maxu a1, a1, a3
348 ; RV32ZBB-NEXT: ret
349 ; RV32ZBB-NEXT: .LBB11_3:
350 ; RV32ZBB-NEXT: mv a0, a2
351 ; RV32ZBB-NEXT: bne a1, a3, .LBB11_2
352 ; RV32ZBB-NEXT: .LBB11_4:
353 ; RV32ZBB-NEXT: maxu a0, a4, a2
354 ; RV32ZBB-NEXT: maxu a1, a1, a3
355 ; RV32ZBB-NEXT: ret
356 ;
357 ; RV64ZBB-LABEL: umax_i64:
358 ; RV64ZBB: # %bb.0:
359 ; RV64ZBB-NEXT: maxu a0, a0, a1
360 ; RV64ZBB-NEXT: ret
361 %c = call i64 @llvm.umax.i64(i64 %a, i64 %b)
362 ret i64 %c
363 }
365 declare i8 @llvm.umin.i8(i8 %a, i8 %b) readnone
367 define zeroext i8 @umin_i8(i8 zeroext %a, i8 zeroext %b) {
368 ; NOZBB-LABEL: umin_i8:
369 ; NOZBB: # %bb.0:
370 ; NOZBB-NEXT: bltu a0, a1, .LBB12_2
371 ; NOZBB-NEXT: # %bb.1:
372 ; NOZBB-NEXT: mv a0, a1
373 ; NOZBB-NEXT: .LBB12_2:
374 ; NOZBB-NEXT: ret
375 ;
376 ; ZBB-LABEL: umin_i8:
377 ; ZBB: # %bb.0:
378 ; ZBB-NEXT: minu a0, a0, a1
379 ; ZBB-NEXT: ret
380 %c = call i8 @llvm.umin.i8(i8 %a, i8 %b)
381 ret i8 %c
382 }
384 declare i16 @llvm.umin.i16(i16 %a, i16 %b) readnone
386 define zeroext i16 @umin_i16(i16 zeroext %a, i16 zeroext %b) {
387 ; NOZBB-LABEL: umin_i16:
388 ; NOZBB: # %bb.0:
389 ; NOZBB-NEXT: bltu a0, a1, .LBB13_2
390 ; NOZBB-NEXT: # %bb.1:
391 ; NOZBB-NEXT: mv a0, a1
392 ; NOZBB-NEXT: .LBB13_2:
393 ; NOZBB-NEXT: ret
394 ;
395 ; ZBB-LABEL: umin_i16:
396 ; ZBB: # %bb.0:
397 ; ZBB-NEXT: minu a0, a0, a1
398 ; ZBB-NEXT: ret
399 %c = call i16 @llvm.umin.i16(i16 %a, i16 %b)
400 ret i16 %c
401 }
403 declare i32 @llvm.umin.i32(i32 %a, i32 %b) readnone
405 define signext i32 @umin_i32(i32 signext %a, i32 signext %b) {
406 ; NOZBB-LABEL: umin_i32:
407 ; NOZBB: # %bb.0:
408 ; NOZBB-NEXT: bltu a0, a1, .LBB14_2
409 ; NOZBB-NEXT: # %bb.1:
410 ; NOZBB-NEXT: mv a0, a1
411 ; NOZBB-NEXT: .LBB14_2:
412 ; NOZBB-NEXT: ret
413 ;
414 ; ZBB-LABEL: umin_i32:
415 ; ZBB: # %bb.0:
416 ; ZBB-NEXT: minu a0, a0, a1
417 ; ZBB-NEXT: ret
418 %c = call i32 @llvm.umin.i32(i32 %a, i32 %b)
419 ret i32 %c
420 }
422 declare i64 @llvm.umin.i64(i64 %a, i64 %b) readnone
424 define i64 @umin_i64(i64 %a, i64 %b) {
425 ; RV32I-LABEL: umin_i64:
426 ; RV32I: # %bb.0:
427 ; RV32I-NEXT: mv a4, a0
428 ; RV32I-NEXT: bgeu a1, a3, .LBB15_5
429 ; RV32I-NEXT: # %bb.1:
430 ; RV32I-NEXT: bgeu a0, a2, .LBB15_6
431 ; RV32I-NEXT: .LBB15_2:
432 ; RV32I-NEXT: bne a1, a3, .LBB15_7
433 ; RV32I-NEXT: .LBB15_3:
434 ; RV32I-NEXT: bgeu a1, a3, .LBB15_8
435 ; RV32I-NEXT: .LBB15_4:
436 ; RV32I-NEXT: ret
437 ; RV32I-NEXT: .LBB15_5:
438 ; RV32I-NEXT: mv a4, a2
439 ; RV32I-NEXT: bltu a0, a2, .LBB15_2
440 ; RV32I-NEXT: .LBB15_6:
441 ; RV32I-NEXT: mv a0, a2
442 ; RV32I-NEXT: beq a1, a3, .LBB15_3
443 ; RV32I-NEXT: .LBB15_7:
444 ; RV32I-NEXT: mv a0, a4
445 ; RV32I-NEXT: bltu a1, a3, .LBB15_4
446 ; RV32I-NEXT: .LBB15_8:
447 ; RV32I-NEXT: mv a1, a3
448 ; RV32I-NEXT: ret
449 ;
450 ; RV64I-LABEL: umin_i64:
451 ; RV64I: # %bb.0:
452 ; RV64I-NEXT: bltu a0, a1, .LBB15_2
453 ; RV64I-NEXT: # %bb.1:
454 ; RV64I-NEXT: mv a0, a1
455 ; RV64I-NEXT: .LBB15_2:
456 ; RV64I-NEXT: ret
457 ;
458 ; RV32ZBB-LABEL: umin_i64:
459 ; RV32ZBB: # %bb.0:
460 ; RV32ZBB-NEXT: mv a4, a0
461 ; RV32ZBB-NEXT: bgeu a1, a3, .LBB15_3
462 ; RV32ZBB-NEXT: # %bb.1:
463 ; RV32ZBB-NEXT: beq a1, a3, .LBB15_4
464 ; RV32ZBB-NEXT: .LBB15_2:
465 ; RV32ZBB-NEXT: minu a1, a1, a3
466 ; RV32ZBB-NEXT: ret
467 ; RV32ZBB-NEXT: .LBB15_3:
468 ; RV32ZBB-NEXT: mv a0, a2
469 ; RV32ZBB-NEXT: bne a1, a3, .LBB15_2
470 ; RV32ZBB-NEXT: .LBB15_4:
471 ; RV32ZBB-NEXT: minu a0, a4, a2
472 ; RV32ZBB-NEXT: minu a1, a1, a3
473 ; RV32ZBB-NEXT: ret
474 ;
475 ; RV64ZBB-LABEL: umin_i64:
476 ; RV64ZBB: # %bb.0:
477 ; RV64ZBB-NEXT: minu a0, a0, a1
478 ; RV64ZBB-NEXT: ret
479 %c = call i64 @llvm.umin.i64(i64 %a, i64 %b)
480 ret i64 %c
481 }
483 ; Tests with the same operand used twice. These should fold away.
485 define signext i32 @smin_same_op_i32(i32 signext %a) {
486 ; NOZBB-LABEL: smin_same_op_i32:
487 ; NOZBB: # %bb.0:
488 ; NOZBB-NEXT: ret
489 ;
490 ; ZBB-LABEL: smin_same_op_i32:
491 ; ZBB: # %bb.0:
492 ; ZBB-NEXT: ret
493 %c = call i32 @llvm.smin.i32(i32 %a, i32 %a)
494 ret i32 %c
495 }
497 define signext i32 @smax_same_op_i32(i32 signext %a) {
498 ; NOZBB-LABEL: smax_same_op_i32:
499 ; NOZBB: # %bb.0:
500 ; NOZBB-NEXT: ret
501 ;
502 ; ZBB-LABEL: smax_same_op_i32:
503 ; ZBB: # %bb.0:
504 ; ZBB-NEXT: ret
505 %c = call i32 @llvm.smax.i32(i32 %a, i32 %a)
506 ret i32 %c
507 }
509 define signext i32 @umin_same_op_i32(i32 signext %a) {
510 ; NOZBB-LABEL: umin_same_op_i32:
511 ; NOZBB: # %bb.0:
512 ; NOZBB-NEXT: ret
513 ;
514 ; ZBB-LABEL: umin_same_op_i32:
515 ; ZBB: # %bb.0:
516 ; ZBB-NEXT: ret
517 %c = call i32 @llvm.umin.i32(i32 %a, i32 %a)
518 ret i32 %c
519 }
521 define signext i32 @umax_same_op_i32(i32 signext %a) {
522 ; NOZBB-LABEL: umax_same_op_i32:
523 ; NOZBB: # %bb.0:
524 ; NOZBB-NEXT: ret
525 ;
526 ; ZBB-LABEL: umax_same_op_i32:
527 ; ZBB: # %bb.0:
528 ; ZBB-NEXT: ret
529 %c = call i32 @llvm.umax.i32(i32 %a, i32 %a)
530 ret i32 %c
531 }
533 ; Tests with undef operands. These should fold to undef for RV32 or 0 for RV64.
535 define signext i32 @smin_undef_i32() {
536 ; RV32I-LABEL: smin_undef_i32:
537 ; RV32I: # %bb.0:
538 ; RV32I-NEXT: ret
539 ;
540 ; RV64I-LABEL: smin_undef_i32:
541 ; RV64I: # %bb.0:
542 ; RV64I-NEXT: li a0, 0
543 ; RV64I-NEXT: ret
544 ;
545 ; RV32ZBB-LABEL: smin_undef_i32:
546 ; RV32ZBB: # %bb.0:
547 ; RV32ZBB-NEXT: ret
548 ;
549 ; RV64ZBB-LABEL: smin_undef_i32:
550 ; RV64ZBB: # %bb.0:
551 ; RV64ZBB-NEXT: li a0, 0
552 ; RV64ZBB-NEXT: ret
553 %c = call i32 @llvm.smin.i32(i32 undef, i32 undef)
554 ret i32 %c
555 }
557 define signext i32 @smax_undef_i32() {
558 ; RV32I-LABEL: smax_undef_i32:
559 ; RV32I: # %bb.0:
560 ; RV32I-NEXT: ret
561 ;
562 ; RV64I-LABEL: smax_undef_i32:
563 ; RV64I: # %bb.0:
564 ; RV64I-NEXT: li a0, 0
565 ; RV64I-NEXT: ret
566 ;
567 ; RV32ZBB-LABEL: smax_undef_i32:
568 ; RV32ZBB: # %bb.0:
569 ; RV32ZBB-NEXT: ret
570 ;
571 ; RV64ZBB-LABEL: smax_undef_i32:
572 ; RV64ZBB: # %bb.0:
573 ; RV64ZBB-NEXT: li a0, 0
574 ; RV64ZBB-NEXT: ret
575 %c = call i32 @llvm.smax.i32(i32 undef, i32 undef)
576 ret i32 %c
577 }
579 define signext i32 @umin_undef_i32() {
580 ; RV32I-LABEL: umin_undef_i32:
581 ; RV32I: # %bb.0:
582 ; RV32I-NEXT: ret
583 ;
584 ; RV64I-LABEL: umin_undef_i32:
585 ; RV64I: # %bb.0:
586 ; RV64I-NEXT: li a0, 0
587 ; RV64I-NEXT: ret
588 ;
589 ; RV32ZBB-LABEL: umin_undef_i32:
590 ; RV32ZBB: # %bb.0:
591 ; RV32ZBB-NEXT: ret
592 ;
593 ; RV64ZBB-LABEL: umin_undef_i32:
594 ; RV64ZBB: # %bb.0:
595 ; RV64ZBB-NEXT: li a0, 0
596 ; RV64ZBB-NEXT: ret
597 %c = call i32 @llvm.umin.i32(i32 undef, i32 undef)
598 ret i32 %c
599 }
601 define signext i32 @umax_undef_i32() {
602 ; RV32I-LABEL: umax_undef_i32:
603 ; RV32I: # %bb.0:
604 ; RV32I-NEXT: ret
605 ;
606 ; RV64I-LABEL: umax_undef_i32:
607 ; RV64I: # %bb.0:
608 ; RV64I-NEXT: li a0, 0
609 ; RV64I-NEXT: ret
610 ;
611 ; RV32ZBB-LABEL: umax_undef_i32:
612 ; RV32ZBB: # %bb.0:
613 ; RV32ZBB-NEXT: ret
614 ;
615 ; RV64ZBB-LABEL: umax_undef_i32:
616 ; RV64ZBB: # %bb.0:
617 ; RV64ZBB-NEXT: li a0, 0
618 ; RV64ZBB-NEXT: ret
619 %c = call i32 @llvm.umax.i32(i32 undef, i32 undef)
620 ret i32 %c
621 }
623 define signext i32 @smax_i32_pos_constant(i32 signext %a) {
624 ; NOZBB-LABEL: smax_i32_pos_constant:
625 ; NOZBB: # %bb.0:
626 ; NOZBB-NEXT: li a1, 10
627 ; NOZBB-NEXT: blt a1, a0, .LBB24_2
628 ; NOZBB-NEXT: # %bb.1:
629 ; NOZBB-NEXT: li a0, 10
630 ; NOZBB-NEXT: .LBB24_2:
631 ; NOZBB-NEXT: ret
632 ;
633 ; ZBB-LABEL: smax_i32_pos_constant:
634 ; ZBB: # %bb.0:
635 ; ZBB-NEXT: li a1, 10
636 ; ZBB-NEXT: max a0, a0, a1
637 ; ZBB-NEXT: ret
638 %c = call i32 @llvm.smax.i32(i32 %a, i32 10)
639 ret i32 %c
640 }
642 define signext i32 @smax_i32_pos_constant_trailing_zeros(i32 signext %a) {
643 ; NOZBB-LABEL: smax_i32_pos_constant_trailing_zeros:
644 ; NOZBB: # %bb.0:
645 ; NOZBB-NEXT: andi a0, a0, -8
646 ; NOZBB-NEXT: li a1, 16
647 ; NOZBB-NEXT: blt a1, a0, .LBB25_2
648 ; NOZBB-NEXT: # %bb.1:
649 ; NOZBB-NEXT: li a0, 16
650 ; NOZBB-NEXT: .LBB25_2:
651 ; NOZBB-NEXT: ret
652 ;
653 ; ZBB-LABEL: smax_i32_pos_constant_trailing_zeros:
654 ; ZBB: # %bb.0:
655 ; ZBB-NEXT: andi a0, a0, -8
656 ; ZBB-NEXT: li a1, 16
657 ; ZBB-NEXT: max a0, a0, a1
658 ; ZBB-NEXT: ret
659 %b = and i32 %a, -8
660 %c = call i32 @llvm.smax.i32(i32 %b, i32 16)
661 %d = and i32 %c, -4
662 ret i32 %d
663 }
665 define signext i32 @smin_i32_negone(i32 signext %a) {
666 ; NOZBB-LABEL: smin_i32_negone:
667 ; NOZBB: # %bb.0:
668 ; NOZBB-NEXT: bltz a0, .LBB26_2
669 ; NOZBB-NEXT: # %bb.1:
670 ; NOZBB-NEXT: li a0, -1
671 ; NOZBB-NEXT: .LBB26_2:
672 ; NOZBB-NEXT: ret
673 ;
674 ; ZBB-LABEL: smin_i32_negone:
675 ; ZBB: # %bb.0:
676 ; ZBB-NEXT: li a1, -1
677 ; ZBB-NEXT: min a0, a0, a1
678 ; ZBB-NEXT: ret
679 %c = call i32 @llvm.smin.i32(i32 %a, i32 -1)
680 ret i32 %c
681 }
683 define i64 @smin_i64_negone(i64 %a) {
684 ; RV32I-LABEL: smin_i64_negone:
685 ; RV32I: # %bb.0:
686 ; RV32I-NEXT: li a2, -1
687 ; RV32I-NEXT: mv a3, a0
688 ; RV32I-NEXT: bge a1, a2, .LBB27_4
689 ; RV32I-NEXT: # %bb.1:
690 ; RV32I-NEXT: bne a1, a2, .LBB27_5
691 ; RV32I-NEXT: .LBB27_2:
692 ; RV32I-NEXT: bgez a1, .LBB27_6
693 ; RV32I-NEXT: .LBB27_3:
694 ; RV32I-NEXT: ret
695 ; RV32I-NEXT: .LBB27_4:
696 ; RV32I-NEXT: li a3, -1
697 ; RV32I-NEXT: beq a1, a2, .LBB27_2
698 ; RV32I-NEXT: .LBB27_5:
699 ; RV32I-NEXT: mv a0, a3
700 ; RV32I-NEXT: bltz a1, .LBB27_3
701 ; RV32I-NEXT: .LBB27_6:
702 ; RV32I-NEXT: li a1, -1
703 ; RV32I-NEXT: ret
704 ;
705 ; RV64I-LABEL: smin_i64_negone:
706 ; RV64I: # %bb.0:
707 ; RV64I-NEXT: bltz a0, .LBB27_2
708 ; RV64I-NEXT: # %bb.1:
709 ; RV64I-NEXT: li a0, -1
710 ; RV64I-NEXT: .LBB27_2:
711 ; RV64I-NEXT: ret
712 ;
713 ; RV32ZBB-LABEL: smin_i64_negone:
714 ; RV32ZBB: # %bb.0:
715 ; RV32ZBB-NEXT: li a2, -1
716 ; RV32ZBB-NEXT: mv a3, a0
717 ; RV32ZBB-NEXT: bge a1, a2, .LBB27_3
718 ; RV32ZBB-NEXT: # %bb.1:
719 ; RV32ZBB-NEXT: bne a1, a2, .LBB27_4
720 ; RV32ZBB-NEXT: .LBB27_2:
721 ; RV32ZBB-NEXT: min a1, a1, a2
722 ; RV32ZBB-NEXT: ret
723 ; RV32ZBB-NEXT: .LBB27_3:
724 ; RV32ZBB-NEXT: li a3, -1
725 ; RV32ZBB-NEXT: beq a1, a2, .LBB27_2
726 ; RV32ZBB-NEXT: .LBB27_4:
727 ; RV32ZBB-NEXT: mv a0, a3
728 ; RV32ZBB-NEXT: min a1, a1, a2
729 ; RV32ZBB-NEXT: ret
730 ;
731 ; RV64ZBB-LABEL: smin_i64_negone:
732 ; RV64ZBB: # %bb.0:
733 ; RV64ZBB-NEXT: li a1, -1
734 ; RV64ZBB-NEXT: min a0, a0, a1
735 ; RV64ZBB-NEXT: ret
736 %c = call i64 @llvm.smin.i64(i64 %a, i64 -1)
737 ret i64 %c
738 }