| blob | 48c6878f53f1f9cf700d68e5dd93e20e51337e37 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
3 ; RUN: | FileCheck %s -check-prefix=RV64I
4 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp -verify-machineinstrs < %s \
5 ; RUN: | FileCheck %s -check-prefix=RV64ZBP
7 define signext i32 @gorc1_i32(i32 signext %a) nounwind {
8 ; RV64I-LABEL: gorc1_i32:
9 ; RV64I: # %bb.0:
10 ; RV64I-NEXT: slliw a1, a0, 1
11 ; RV64I-NEXT: lui a2, 699051
12 ; RV64I-NEXT: addiw a2, a2, -1366
13 ; RV64I-NEXT: and a1, a1, a2
14 ; RV64I-NEXT: srli a2, a0, 1
15 ; RV64I-NEXT: lui a3, 349525
16 ; RV64I-NEXT: addiw a3, a3, 1365
17 ; RV64I-NEXT: and a2, a2, a3
18 ; RV64I-NEXT: or a0, a2, a0
19 ; RV64I-NEXT: or a0, a0, a1
20 ; RV64I-NEXT: ret
21 ;
22 ; RV64ZBP-LABEL: gorc1_i32:
23 ; RV64ZBP: # %bb.0:
24 ; RV64ZBP-NEXT: gorciw a0, a0, 1
25 ; RV64ZBP-NEXT: ret
26 %and = shl i32 %a, 1
27 %shl = and i32 %and, -1431655766
28 %and1 = lshr i32 %a, 1
29 %shr = and i32 %and1, 1431655765
30 %or = or i32 %shr, %a
31 %or2 = or i32 %or, %shl
32 ret i32 %or2
33 }
35 define i64 @gorc1_i64(i64 %a) nounwind {
36 ; RV64I-LABEL: gorc1_i64:
37 ; RV64I: # %bb.0:
38 ; RV64I-NEXT: lui a1, %hi(.LCPI1_0)
39 ; RV64I-NEXT: ld a1, %lo(.LCPI1_0)(a1)
40 ; RV64I-NEXT: lui a2, %hi(.LCPI1_1)
41 ; RV64I-NEXT: ld a2, %lo(.LCPI1_1)(a2)
42 ; RV64I-NEXT: slli a3, a0, 1
43 ; RV64I-NEXT: and a1, a3, a1
44 ; RV64I-NEXT: srli a3, a0, 1
45 ; RV64I-NEXT: and a2, a3, a2
46 ; RV64I-NEXT: or a0, a2, a0
47 ; RV64I-NEXT: or a0, a0, a1
48 ; RV64I-NEXT: ret
49 ;
50 ; RV64ZBP-LABEL: gorc1_i64:
51 ; RV64ZBP: # %bb.0:
52 ; RV64ZBP-NEXT: orc.p a0, a0
53 ; RV64ZBP-NEXT: ret
54 %and = shl i64 %a, 1
55 %shl = and i64 %and, -6148914691236517206
56 %and1 = lshr i64 %a, 1
57 %shr = and i64 %and1, 6148914691236517205
58 %or = or i64 %shr, %a
59 %or2 = or i64 %or, %shl
60 ret i64 %or2
61 }
63 define signext i32 @gorc2_i32(i32 signext %a) nounwind {
64 ; RV64I-LABEL: gorc2_i32:
65 ; RV64I: # %bb.0:
66 ; RV64I-NEXT: slliw a1, a0, 2
67 ; RV64I-NEXT: lui a2, 838861
68 ; RV64I-NEXT: addiw a2, a2, -820
69 ; RV64I-NEXT: and a1, a1, a2
70 ; RV64I-NEXT: srli a2, a0, 2
71 ; RV64I-NEXT: lui a3, 209715
72 ; RV64I-NEXT: addiw a3, a3, 819
73 ; RV64I-NEXT: and a2, a2, a3
74 ; RV64I-NEXT: or a0, a2, a0
75 ; RV64I-NEXT: or a0, a0, a1
76 ; RV64I-NEXT: ret
77 ;
78 ; RV64ZBP-LABEL: gorc2_i32:
79 ; RV64ZBP: # %bb.0:
80 ; RV64ZBP-NEXT: gorciw a0, a0, 2
81 ; RV64ZBP-NEXT: ret
82 %and = shl i32 %a, 2
83 %shl = and i32 %and, -858993460
84 %and1 = lshr i32 %a, 2
85 %shr = and i32 %and1, 858993459
86 %or = or i32 %shr, %a
87 %or2 = or i32 %or, %shl
88 ret i32 %or2
89 }
91 define i64 @gorc2_i64(i64 %a) nounwind {
92 ; RV64I-LABEL: gorc2_i64:
93 ; RV64I: # %bb.0:
94 ; RV64I-NEXT: lui a1, %hi(.LCPI3_0)
95 ; RV64I-NEXT: ld a1, %lo(.LCPI3_0)(a1)
96 ; RV64I-NEXT: lui a2, %hi(.LCPI3_1)
97 ; RV64I-NEXT: ld a2, %lo(.LCPI3_1)(a2)
98 ; RV64I-NEXT: slli a3, a0, 2
99 ; RV64I-NEXT: and a1, a3, a1
100 ; RV64I-NEXT: srli a3, a0, 2
101 ; RV64I-NEXT: and a2, a3, a2
102 ; RV64I-NEXT: or a0, a2, a0
103 ; RV64I-NEXT: or a0, a0, a1
104 ; RV64I-NEXT: ret
105 ;
106 ; RV64ZBP-LABEL: gorc2_i64:
107 ; RV64ZBP: # %bb.0:
108 ; RV64ZBP-NEXT: orc2.n a0, a0
109 ; RV64ZBP-NEXT: ret
110 %and = shl i64 %a, 2
111 %shl = and i64 %and, -3689348814741910324
112 %and1 = lshr i64 %a, 2
113 %shr = and i64 %and1, 3689348814741910323
114 %or = or i64 %shr, %a
115 %or2 = or i64 %or, %shl
116 ret i64 %or2
117 }
119 define signext i32 @gorc3_i32(i32 signext %a) nounwind {
120 ; RV64I-LABEL: gorc3_i32:
121 ; RV64I: # %bb.0:
122 ; RV64I-NEXT: slliw a1, a0, 1
123 ; RV64I-NEXT: lui a2, 699051
124 ; RV64I-NEXT: addiw a2, a2, -1366
125 ; RV64I-NEXT: and a1, a1, a2
126 ; RV64I-NEXT: srli a2, a0, 1
127 ; RV64I-NEXT: lui a3, 349525
128 ; RV64I-NEXT: addiw a3, a3, 1365
129 ; RV64I-NEXT: and a2, a2, a3
130 ; RV64I-NEXT: or a0, a2, a0
131 ; RV64I-NEXT: or a0, a0, a1
132 ; RV64I-NEXT: slliw a1, a0, 2
133 ; RV64I-NEXT: lui a2, 838861
134 ; RV64I-NEXT: addiw a2, a2, -820
135 ; RV64I-NEXT: and a1, a1, a2
136 ; RV64I-NEXT: srli a2, a0, 2
137 ; RV64I-NEXT: lui a3, 209715
138 ; RV64I-NEXT: addiw a3, a3, 819
139 ; RV64I-NEXT: and a2, a2, a3
140 ; RV64I-NEXT: or a0, a2, a0
141 ; RV64I-NEXT: or a0, a0, a1
142 ; RV64I-NEXT: ret
143 ;
144 ; RV64ZBP-LABEL: gorc3_i32:
145 ; RV64ZBP: # %bb.0:
146 ; RV64ZBP-NEXT: gorciw a0, a0, 3
147 ; RV64ZBP-NEXT: ret
148 %and1 = shl i32 %a, 1
149 %shl1 = and i32 %and1, -1431655766
150 %and1b = lshr i32 %a, 1
151 %shr1 = and i32 %and1b, 1431655765
152 %or1 = or i32 %shr1, %a
153 %or1b = or i32 %or1, %shl1
154 %and2 = shl i32 %or1b, 2
155 %shl2 = and i32 %and2, -858993460
156 %and2b = lshr i32 %or1b, 2
157 %shr2 = and i32 %and2b, 858993459
158 %or2 = or i32 %shr2, %or1b
159 %or2b = or i32 %or2, %shl2
160 ret i32 %or2b
161 }
163 define i64 @gorc3_i64(i64 %a) nounwind {
164 ; RV64I-LABEL: gorc3_i64:
165 ; RV64I: # %bb.0:
166 ; RV64I-NEXT: lui a1, %hi(.LCPI5_0)
167 ; RV64I-NEXT: ld a1, %lo(.LCPI5_0)(a1)
168 ; RV64I-NEXT: lui a2, %hi(.LCPI5_1)
169 ; RV64I-NEXT: ld a2, %lo(.LCPI5_1)(a2)
170 ; RV64I-NEXT: slli a3, a0, 1
171 ; RV64I-NEXT: and a1, a3, a1
172 ; RV64I-NEXT: srli a3, a0, 1
173 ; RV64I-NEXT: and a2, a3, a2
174 ; RV64I-NEXT: or a0, a2, a0
175 ; RV64I-NEXT: or a0, a0, a1
176 ; RV64I-NEXT: lui a1, %hi(.LCPI5_2)
177 ; RV64I-NEXT: ld a1, %lo(.LCPI5_2)(a1)
178 ; RV64I-NEXT: lui a2, %hi(.LCPI5_3)
179 ; RV64I-NEXT: ld a2, %lo(.LCPI5_3)(a2)
180 ; RV64I-NEXT: slli a3, a0, 2
181 ; RV64I-NEXT: and a1, a3, a1
182 ; RV64I-NEXT: srli a3, a0, 2
183 ; RV64I-NEXT: and a2, a3, a2
184 ; RV64I-NEXT: or a0, a2, a0
185 ; RV64I-NEXT: or a0, a0, a1
186 ; RV64I-NEXT: ret
187 ;
188 ; RV64ZBP-LABEL: gorc3_i64:
189 ; RV64ZBP: # %bb.0:
190 ; RV64ZBP-NEXT: orc.n a0, a0
191 ; RV64ZBP-NEXT: ret
192 %and1 = shl i64 %a, 1
193 %shl1 = and i64 %and1, -6148914691236517206
194 %and1b = lshr i64 %a, 1
195 %shr1 = and i64 %and1b, 6148914691236517205
196 %or1 = or i64 %shr1, %a
197 %or1b = or i64 %or1, %shl1
198 %and2 = shl i64 %or1b, 2
199 %shl2 = and i64 %and2, -3689348814741910324
200 %and2b = lshr i64 %or1b, 2
201 %shr2 = and i64 %and2b, 3689348814741910323
202 %or2 = or i64 %shr2, %or1b
203 %or2b = or i64 %or2, %shl2
204 ret i64 %or2b
205 }
207 define signext i32 @gorc4_i32(i32 signext %a) nounwind {
208 ; RV64I-LABEL: gorc4_i32:
209 ; RV64I: # %bb.0:
210 ; RV64I-NEXT: slliw a1, a0, 4
211 ; RV64I-NEXT: lui a2, 986895
212 ; RV64I-NEXT: addiw a2, a2, 240
213 ; RV64I-NEXT: and a1, a1, a2
214 ; RV64I-NEXT: srli a2, a0, 4
215 ; RV64I-NEXT: lui a3, 61681
216 ; RV64I-NEXT: addiw a3, a3, -241
217 ; RV64I-NEXT: and a2, a2, a3
218 ; RV64I-NEXT: or a0, a2, a0
219 ; RV64I-NEXT: or a0, a0, a1
220 ; RV64I-NEXT: ret
221 ;
222 ; RV64ZBP-LABEL: gorc4_i32:
223 ; RV64ZBP: # %bb.0:
224 ; RV64ZBP-NEXT: gorciw a0, a0, 4
225 ; RV64ZBP-NEXT: ret
226 %and = shl i32 %a, 4
227 %shl = and i32 %and, -252645136
228 %and1 = lshr i32 %a, 4
229 %shr = and i32 %and1, 252645135
230 %or = or i32 %shr, %a
231 %or2 = or i32 %or, %shl
232 ret i32 %or2
233 }
235 define i64 @gorc4_i64(i64 %a) nounwind {
236 ; RV64I-LABEL: gorc4_i64:
237 ; RV64I: # %bb.0:
238 ; RV64I-NEXT: lui a1, %hi(.LCPI7_0)
239 ; RV64I-NEXT: ld a1, %lo(.LCPI7_0)(a1)
240 ; RV64I-NEXT: lui a2, %hi(.LCPI7_1)
241 ; RV64I-NEXT: ld a2, %lo(.LCPI7_1)(a2)
242 ; RV64I-NEXT: slli a3, a0, 4
243 ; RV64I-NEXT: and a1, a3, a1
244 ; RV64I-NEXT: srli a3, a0, 4
245 ; RV64I-NEXT: and a2, a3, a2
246 ; RV64I-NEXT: or a0, a2, a0
247 ; RV64I-NEXT: or a0, a0, a1
248 ; RV64I-NEXT: ret
249 ;
250 ; RV64ZBP-LABEL: gorc4_i64:
251 ; RV64ZBP: # %bb.0:
252 ; RV64ZBP-NEXT: orc4.b a0, a0
253 ; RV64ZBP-NEXT: ret
254 %and = shl i64 %a, 4
255 %shl = and i64 %and, -1085102592571150096
256 %and1 = lshr i64 %a, 4
257 %shr = and i64 %and1, 1085102592571150095
258 %or = or i64 %shr, %a
259 %or2 = or i64 %or, %shl
260 ret i64 %or2
261 }
263 define signext i32 @gorc5_i32(i32 signext %a) nounwind {
264 ; RV64I-LABEL: gorc5_i32:
265 ; RV64I: # %bb.0:
266 ; RV64I-NEXT: slliw a1, a0, 1
267 ; RV64I-NEXT: lui a2, 699051
268 ; RV64I-NEXT: addiw a2, a2, -1366
269 ; RV64I-NEXT: and a1, a1, a2
270 ; RV64I-NEXT: srli a2, a0, 1
271 ; RV64I-NEXT: lui a3, 349525
272 ; RV64I-NEXT: addiw a3, a3, 1365
273 ; RV64I-NEXT: and a2, a2, a3
274 ; RV64I-NEXT: or a0, a2, a0
275 ; RV64I-NEXT: or a0, a0, a1
276 ; RV64I-NEXT: slliw a1, a0, 4
277 ; RV64I-NEXT: lui a2, 986895
278 ; RV64I-NEXT: addiw a2, a2, 240
279 ; RV64I-NEXT: and a1, a1, a2
280 ; RV64I-NEXT: srli a2, a0, 4
281 ; RV64I-NEXT: lui a3, 61681
282 ; RV64I-NEXT: addiw a3, a3, -241
283 ; RV64I-NEXT: and a2, a2, a3
284 ; RV64I-NEXT: or a0, a2, a0
285 ; RV64I-NEXT: or a0, a0, a1
286 ; RV64I-NEXT: ret
287 ;
288 ; RV64ZBP-LABEL: gorc5_i32:
289 ; RV64ZBP: # %bb.0:
290 ; RV64ZBP-NEXT: gorciw a0, a0, 5
291 ; RV64ZBP-NEXT: ret
292 %and1 = shl i32 %a, 1
293 %shl1 = and i32 %and1, -1431655766
294 %and1b = lshr i32 %a, 1
295 %shr1 = and i32 %and1b, 1431655765
296 %or1 = or i32 %shr1, %a
297 %or1b = or i32 %or1, %shl1
298 %and2 = shl i32 %or1b, 4
299 %shl2 = and i32 %and2, -252645136
300 %and2b = lshr i32 %or1b, 4
301 %shr2 = and i32 %and2b, 252645135
302 %or2 = or i32 %shr2, %or1b
303 %or2b = or i32 %or2, %shl2
304 ret i32 %or2b
305 }
307 define i64 @gorc5_i64(i64 %a) nounwind {
308 ; RV64I-LABEL: gorc5_i64:
309 ; RV64I: # %bb.0:
310 ; RV64I-NEXT: lui a1, %hi(.LCPI9_0)
311 ; RV64I-NEXT: ld a1, %lo(.LCPI9_0)(a1)
312 ; RV64I-NEXT: lui a2, %hi(.LCPI9_1)
313 ; RV64I-NEXT: ld a2, %lo(.LCPI9_1)(a2)
314 ; RV64I-NEXT: slli a3, a0, 1
315 ; RV64I-NEXT: and a1, a3, a1
316 ; RV64I-NEXT: srli a3, a0, 1
317 ; RV64I-NEXT: and a2, a3, a2
318 ; RV64I-NEXT: or a0, a2, a0
319 ; RV64I-NEXT: or a0, a0, a1
320 ; RV64I-NEXT: lui a1, %hi(.LCPI9_2)
321 ; RV64I-NEXT: ld a1, %lo(.LCPI9_2)(a1)
322 ; RV64I-NEXT: lui a2, %hi(.LCPI9_3)
323 ; RV64I-NEXT: ld a2, %lo(.LCPI9_3)(a2)
324 ; RV64I-NEXT: slli a3, a0, 4
325 ; RV64I-NEXT: and a1, a3, a1
326 ; RV64I-NEXT: srli a3, a0, 4
327 ; RV64I-NEXT: and a2, a3, a2
328 ; RV64I-NEXT: or a0, a2, a0
329 ; RV64I-NEXT: or a0, a0, a1
330 ; RV64I-NEXT: ret
331 ;
332 ; RV64ZBP-LABEL: gorc5_i64:
333 ; RV64ZBP: # %bb.0:
334 ; RV64ZBP-NEXT: gorci a0, a0, 5
335 ; RV64ZBP-NEXT: ret
336 %and1 = shl i64 %a, 1
337 %shl1 = and i64 %and1, -6148914691236517206
338 %and1b = lshr i64 %a, 1
339 %shr1 = and i64 %and1b, 6148914691236517205
340 %or1 = or i64 %shr1, %a
341 %or1b = or i64 %or1, %shl1
342 %and2 = shl i64 %or1b, 4
343 %shl2 = and i64 %and2, -1085102592571150096
344 %and2b = lshr i64 %or1b, 4
345 %shr2 = and i64 %and2b, 1085102592571150095
346 %or2 = or i64 %shr2, %or1b
347 %or2b = or i64 %or2, %shl2
348 ret i64 %or2b
349 }
351 define signext i32 @gorc6_i32(i32 signext %a) nounwind {
352 ; RV64I-LABEL: gorc6_i32:
353 ; RV64I: # %bb.0:
354 ; RV64I-NEXT: slliw a1, a0, 2
355 ; RV64I-NEXT: lui a2, 838861
356 ; RV64I-NEXT: addiw a2, a2, -820
357 ; RV64I-NEXT: and a1, a1, a2
358 ; RV64I-NEXT: srli a2, a0, 2
359 ; RV64I-NEXT: lui a3, 209715
360 ; RV64I-NEXT: addiw a3, a3, 819
361 ; RV64I-NEXT: and a2, a2, a3
362 ; RV64I-NEXT: or a0, a2, a0
363 ; RV64I-NEXT: or a0, a0, a1
364 ; RV64I-NEXT: slliw a1, a0, 4
365 ; RV64I-NEXT: lui a2, 986895
366 ; RV64I-NEXT: addiw a2, a2, 240
367 ; RV64I-NEXT: and a1, a1, a2
368 ; RV64I-NEXT: srli a2, a0, 4
369 ; RV64I-NEXT: lui a3, 61681
370 ; RV64I-NEXT: addiw a3, a3, -241
371 ; RV64I-NEXT: and a2, a2, a3
372 ; RV64I-NEXT: or a0, a2, a0
373 ; RV64I-NEXT: or a0, a0, a1
374 ; RV64I-NEXT: ret
375 ;
376 ; RV64ZBP-LABEL: gorc6_i32:
377 ; RV64ZBP: # %bb.0:
378 ; RV64ZBP-NEXT: gorciw a0, a0, 6
379 ; RV64ZBP-NEXT: ret
380 %and1 = shl i32 %a, 2
381 %shl1 = and i32 %and1, -858993460
382 %and1b = lshr i32 %a, 2
383 %shr1 = and i32 %and1b, 858993459
384 %or1 = or i32 %shr1, %a
385 %or1b = or i32 %or1, %shl1
386 %and2 = shl i32 %or1b, 4
387 %shl2 = and i32 %and2, -252645136
388 %and2b = lshr i32 %or1b, 4
389 %shr2 = and i32 %and2b, 252645135
390 %or2 = or i32 %shr2, %or1b
391 %or2b = or i32 %or2, %shl2
392 ret i32 %or2b
393 }
395 define i64 @gorc6_i64(i64 %a) nounwind {
396 ; RV64I-LABEL: gorc6_i64:
397 ; RV64I: # %bb.0:
398 ; RV64I-NEXT: lui a1, %hi(.LCPI11_0)
399 ; RV64I-NEXT: ld a1, %lo(.LCPI11_0)(a1)
400 ; RV64I-NEXT: lui a2, %hi(.LCPI11_1)
401 ; RV64I-NEXT: ld a2, %lo(.LCPI11_1)(a2)
402 ; RV64I-NEXT: slli a3, a0, 2
403 ; RV64I-NEXT: and a1, a3, a1
404 ; RV64I-NEXT: srli a3, a0, 2
405 ; RV64I-NEXT: and a2, a3, a2
406 ; RV64I-NEXT: or a0, a2, a0
407 ; RV64I-NEXT: or a0, a0, a1
408 ; RV64I-NEXT: lui a1, %hi(.LCPI11_2)
409 ; RV64I-NEXT: ld a1, %lo(.LCPI11_2)(a1)
410 ; RV64I-NEXT: lui a2, %hi(.LCPI11_3)
411 ; RV64I-NEXT: ld a2, %lo(.LCPI11_3)(a2)
412 ; RV64I-NEXT: slli a3, a0, 4
413 ; RV64I-NEXT: and a1, a3, a1
414 ; RV64I-NEXT: srli a3, a0, 4
415 ; RV64I-NEXT: and a2, a3, a2
416 ; RV64I-NEXT: or a0, a2, a0
417 ; RV64I-NEXT: or a0, a0, a1
418 ; RV64I-NEXT: ret
419 ;
420 ; RV64ZBP-LABEL: gorc6_i64:
421 ; RV64ZBP: # %bb.0:
422 ; RV64ZBP-NEXT: orc2.b a0, a0
423 ; RV64ZBP-NEXT: ret
424 %and1 = shl i64 %a, 2
425 %shl1 = and i64 %and1, -3689348814741910324
426 %and1b = lshr i64 %a, 2
427 %shr1 = and i64 %and1b, 3689348814741910323
428 %or1 = or i64 %shr1, %a
429 %or1b = or i64 %or1, %shl1
430 %and2 = shl i64 %or1b, 4
431 %shl2 = and i64 %and2, -1085102592571150096
432 %and2b = lshr i64 %or1b, 4
433 %shr2 = and i64 %and2b, 1085102592571150095
434 %or2 = or i64 %shr2, %or1b
435 %or2b = or i64 %or2, %shl2
436 ret i64 %or2b
437 }
439 define signext i32 @gorc7_i32(i32 signext %a) nounwind {
440 ; RV64I-LABEL: gorc7_i32:
441 ; RV64I: # %bb.0:
442 ; RV64I-NEXT: slliw a1, a0, 1
443 ; RV64I-NEXT: lui a2, 699051
444 ; RV64I-NEXT: addiw a2, a2, -1366
445 ; RV64I-NEXT: and a1, a1, a2
446 ; RV64I-NEXT: srli a2, a0, 1
447 ; RV64I-NEXT: lui a3, 349525
448 ; RV64I-NEXT: addiw a3, a3, 1365
449 ; RV64I-NEXT: and a2, a2, a3
450 ; RV64I-NEXT: or a0, a2, a0
451 ; RV64I-NEXT: or a0, a0, a1
452 ; RV64I-NEXT: slliw a1, a0, 2
453 ; RV64I-NEXT: lui a2, 838861
454 ; RV64I-NEXT: addiw a2, a2, -820
455 ; RV64I-NEXT: and a1, a1, a2
456 ; RV64I-NEXT: srli a2, a0, 2
457 ; RV64I-NEXT: lui a3, 209715
458 ; RV64I-NEXT: addiw a3, a3, 819
459 ; RV64I-NEXT: and a2, a2, a3
460 ; RV64I-NEXT: or a0, a2, a0
461 ; RV64I-NEXT: or a0, a0, a1
462 ; RV64I-NEXT: slli a1, a0, 4
463 ; RV64I-NEXT: lui a2, 986895
464 ; RV64I-NEXT: addiw a2, a2, 240
465 ; RV64I-NEXT: and a1, a1, a2
466 ; RV64I-NEXT: srli a2, a0, 4
467 ; RV64I-NEXT: lui a3, 61681
468 ; RV64I-NEXT: addiw a3, a3, -241
469 ; RV64I-NEXT: and a2, a2, a3
470 ; RV64I-NEXT: or a0, a2, a0
471 ; RV64I-NEXT: or a0, a0, a1
472 ; RV64I-NEXT: sext.w a0, a0
473 ; RV64I-NEXT: ret
474 ;
475 ; RV64ZBP-LABEL: gorc7_i32:
476 ; RV64ZBP: # %bb.0:
477 ; RV64ZBP-NEXT: gorciw a0, a0, 7
478 ; RV64ZBP-NEXT: ret
479 %and1 = shl i32 %a, 1
480 %shl1 = and i32 %and1, -1431655766
481 %and1b = lshr i32 %a, 1
482 %shr1 = and i32 %and1b, 1431655765
483 %or1 = or i32 %shr1, %a
484 %or1b = or i32 %or1, %shl1
485 %and2 = shl i32 %or1b, 2
486 %shl2 = and i32 %and2, -858993460
487 %and2b = lshr i32 %or1b, 2
488 %shr2 = and i32 %and2b, 858993459
489 %or2 = or i32 %shr2, %or1b
490 %or2b = or i32 %or2, %shl2
491 %and3 = shl i32 %or2b, 4
492 %shl3 = and i32 %and3, -252645136
493 %and3b = lshr i32 %or2b, 4
494 %shr3 = and i32 %and3b, 252645135
495 %or3 = or i32 %shr3, %or2b
496 %or3b = or i32 %or3, %shl3
497 ret i32 %or3b
498 }
500 define i64 @gorc7_i64(i64 %a) nounwind {
501 ; RV64I-LABEL: gorc7_i64:
502 ; RV64I: # %bb.0:
503 ; RV64I-NEXT: lui a1, %hi(.LCPI13_0)
504 ; RV64I-NEXT: ld a1, %lo(.LCPI13_0)(a1)
505 ; RV64I-NEXT: lui a2, %hi(.LCPI13_1)
506 ; RV64I-NEXT: ld a2, %lo(.LCPI13_1)(a2)
507 ; RV64I-NEXT: slli a3, a0, 1
508 ; RV64I-NEXT: and a1, a3, a1
509 ; RV64I-NEXT: srli a3, a0, 1
510 ; RV64I-NEXT: and a2, a3, a2
511 ; RV64I-NEXT: or a0, a2, a0
512 ; RV64I-NEXT: or a0, a0, a1
513 ; RV64I-NEXT: lui a1, %hi(.LCPI13_2)
514 ; RV64I-NEXT: ld a1, %lo(.LCPI13_2)(a1)
515 ; RV64I-NEXT: lui a2, %hi(.LCPI13_3)
516 ; RV64I-NEXT: ld a2, %lo(.LCPI13_3)(a2)
517 ; RV64I-NEXT: slli a3, a0, 2
518 ; RV64I-NEXT: and a1, a3, a1
519 ; RV64I-NEXT: srli a3, a0, 2
520 ; RV64I-NEXT: and a2, a3, a2
521 ; RV64I-NEXT: or a0, a2, a0
522 ; RV64I-NEXT: or a0, a0, a1
523 ; RV64I-NEXT: lui a1, %hi(.LCPI13_4)
524 ; RV64I-NEXT: ld a1, %lo(.LCPI13_4)(a1)
525 ; RV64I-NEXT: lui a2, %hi(.LCPI13_5)
526 ; RV64I-NEXT: ld a2, %lo(.LCPI13_5)(a2)
527 ; RV64I-NEXT: slli a3, a0, 4
528 ; RV64I-NEXT: and a1, a3, a1
529 ; RV64I-NEXT: srli a3, a0, 4
530 ; RV64I-NEXT: and a2, a3, a2
531 ; RV64I-NEXT: or a0, a2, a0
532 ; RV64I-NEXT: or a0, a0, a1
533 ; RV64I-NEXT: ret
534 ;
535 ; RV64ZBP-LABEL: gorc7_i64:
536 ; RV64ZBP: # %bb.0:
537 ; RV64ZBP-NEXT: orc.b a0, a0
538 ; RV64ZBP-NEXT: ret
539 %and1 = shl i64 %a, 1
540 %shl1 = and i64 %and1, -6148914691236517206
541 %and1b = lshr i64 %a, 1
542 %shr1 = and i64 %and1b, 6148914691236517205
543 %or1 = or i64 %shr1, %a
544 %or1b = or i64 %or1, %shl1
545 %and2 = shl i64 %or1b, 2
546 %shl2 = and i64 %and2, -3689348814741910324
547 %and2b = lshr i64 %or1b, 2
548 %shr2 = and i64 %and2b, 3689348814741910323
549 %or2 = or i64 %shr2, %or1b
550 %or2b = or i64 %or2, %shl2
551 %and3 = shl i64 %or2b, 4
552 %shl3 = and i64 %and3, -1085102592571150096
553 %and3b = lshr i64 %or2b, 4
554 %shr3 = and i64 %and3b, 1085102592571150095
555 %or3 = or i64 %shr3, %or2b
556 %or3b = or i64 %or3, %shl3
557 ret i64 %or3b
558 }
560 define signext i32 @gorc8_i32(i32 signext %a) nounwind {
561 ; RV64I-LABEL: gorc8_i32:
562 ; RV64I: # %bb.0:
563 ; RV64I-NEXT: slliw a1, a0, 8
564 ; RV64I-NEXT: lui a2, 1044496
565 ; RV64I-NEXT: addiw a2, a2, -256
566 ; RV64I-NEXT: and a1, a1, a2
567 ; RV64I-NEXT: srli a2, a0, 8
568 ; RV64I-NEXT: lui a3, 4080
569 ; RV64I-NEXT: addiw a3, a3, 255
570 ; RV64I-NEXT: and a2, a2, a3
571 ; RV64I-NEXT: or a0, a2, a0
572 ; RV64I-NEXT: or a0, a0, a1
573 ; RV64I-NEXT: ret
574 ;
575 ; RV64ZBP-LABEL: gorc8_i32:
576 ; RV64ZBP: # %bb.0:
577 ; RV64ZBP-NEXT: gorciw a0, a0, 8
578 ; RV64ZBP-NEXT: ret
579 %and = shl i32 %a, 8
580 %shl = and i32 %and, -16711936
581 %and1 = lshr i32 %a, 8
582 %shr = and i32 %and1, 16711935
583 %or = or i32 %shr, %a
584 %or2 = or i32 %or, %shl
585 ret i32 %or2
586 }
588 define i64 @gorc8_i64(i64 %a) nounwind {
589 ; RV64I-LABEL: gorc8_i64:
590 ; RV64I: # %bb.0:
591 ; RV64I-NEXT: lui a1, %hi(.LCPI15_0)
592 ; RV64I-NEXT: ld a1, %lo(.LCPI15_0)(a1)
593 ; RV64I-NEXT: lui a2, %hi(.LCPI15_1)
594 ; RV64I-NEXT: ld a2, %lo(.LCPI15_1)(a2)
595 ; RV64I-NEXT: slli a3, a0, 8
596 ; RV64I-NEXT: and a1, a3, a1
597 ; RV64I-NEXT: srli a3, a0, 8
598 ; RV64I-NEXT: and a2, a3, a2
599 ; RV64I-NEXT: or a0, a2, a0
600 ; RV64I-NEXT: or a0, a0, a1
601 ; RV64I-NEXT: ret
602 ;
603 ; RV64ZBP-LABEL: gorc8_i64:
604 ; RV64ZBP: # %bb.0:
605 ; RV64ZBP-NEXT: orc8.h a0, a0
606 ; RV64ZBP-NEXT: ret
607 %and = shl i64 %a, 8
608 %shl = and i64 %and, -71777214294589696
609 %and1 = lshr i64 %a, 8
610 %shr = and i64 %and1, 71777214294589695
611 %or = or i64 %shr, %a
612 %or2 = or i64 %or, %shl
613 ret i64 %or2
614 }
616 define signext i32 @gorc12_i32(i32 signext %a) nounwind {
617 ; RV64I-LABEL: gorc12_i32:
618 ; RV64I: # %bb.0:
619 ; RV64I-NEXT: slliw a1, a0, 4
620 ; RV64I-NEXT: lui a2, 986895
621 ; RV64I-NEXT: addiw a2, a2, 240
622 ; RV64I-NEXT: and a1, a1, a2
623 ; RV64I-NEXT: srli a2, a0, 4
624 ; RV64I-NEXT: lui a3, 61681
625 ; RV64I-NEXT: addiw a3, a3, -241
626 ; RV64I-NEXT: and a2, a2, a3
627 ; RV64I-NEXT: or a0, a2, a0
628 ; RV64I-NEXT: or a0, a0, a1
629 ; RV64I-NEXT: slliw a1, a0, 8
630 ; RV64I-NEXT: lui a2, 1044496
631 ; RV64I-NEXT: addiw a2, a2, -256
632 ; RV64I-NEXT: and a1, a1, a2
633 ; RV64I-NEXT: srli a2, a0, 8
634 ; RV64I-NEXT: lui a3, 4080
635 ; RV64I-NEXT: addiw a3, a3, 255
636 ; RV64I-NEXT: and a2, a2, a3
637 ; RV64I-NEXT: or a0, a2, a0
638 ; RV64I-NEXT: or a0, a0, a1
639 ; RV64I-NEXT: ret
640 ;
641 ; RV64ZBP-LABEL: gorc12_i32:
642 ; RV64ZBP: # %bb.0:
643 ; RV64ZBP-NEXT: gorciw a0, a0, 12
644 ; RV64ZBP-NEXT: ret
645 %and1 = shl i32 %a, 4
646 %shl1 = and i32 %and1, -252645136
647 %and1b = lshr i32 %a, 4
648 %shr1 = and i32 %and1b, 252645135
649 %or1 = or i32 %shr1, %a
650 %or1b = or i32 %or1, %shl1
651 %and2 = shl i32 %or1b, 8
652 %shl2 = and i32 %and2, -16711936
653 %and2b = lshr i32 %or1b, 8
654 %shr2 = and i32 %and2b, 16711935
655 %or2 = or i32 %shr2, %or1b
656 %or2b = or i32 %or2, %shl2
657 ret i32 %or2b
658 }
660 define i64 @gorc12_i64(i64 %a) nounwind {
661 ; RV64I-LABEL: gorc12_i64:
662 ; RV64I: # %bb.0:
663 ; RV64I-NEXT: lui a1, %hi(.LCPI17_0)
664 ; RV64I-NEXT: ld a1, %lo(.LCPI17_0)(a1)
665 ; RV64I-NEXT: lui a2, %hi(.LCPI17_1)
666 ; RV64I-NEXT: ld a2, %lo(.LCPI17_1)(a2)
667 ; RV64I-NEXT: slli a3, a0, 4
668 ; RV64I-NEXT: and a1, a3, a1
669 ; RV64I-NEXT: srli a3, a0, 4
670 ; RV64I-NEXT: and a2, a3, a2
671 ; RV64I-NEXT: or a0, a2, a0
672 ; RV64I-NEXT: or a0, a0, a1
673 ; RV64I-NEXT: lui a1, %hi(.LCPI17_2)
674 ; RV64I-NEXT: ld a1, %lo(.LCPI17_2)(a1)
675 ; RV64I-NEXT: lui a2, %hi(.LCPI17_3)
676 ; RV64I-NEXT: ld a2, %lo(.LCPI17_3)(a2)
677 ; RV64I-NEXT: slli a3, a0, 8
678 ; RV64I-NEXT: and a1, a3, a1
679 ; RV64I-NEXT: srli a3, a0, 8
680 ; RV64I-NEXT: and a2, a3, a2
681 ; RV64I-NEXT: or a0, a2, a0
682 ; RV64I-NEXT: or a0, a0, a1
683 ; RV64I-NEXT: ret
684 ;
685 ; RV64ZBP-LABEL: gorc12_i64:
686 ; RV64ZBP: # %bb.0:
687 ; RV64ZBP-NEXT: orc4.h a0, a0
688 ; RV64ZBP-NEXT: ret
689 %and1 = shl i64 %a, 4
690 %shl1 = and i64 %and1, -1085102592571150096
691 %and1b = lshr i64 %a, 4
692 %shr1 = and i64 %and1b, 1085102592571150095
693 %or1 = or i64 %shr1, %a
694 %or1b = or i64 %or1, %shl1
695 %and2 = shl i64 %or1b, 8
696 %shl2 = and i64 %and2, -71777214294589696
697 %and2b = lshr i64 %or1b, 8
698 %shr2 = and i64 %and2b, 71777214294589695
699 %or2 = or i64 %shr2, %or1b
700 %or2b = or i64 %or2, %shl2
701 ret i64 %or2b
702 }
704 define signext i32 @gorc14_i32(i32 signext %a) nounwind {
705 ; RV64I-LABEL: gorc14_i32:
706 ; RV64I: # %bb.0:
707 ; RV64I-NEXT: slliw a1, a0, 2
708 ; RV64I-NEXT: lui a2, 838861
709 ; RV64I-NEXT: addiw a2, a2, -820
710 ; RV64I-NEXT: and a1, a1, a2
711 ; RV64I-NEXT: srli a2, a0, 2
712 ; RV64I-NEXT: lui a3, 209715
713 ; RV64I-NEXT: addiw a3, a3, 819
714 ; RV64I-NEXT: and a2, a2, a3
715 ; RV64I-NEXT: or a0, a2, a0
716 ; RV64I-NEXT: or a0, a0, a1
717 ; RV64I-NEXT: slliw a1, a0, 4
718 ; RV64I-NEXT: lui a2, 986895
719 ; RV64I-NEXT: addiw a2, a2, 240
720 ; RV64I-NEXT: and a1, a1, a2
721 ; RV64I-NEXT: srli a2, a0, 4
722 ; RV64I-NEXT: lui a3, 61681
723 ; RV64I-NEXT: addiw a3, a3, -241
724 ; RV64I-NEXT: and a2, a2, a3
725 ; RV64I-NEXT: or a0, a2, a0
726 ; RV64I-NEXT: or a0, a0, a1
727 ; RV64I-NEXT: slli a1, a0, 8
728 ; RV64I-NEXT: lui a2, 1044496
729 ; RV64I-NEXT: addiw a2, a2, -256
730 ; RV64I-NEXT: and a1, a1, a2
731 ; RV64I-NEXT: srli a2, a0, 8
732 ; RV64I-NEXT: lui a3, 4080
733 ; RV64I-NEXT: addiw a3, a3, 255
734 ; RV64I-NEXT: and a2, a2, a3
735 ; RV64I-NEXT: or a0, a2, a0
736 ; RV64I-NEXT: or a0, a0, a1
737 ; RV64I-NEXT: sext.w a0, a0
738 ; RV64I-NEXT: ret
739 ;
740 ; RV64ZBP-LABEL: gorc14_i32:
741 ; RV64ZBP: # %bb.0:
742 ; RV64ZBP-NEXT: gorciw a0, a0, 14
743 ; RV64ZBP-NEXT: ret
744 %and1 = shl i32 %a, 2
745 %shl1 = and i32 %and1, -858993460
746 %and1b = lshr i32 %a, 2
747 %shr1 = and i32 %and1b, 858993459
748 %or1 = or i32 %shr1, %a
749 %or1b = or i32 %or1, %shl1
750 %and2 = shl i32 %or1b, 4
751 %shl2 = and i32 %and2, -252645136
752 %and2b = lshr i32 %or1b, 4
753 %shr2 = and i32 %and2b, 252645135
754 %or2 = or i32 %shr2, %or1b
755 %or2b = or i32 %or2, %shl2
756 %and3 = shl i32 %or2b, 8
757 %shl3 = and i32 %and3, -16711936
758 %and3b = lshr i32 %or2b, 8
759 %shr3 = and i32 %and3b, 16711935
760 %or3 = or i32 %shr3, %or2b
761 %or3b = or i32 %or3, %shl3
762 ret i32 %or3b
763 }
765 define i64 @gorc14_i64(i64 %a) nounwind {
766 ; RV64I-LABEL: gorc14_i64:
767 ; RV64I: # %bb.0:
768 ; RV64I-NEXT: lui a1, %hi(.LCPI19_0)
769 ; RV64I-NEXT: ld a1, %lo(.LCPI19_0)(a1)
770 ; RV64I-NEXT: lui a2, %hi(.LCPI19_1)
771 ; RV64I-NEXT: ld a2, %lo(.LCPI19_1)(a2)
772 ; RV64I-NEXT: slli a3, a0, 2
773 ; RV64I-NEXT: and a1, a3, a1
774 ; RV64I-NEXT: srli a3, a0, 2
775 ; RV64I-NEXT: and a2, a3, a2
776 ; RV64I-NEXT: or a0, a2, a0
777 ; RV64I-NEXT: or a0, a0, a1
778 ; RV64I-NEXT: lui a1, %hi(.LCPI19_2)
779 ; RV64I-NEXT: ld a1, %lo(.LCPI19_2)(a1)
780 ; RV64I-NEXT: lui a2, %hi(.LCPI19_3)
781 ; RV64I-NEXT: ld a2, %lo(.LCPI19_3)(a2)
782 ; RV64I-NEXT: slli a3, a0, 4
783 ; RV64I-NEXT: and a1, a3, a1
784 ; RV64I-NEXT: srli a3, a0, 4
785 ; RV64I-NEXT: and a2, a3, a2
786 ; RV64I-NEXT: or a0, a2, a0
787 ; RV64I-NEXT: or a0, a0, a1
788 ; RV64I-NEXT: lui a1, %hi(.LCPI19_4)
789 ; RV64I-NEXT: ld a1, %lo(.LCPI19_4)(a1)
790 ; RV64I-NEXT: lui a2, %hi(.LCPI19_5)
791 ; RV64I-NEXT: ld a2, %lo(.LCPI19_5)(a2)
792 ; RV64I-NEXT: slli a3, a0, 8
793 ; RV64I-NEXT: and a1, a3, a1
794 ; RV64I-NEXT: srli a3, a0, 8
795 ; RV64I-NEXT: and a2, a3, a2
796 ; RV64I-NEXT: or a0, a2, a0
797 ; RV64I-NEXT: or a0, a0, a1
798 ; RV64I-NEXT: ret
799 ;
800 ; RV64ZBP-LABEL: gorc14_i64:
801 ; RV64ZBP: # %bb.0:
802 ; RV64ZBP-NEXT: orc2.h a0, a0
803 ; RV64ZBP-NEXT: ret
804 %and1 = shl i64 %a, 2
805 %shl1 = and i64 %and1, -3689348814741910324
806 %and1b = lshr i64 %a, 2
807 %shr1 = and i64 %and1b, 3689348814741910323
808 %or1 = or i64 %shr1, %a
809 %or1b = or i64 %or1, %shl1
810 %and2 = shl i64 %or1b, 4
811 %shl2 = and i64 %and2, -1085102592571150096
812 %and2b = lshr i64 %or1b, 4
813 %shr2 = and i64 %and2b, 1085102592571150095
814 %or2 = or i64 %shr2, %or1b
815 %or2b = or i64 %or2, %shl2
816 %and3 = shl i64 %or2b, 8
817 %shl3 = and i64 %and3, -71777214294589696
818 %and3b = lshr i64 %or2b, 8
819 %shr3 = and i64 %and3b, 71777214294589695
820 %or3 = or i64 %shr3, %or2b
821 %or3b = or i64 %or3, %shl3
822 ret i64 %or3b
823 }
825 define signext i32 @gorc16_i32(i32 signext %a) nounwind {
826 ; RV64I-LABEL: gorc16_i32:
827 ; RV64I: # %bb.0:
828 ; RV64I-NEXT: slliw a1, a0, 16
829 ; RV64I-NEXT: srliw a2, a0, 16
830 ; RV64I-NEXT: or a0, a2, a0
831 ; RV64I-NEXT: or a0, a0, a1
832 ; RV64I-NEXT: ret
833 ;
834 ; RV64ZBP-LABEL: gorc16_i32:
835 ; RV64ZBP: # %bb.0:
836 ; RV64ZBP-NEXT: gorciw a0, a0, 16
837 ; RV64ZBP-NEXT: ret
838 %shl = shl i32 %a, 16
839 %shr = lshr i32 %a, 16
840 %or = or i32 %shr, %a
841 %or2 = or i32 %or, %shl
842 ret i32 %or2
843 }
845 define i32 @gorc16_rotl_i32(i32 %a) nounwind {
846 ; RV64I-LABEL: gorc16_rotl_i32:
847 ; RV64I: # %bb.0:
848 ; RV64I-NEXT: srliw a1, a0, 16
849 ; RV64I-NEXT: slliw a2, a0, 16
850 ; RV64I-NEXT: or a1, a2, a1
851 ; RV64I-NEXT: or a0, a1, a0
852 ; RV64I-NEXT: ret
853 ;
854 ; RV64ZBP-LABEL: gorc16_rotl_i32:
855 ; RV64ZBP: # %bb.0:
856 ; RV64ZBP-NEXT: orc16.w a0, a0
857 ; RV64ZBP-NEXT: ret
858 %rot = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 16)
859 %or = or i32 %rot, %a
860 ret i32 %or
861 }
863 define i32 @gorc16_rotr_i32(i32 %a) nounwind {
864 ; RV64I-LABEL: gorc16_rotr_i32:
865 ; RV64I: # %bb.0:
866 ; RV64I-NEXT: slliw a1, a0, 16
867 ; RV64I-NEXT: srliw a2, a0, 16
868 ; RV64I-NEXT: or a1, a2, a1
869 ; RV64I-NEXT: or a0, a1, a0
870 ; RV64I-NEXT: ret
871 ;
872 ; RV64ZBP-LABEL: gorc16_rotr_i32:
873 ; RV64ZBP: # %bb.0:
874 ; RV64ZBP-NEXT: orc16.w a0, a0
875 ; RV64ZBP-NEXT: ret
876 %rot = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 16)
877 %or = or i32 %rot, %a
878 ret i32 %or
879 }
881 define i64 @gorc16_i64(i64 %a) nounwind {
882 ; RV64I-LABEL: gorc16_i64:
883 ; RV64I: # %bb.0:
884 ; RV64I-NEXT: slli a1, a0, 16
885 ; RV64I-NEXT: lui a2, 983041
886 ; RV64I-NEXT: slli a3, a2, 4
887 ; RV64I-NEXT: addi a3, a3, -1
888 ; RV64I-NEXT: slli a3, a3, 16
889 ; RV64I-NEXT: and a1, a1, a3
890 ; RV64I-NEXT: srli a3, a0, 16
891 ; RV64I-NEXT: slli a2, a2, 20
892 ; RV64I-NEXT: addi a2, a2, -1
893 ; RV64I-NEXT: srli a2, a2, 16
894 ; RV64I-NEXT: and a2, a3, a2
895 ; RV64I-NEXT: or a0, a2, a0
896 ; RV64I-NEXT: or a0, a0, a1
897 ; RV64I-NEXT: ret
898 ;
899 ; RV64ZBP-LABEL: gorc16_i64:
900 ; RV64ZBP: # %bb.0:
901 ; RV64ZBP-NEXT: orc16.w a0, a0
902 ; RV64ZBP-NEXT: ret
903 %and = shl i64 %a, 16
904 %shl = and i64 %and, -281470681808896
905 %and1 = lshr i64 %a, 16
906 %shr = and i64 %and1, 281470681808895
907 %or = or i64 %shr, %a
908 %or2 = or i64 %or, %shl
909 ret i64 %or2
910 }
912 define i64 @gorc32(i64 %a) nounwind {
913 ; RV64I-LABEL: gorc32:
914 ; RV64I: # %bb.0:
915 ; RV64I-NEXT: slli a1, a0, 32
916 ; RV64I-NEXT: srli a2, a0, 32
917 ; RV64I-NEXT: or a0, a2, a0
918 ; RV64I-NEXT: or a0, a0, a1
919 ; RV64I-NEXT: ret
920 ;
921 ; RV64ZBP-LABEL: gorc32:
922 ; RV64ZBP: # %bb.0:
923 ; RV64ZBP-NEXT: orc32 a0, a0
924 ; RV64ZBP-NEXT: ret
925 %shl = shl i64 %a, 32
926 %shr = lshr i64 %a, 32
927 %or = or i64 %shr, %a
928 %or2 = or i64 %or, %shl
929 ret i64 %or2
930 }
932 ; gorc2, gorc2 -> gorc2
933 define signext i32 @gorc2b_i32(i32 signext %a) nounwind {
934 ; RV64I-LABEL: gorc2b_i32:
935 ; RV64I: # %bb.0:
936 ; RV64I-NEXT: slliw a1, a0, 2
937 ; RV64I-NEXT: lui a2, 838861
938 ; RV64I-NEXT: addiw a2, a2, -820
939 ; RV64I-NEXT: and a1, a1, a2
940 ; RV64I-NEXT: srli a3, a0, 2
941 ; RV64I-NEXT: lui a4, 209715
942 ; RV64I-NEXT: addiw a4, a4, 819
943 ; RV64I-NEXT: and a3, a3, a4
944 ; RV64I-NEXT: or a0, a3, a0
945 ; RV64I-NEXT: or a1, a0, a1
946 ; RV64I-NEXT: slliw a0, a0, 2
947 ; RV64I-NEXT: and a0, a0, a2
948 ; RV64I-NEXT: srli a2, a1, 2
949 ; RV64I-NEXT: and a2, a2, a4
950 ; RV64I-NEXT: or a1, a2, a1
951 ; RV64I-NEXT: or a0, a1, a0
952 ; RV64I-NEXT: ret
953 ;
954 ; RV64ZBP-LABEL: gorc2b_i32:
955 ; RV64ZBP: # %bb.0:
956 ; RV64ZBP-NEXT: srliw a1, a0, 2
957 ; RV64ZBP-NEXT: or a1, a1, a0
958 ; RV64ZBP-NEXT: orc2.n a0, a0
959 ; RV64ZBP-NEXT: slli a1, a1, 2
960 ; RV64ZBP-NEXT: lui a2, 838861
961 ; RV64ZBP-NEXT: addiw a2, a2, -820
962 ; RV64ZBP-NEXT: and a1, a1, a2
963 ; RV64ZBP-NEXT: srli a2, a0, 2
964 ; RV64ZBP-NEXT: lui a3, 209715
965 ; RV64ZBP-NEXT: addiw a3, a3, 819
966 ; RV64ZBP-NEXT: and a2, a2, a3
967 ; RV64ZBP-NEXT: or a0, a2, a0
968 ; RV64ZBP-NEXT: or a0, a0, a1
969 ; RV64ZBP-NEXT: sext.w a0, a0
970 ; RV64ZBP-NEXT: ret
971 %and1 = shl i32 %a, 2
972 %shl1 = and i32 %and1, -858993460
973 %and1b = lshr i32 %a, 2
974 %shr1 = and i32 %and1b, 858993459
975 %or1 = or i32 %shr1, %a
976 %or1b = or i32 %or1, %shl1
977 %and2 = shl i32 %or1b, 2
978 %shl2 = and i32 %and2, -858993460
979 %and2b = lshr i32 %or1b, 2
980 %shr2 = and i32 %and2b, 858993459
981 %or2 = or i32 %shr2, %or1b
982 %or2b = or i32 %or2, %shl2
983 ret i32 %or2b
984 }
986 ; gorc2, gorc2 -> gorc2
987 define i64 @gorc2b_i64(i64 %a) nounwind {
988 ; RV64I-LABEL: gorc2b_i64:
989 ; RV64I: # %bb.0:
990 ; RV64I-NEXT: lui a1, %hi(.LCPI26_0)
991 ; RV64I-NEXT: ld a1, %lo(.LCPI26_0)(a1)
992 ; RV64I-NEXT: lui a2, %hi(.LCPI26_1)
993 ; RV64I-NEXT: ld a2, %lo(.LCPI26_1)(a2)
994 ; RV64I-NEXT: slli a3, a0, 2
995 ; RV64I-NEXT: and a3, a3, a1
996 ; RV64I-NEXT: srli a4, a0, 2
997 ; RV64I-NEXT: and a4, a4, a2
998 ; RV64I-NEXT: or a0, a4, a0
999 ; RV64I-NEXT: or a3, a0, a3
1000 ; RV64I-NEXT: slli a0, a0, 2
1001 ; RV64I-NEXT: and a0, a0, a1
1002 ; RV64I-NEXT: srli a1, a3, 2
1003 ; RV64I-NEXT: and a1, a1, a2
1004 ; RV64I-NEXT: or a1, a1, a3
1005 ; RV64I-NEXT: or a0, a1, a0
1006 ; RV64I-NEXT: ret
1007 ;
1008 ; RV64ZBP-LABEL: gorc2b_i64:
1009 ; RV64ZBP: # %bb.0:
1010 ; RV64ZBP-NEXT: srli a1, a0, 2
1011 ; RV64ZBP-NEXT: or a1, a1, a0
1012 ; RV64ZBP-NEXT: orc2.n a0, a0
1013 ; RV64ZBP-NEXT: lui a2, %hi(.LCPI26_0)
1014 ; RV64ZBP-NEXT: ld a2, %lo(.LCPI26_0)(a2)
1015 ; RV64ZBP-NEXT: lui a3, %hi(.LCPI26_1)
1016 ; RV64ZBP-NEXT: ld a3, %lo(.LCPI26_1)(a3)
1017 ; RV64ZBP-NEXT: slli a1, a1, 2
1018 ; RV64ZBP-NEXT: and a1, a1, a2
1019 ; RV64ZBP-NEXT: srli a2, a0, 2
1020 ; RV64ZBP-NEXT: and a2, a2, a3
1021 ; RV64ZBP-NEXT: or a0, a2, a0
1022 ; RV64ZBP-NEXT: or a0, a0, a1
1023 ; RV64ZBP-NEXT: ret
1024 %and1 = shl i64 %a, 2
1025 %shl1 = and i64 %and1, -3689348814741910324
1026 %and1b = lshr i64 %a, 2
1027 %shr1 = and i64 %and1b, 3689348814741910323
1028 %or1 = or i64 %shr1, %a
1029 %or1b = or i64 %or1, %shl1
1030 %and2 = shl i64 %or1b, 2
1031 %shl2 = and i64 %and2, -3689348814741910324
1032 %and2b = lshr i64 %or1b, 2
1033 %shr2 = and i64 %and2b, 3689348814741910323
1034 %or2 = or i64 %shr2, %or1b
1035 %or2b = or i64 %or2, %shl2
1036 ret i64 %or2b
1037 }
1039 ; gorc1, gorc2, gorc1 -> gorc2
1040 define signext i32 @gorc3b_i32(i32 signext %a) nounwind {
1041 ; RV64I-LABEL: gorc3b_i32:
1042 ; RV64I: # %bb.0:
1043 ; RV64I-NEXT: slliw a1, a0, 1
1044 ; RV64I-NEXT: lui a2, 699051
1045 ; RV64I-NEXT: addiw a2, a2, -1366
1046 ; RV64I-NEXT: and a1, a1, a2
1047 ; RV64I-NEXT: srli a3, a0, 1
1048 ; RV64I-NEXT: lui a4, 349525
1049 ; RV64I-NEXT: addiw a4, a4, 1365
1050 ; RV64I-NEXT: and a3, a3, a4
1051 ; RV64I-NEXT: or a0, a3, a0
1052 ; RV64I-NEXT: or a0, a0, a1
1053 ; RV64I-NEXT: slliw a1, a0, 2
1054 ; RV64I-NEXT: lui a3, 838861
1055 ; RV64I-NEXT: addiw a3, a3, -820
1056 ; RV64I-NEXT: and a1, a1, a3
1057 ; RV64I-NEXT: srli a3, a0, 2
1058 ; RV64I-NEXT: lui a5, 209715
1059 ; RV64I-NEXT: addiw a5, a5, 819
1060 ; RV64I-NEXT: and a3, a3, a5
1061 ; RV64I-NEXT: or a0, a3, a0
1062 ; RV64I-NEXT: or a0, a0, a1
1063 ; RV64I-NEXT: slli a1, a0, 1
1064 ; RV64I-NEXT: and a1, a1, a2
1065 ; RV64I-NEXT: srli a2, a0, 1
1066 ; RV64I-NEXT: and a2, a2, a4
1067 ; RV64I-NEXT: or a0, a2, a0
1068 ; RV64I-NEXT: or a0, a0, a1
1069 ; RV64I-NEXT: sext.w a0, a0
1070 ; RV64I-NEXT: ret
1071 ;
1072 ; RV64ZBP-LABEL: gorc3b_i32:
1073 ; RV64ZBP: # %bb.0:
1074 ; RV64ZBP-NEXT: gorciw a0, a0, 3
1075 ; RV64ZBP-NEXT: ret
1076 %and1 = shl i32 %a, 1
1077 %shl1 = and i32 %and1, -1431655766
1078 %and1b = lshr i32 %a, 1
1079 %shr1 = and i32 %and1b, 1431655765
1080 %or1 = or i32 %shr1, %a
1081 %or1b = or i32 %or1, %shl1
1082 %and2 = shl i32 %or1b, 2
1083 %shl2 = and i32 %and2, -858993460
1084 %and2b = lshr i32 %or1b, 2
1085 %shr2 = and i32 %and2b, 858993459
1086 %or2 = or i32 %shr2, %or1b
1087 %or2b = or i32 %or2, %shl2
1088 %and3 = shl i32 %or2b, 1
1089 %shl3 = and i32 %and3, -1431655766
1090 %and3b = lshr i32 %or2b, 1
1091 %shr3 = and i32 %and3b, 1431655765
1092 %or3 = or i32 %shr3, %or2b
1093 %or3b = or i32 %or3, %shl3
1094 ret i32 %or3b
1095 }
1097 ; gorc1, gorc2, gorc1 -> gorc2
1098 define i64 @gorc3b_i64(i64 %a) nounwind {
1099 ; RV64I-LABEL: gorc3b_i64:
1100 ; RV64I: # %bb.0:
1101 ; RV64I-NEXT: lui a1, %hi(.LCPI28_0)
1102 ; RV64I-NEXT: ld a1, %lo(.LCPI28_0)(a1)
1103 ; RV64I-NEXT: lui a2, %hi(.LCPI28_1)
1104 ; RV64I-NEXT: ld a2, %lo(.LCPI28_1)(a2)
1105 ; RV64I-NEXT: slli a3, a0, 1
1106 ; RV64I-NEXT: and a3, a3, a1
1107 ; RV64I-NEXT: srli a4, a0, 1
1108 ; RV64I-NEXT: and a4, a4, a2
1109 ; RV64I-NEXT: or a0, a4, a0
1110 ; RV64I-NEXT: or a0, a0, a3
1111 ; RV64I-NEXT: lui a3, %hi(.LCPI28_2)
1112 ; RV64I-NEXT: ld a3, %lo(.LCPI28_2)(a3)
1113 ; RV64I-NEXT: lui a4, %hi(.LCPI28_3)
1114 ; RV64I-NEXT: ld a4, %lo(.LCPI28_3)(a4)
1115 ; RV64I-NEXT: slli a5, a0, 2
1116 ; RV64I-NEXT: and a3, a5, a3
1117 ; RV64I-NEXT: srli a5, a0, 2
1118 ; RV64I-NEXT: and a4, a5, a4
1119 ; RV64I-NEXT: or a0, a4, a0
1120 ; RV64I-NEXT: or a0, a0, a3
1121 ; RV64I-NEXT: slli a3, a0, 1
1122 ; RV64I-NEXT: and a1, a3, a1
1123 ; RV64I-NEXT: srli a3, a0, 1
1124 ; RV64I-NEXT: and a2, a3, a2
1125 ; RV64I-NEXT: or a0, a2, a0
1126 ; RV64I-NEXT: or a0, a0, a1
1127 ; RV64I-NEXT: ret
1128 ;
1129 ; RV64ZBP-LABEL: gorc3b_i64:
1130 ; RV64ZBP: # %bb.0:
1131 ; RV64ZBP-NEXT: orc.n a0, a0
1132 ; RV64ZBP-NEXT: ret
1133 %and1 = shl i64 %a, 1
1134 %shl1 = and i64 %and1, -6148914691236517206
1135 %and1b = lshr i64 %a, 1
1136 %shr1 = and i64 %and1b, 6148914691236517205
1137 %or1 = or i64 %shr1, %a
1138 %or1b = or i64 %or1, %shl1
1139 %and2 = shl i64 %or1b, 2
1140 %shl2 = and i64 %and2, -3689348814741910324
1141 %and2b = lshr i64 %or1b, 2
1142 %shr2 = and i64 %and2b, 3689348814741910323
1143 %or2 = or i64 %shr2, %or1b
1144 %or2b = or i64 %or2, %shl2
1145 %and3 = shl i64 %or2b, 1
1146 %shl3 = and i64 %and3, -6148914691236517206
1147 %and3b = lshr i64 %or2b, 1
1148 %shr3 = and i64 %and3b, 6148914691236517205
1149 %or3 = or i64 %shr3, %or2b
1150 %or3b = or i64 %or3, %shl3
1151 ret i64 %or3b
1152 }
1154 define i64 @gorc32_rotl(i64 %a) nounwind {
1155 ; RV64I-LABEL: gorc32_rotl:
1156 ; RV64I: # %bb.0:
1157 ; RV64I-NEXT: srli a1, a0, 32
1158 ; RV64I-NEXT: slli a2, a0, 32
1159 ; RV64I-NEXT: or a1, a2, a1
1160 ; RV64I-NEXT: or a0, a1, a0
1161 ; RV64I-NEXT: ret
1162 ;
1163 ; RV64ZBP-LABEL: gorc32_rotl:
1164 ; RV64ZBP: # %bb.0:
1165 ; RV64ZBP-NEXT: orc32 a0, a0
1166 ; RV64ZBP-NEXT: ret
1167 %rot = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 32)
1168 %or = or i64 %rot, %a
1169 ret i64 %or
1170 }
1172 define i64 @gorc32_rotr(i64 %a) nounwind {
1173 ; RV64I-LABEL: gorc32_rotr:
1174 ; RV64I: # %bb.0:
1175 ; RV64I-NEXT: slli a1, a0, 32
1176 ; RV64I-NEXT: srli a2, a0, 32
1177 ; RV64I-NEXT: or a1, a2, a1
1178 ; RV64I-NEXT: or a0, a1, a0
1179 ; RV64I-NEXT: ret
1180 ;
1181 ; RV64ZBP-LABEL: gorc32_rotr:
1182 ; RV64ZBP: # %bb.0:
1183 ; RV64ZBP-NEXT: orc32 a0, a0
1184 ; RV64ZBP-NEXT: ret
1185 %rot = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 32)
1186 %or = or i64 %rot, %a
1187 ret i64 %or
1188 }
1190 define signext i32 @grev1_i32(i32 signext %a) nounwind {
1191 ; RV64I-LABEL: grev1_i32:
1192 ; RV64I: # %bb.0:
1193 ; RV64I-NEXT: slliw a1, a0, 1
1194 ; RV64I-NEXT: lui a2, 699051
1195 ; RV64I-NEXT: addiw a2, a2, -1366
1196 ; RV64I-NEXT: and a1, a1, a2
1197 ; RV64I-NEXT: srli a0, a0, 1
1198 ; RV64I-NEXT: lui a2, 349525
1199 ; RV64I-NEXT: addiw a2, a2, 1365
1200 ; RV64I-NEXT: and a0, a0, a2
1201 ; RV64I-NEXT: or a0, a1, a0
1202 ; RV64I-NEXT: ret
1203 ;
1204 ; RV64ZBP-LABEL: grev1_i32:
1205 ; RV64ZBP: # %bb.0:
1206 ; RV64ZBP-NEXT: greviw a0, a0, 1
1207 ; RV64ZBP-NEXT: ret
1208 %and = shl i32 %a, 1
1209 %shl = and i32 %and, -1431655766
1210 %and1 = lshr i32 %a, 1
1211 %shr = and i32 %and1, 1431655765
1212 %or = or i32 %shl, %shr
1213 ret i32 %or
1214 }
1216 define i64 @grev1_i64(i64 %a) nounwind {
1217 ; RV64I-LABEL: grev1_i64:
1218 ; RV64I: # %bb.0:
1219 ; RV64I-NEXT: lui a1, %hi(.LCPI32_0)
1220 ; RV64I-NEXT: ld a1, %lo(.LCPI32_0)(a1)
1221 ; RV64I-NEXT: lui a2, %hi(.LCPI32_1)
1222 ; RV64I-NEXT: ld a2, %lo(.LCPI32_1)(a2)
1223 ; RV64I-NEXT: slli a3, a0, 1
1224 ; RV64I-NEXT: and a1, a3, a1
1225 ; RV64I-NEXT: srli a0, a0, 1
1226 ; RV64I-NEXT: and a0, a0, a2
1227 ; RV64I-NEXT: or a0, a1, a0
1228 ; RV64I-NEXT: ret
1229 ;
1230 ; RV64ZBP-LABEL: grev1_i64:
1231 ; RV64ZBP: # %bb.0:
1232 ; RV64ZBP-NEXT: rev.p a0, a0
1233 ; RV64ZBP-NEXT: ret
1234 %and = shl i64 %a, 1
1235 %shl = and i64 %and, -6148914691236517206
1236 %and1 = lshr i64 %a, 1
1237 %shr = and i64 %and1, 6148914691236517205
1238 %or = or i64 %shl, %shr
1239 ret i64 %or
1240 }
1242 define signext i32 @grev2_i32(i32 signext %a) nounwind {
1243 ; RV64I-LABEL: grev2_i32:
1244 ; RV64I: # %bb.0:
1245 ; RV64I-NEXT: slliw a1, a0, 2
1246 ; RV64I-NEXT: lui a2, 838861
1247 ; RV64I-NEXT: addiw a2, a2, -820
1248 ; RV64I-NEXT: and a1, a1, a2
1249 ; RV64I-NEXT: srli a0, a0, 2
1250 ; RV64I-NEXT: lui a2, 209715
1251 ; RV64I-NEXT: addiw a2, a2, 819
1252 ; RV64I-NEXT: and a0, a0, a2
1253 ; RV64I-NEXT: or a0, a1, a0
1254 ; RV64I-NEXT: ret
1255 ;
1256 ; RV64ZBP-LABEL: grev2_i32:
1257 ; RV64ZBP: # %bb.0:
1258 ; RV64ZBP-NEXT: greviw a0, a0, 2
1259 ; RV64ZBP-NEXT: ret
1260 %and = shl i32 %a, 2
1261 %shl = and i32 %and, -858993460
1262 %and1 = lshr i32 %a, 2
1263 %shr = and i32 %and1, 858993459
1264 %or = or i32 %shl, %shr
1265 ret i32 %or
1266 }
1268 define i64 @grev2_i64(i64 %a) nounwind {
1269 ; RV64I-LABEL: grev2_i64:
1270 ; RV64I: # %bb.0:
1271 ; RV64I-NEXT: lui a1, %hi(.LCPI34_0)
1272 ; RV64I-NEXT: ld a1, %lo(.LCPI34_0)(a1)
1273 ; RV64I-NEXT: lui a2, %hi(.LCPI34_1)
1274 ; RV64I-NEXT: ld a2, %lo(.LCPI34_1)(a2)
1275 ; RV64I-NEXT: slli a3, a0, 2
1276 ; RV64I-NEXT: and a1, a3, a1
1277 ; RV64I-NEXT: srli a0, a0, 2
1278 ; RV64I-NEXT: and a0, a0, a2
1279 ; RV64I-NEXT: or a0, a1, a0
1280 ; RV64I-NEXT: ret
1281 ;
1282 ; RV64ZBP-LABEL: grev2_i64:
1283 ; RV64ZBP: # %bb.0:
1284 ; RV64ZBP-NEXT: rev2.n a0, a0
1285 ; RV64ZBP-NEXT: ret
1286 %and = shl i64 %a, 2
1287 %shl = and i64 %and, -3689348814741910324
1288 %and1 = lshr i64 %a, 2
1289 %shr = and i64 %and1, 3689348814741910323
1290 %or = or i64 %shl, %shr
1291 ret i64 %or
1292 }
1294 define signext i32 @grev3_i32(i32 signext %a) nounwind {
1295 ; RV64I-LABEL: grev3_i32:
1296 ; RV64I: # %bb.0:
1297 ; RV64I-NEXT: slliw a1, a0, 1
1298 ; RV64I-NEXT: lui a2, 699051
1299 ; RV64I-NEXT: addiw a2, a2, -1366
1300 ; RV64I-NEXT: and a1, a1, a2
1301 ; RV64I-NEXT: srli a0, a0, 1
1302 ; RV64I-NEXT: lui a2, 349525
1303 ; RV64I-NEXT: addiw a2, a2, 1365
1304 ; RV64I-NEXT: and a0, a0, a2
1305 ; RV64I-NEXT: or a0, a1, a0
1306 ; RV64I-NEXT: slliw a1, a0, 2
1307 ; RV64I-NEXT: lui a2, 838861
1308 ; RV64I-NEXT: addiw a2, a2, -820
1309 ; RV64I-NEXT: and a1, a1, a2
1310 ; RV64I-NEXT: srli a0, a0, 2
1311 ; RV64I-NEXT: lui a2, 209715
1312 ; RV64I-NEXT: addiw a2, a2, 819
1313 ; RV64I-NEXT: and a0, a0, a2
1314 ; RV64I-NEXT: or a0, a1, a0
1315 ; RV64I-NEXT: ret
1316 ;
1317 ; RV64ZBP-LABEL: grev3_i32:
1318 ; RV64ZBP: # %bb.0:
1319 ; RV64ZBP-NEXT: greviw a0, a0, 3
1320 ; RV64ZBP-NEXT: ret
1321 %and1 = shl i32 %a, 1
1322 %shl1 = and i32 %and1, -1431655766
1323 %and1b = lshr i32 %a, 1
1324 %shr1 = and i32 %and1b, 1431655765
1325 %or1 = or i32 %shl1, %shr1
1326 %and2 = shl i32 %or1, 2
1327 %shl2 = and i32 %and2, -858993460
1328 %and2b = lshr i32 %or1, 2
1329 %shr2 = and i32 %and2b, 858993459
1330 %or2 = or i32 %shl2, %shr2
1331 ret i32 %or2
1332 }
1334 define i64 @grev3_i64(i64 %a) nounwind {
1335 ; RV64I-LABEL: grev3_i64:
1336 ; RV64I: # %bb.0:
1337 ; RV64I-NEXT: lui a1, %hi(.LCPI36_0)
1338 ; RV64I-NEXT: ld a1, %lo(.LCPI36_0)(a1)
1339 ; RV64I-NEXT: lui a2, %hi(.LCPI36_1)
1340 ; RV64I-NEXT: ld a2, %lo(.LCPI36_1)(a2)
1341 ; RV64I-NEXT: slli a3, a0, 1
1342 ; RV64I-NEXT: and a1, a3, a1
1343 ; RV64I-NEXT: srli a0, a0, 1
1344 ; RV64I-NEXT: and a0, a0, a2
1345 ; RV64I-NEXT: or a0, a1, a0
1346 ; RV64I-NEXT: lui a1, %hi(.LCPI36_2)
1347 ; RV64I-NEXT: ld a1, %lo(.LCPI36_2)(a1)
1348 ; RV64I-NEXT: lui a2, %hi(.LCPI36_3)
1349 ; RV64I-NEXT: ld a2, %lo(.LCPI36_3)(a2)
1350 ; RV64I-NEXT: slli a3, a0, 2
1351 ; RV64I-NEXT: and a1, a3, a1
1352 ; RV64I-NEXT: srli a0, a0, 2
1353 ; RV64I-NEXT: and a0, a0, a2
1354 ; RV64I-NEXT: or a0, a1, a0
1355 ; RV64I-NEXT: ret
1356 ;
1357 ; RV64ZBP-LABEL: grev3_i64:
1358 ; RV64ZBP: # %bb.0:
1359 ; RV64ZBP-NEXT: rev.n a0, a0
1360 ; RV64ZBP-NEXT: ret
1361 %and1 = shl i64 %a, 1
1362 %shl1 = and i64 %and1, -6148914691236517206
1363 %and1b = lshr i64 %a, 1
1364 %shr1 = and i64 %and1b, 6148914691236517205
1365 %or1 = or i64 %shl1, %shr1
1366 %and2 = shl i64 %or1, 2
1367 %shl2 = and i64 %and2, -3689348814741910324
1368 %and2b = lshr i64 %or1, 2
1369 %shr2 = and i64 %and2b, 3689348814741910323
1370 %or2 = or i64 %shl2, %shr2
1371 ret i64 %or2
1372 }
1374 define signext i32 @grev4_i32(i32 signext %a) nounwind {
1375 ; RV64I-LABEL: grev4_i32:
1376 ; RV64I: # %bb.0:
1377 ; RV64I-NEXT: slliw a1, a0, 4
1378 ; RV64I-NEXT: lui a2, 986895
1379 ; RV64I-NEXT: addiw a2, a2, 240
1380 ; RV64I-NEXT: and a1, a1, a2
1381 ; RV64I-NEXT: srli a0, a0, 4
1382 ; RV64I-NEXT: lui a2, 61681
1383 ; RV64I-NEXT: addiw a2, a2, -241
1384 ; RV64I-NEXT: and a0, a0, a2
1385 ; RV64I-NEXT: or a0, a1, a0
1386 ; RV64I-NEXT: ret
1387 ;
1388 ; RV64ZBP-LABEL: grev4_i32:
1389 ; RV64ZBP: # %bb.0:
1390 ; RV64ZBP-NEXT: greviw a0, a0, 4
1391 ; RV64ZBP-NEXT: ret
1392 %and = shl i32 %a, 4
1393 %shl = and i32 %and, -252645136
1394 %and1 = lshr i32 %a, 4
1395 %shr = and i32 %and1, 252645135
1396 %or = or i32 %shl, %shr
1397 ret i32 %or
1398 }
1400 define i64 @grev4_i64(i64 %a) nounwind {
1401 ; RV64I-LABEL: grev4_i64:
1402 ; RV64I: # %bb.0:
1403 ; RV64I-NEXT: lui a1, %hi(.LCPI38_0)
1404 ; RV64I-NEXT: ld a1, %lo(.LCPI38_0)(a1)
1405 ; RV64I-NEXT: lui a2, %hi(.LCPI38_1)
1406 ; RV64I-NEXT: ld a2, %lo(.LCPI38_1)(a2)
1407 ; RV64I-NEXT: slli a3, a0, 4
1408 ; RV64I-NEXT: and a1, a3, a1
1409 ; RV64I-NEXT: srli a0, a0, 4
1410 ; RV64I-NEXT: and a0, a0, a2
1411 ; RV64I-NEXT: or a0, a1, a0
1412 ; RV64I-NEXT: ret
1413 ;
1414 ; RV64ZBP-LABEL: grev4_i64:
1415 ; RV64ZBP: # %bb.0:
1416 ; RV64ZBP-NEXT: rev4.b a0, a0
1417 ; RV64ZBP-NEXT: ret
1418 %and = shl i64 %a, 4
1419 %shl = and i64 %and, -1085102592571150096
1420 %and1 = lshr i64 %a, 4
1421 %shr = and i64 %and1, 1085102592571150095
1422 %or = or i64 %shl, %shr
1423 ret i64 %or
1424 }
1426 define signext i32 @grev5_i32(i32 signext %a) nounwind {
1427 ; RV64I-LABEL: grev5_i32:
1428 ; RV64I: # %bb.0:
1429 ; RV64I-NEXT: slliw a1, a0, 1
1430 ; RV64I-NEXT: lui a2, 699051
1431 ; RV64I-NEXT: addiw a2, a2, -1366
1432 ; RV64I-NEXT: and a1, a1, a2
1433 ; RV64I-NEXT: srli a0, a0, 1
1434 ; RV64I-NEXT: lui a2, 349525
1435 ; RV64I-NEXT: addiw a2, a2, 1365
1436 ; RV64I-NEXT: and a0, a0, a2
1437 ; RV64I-NEXT: or a0, a1, a0
1438 ; RV64I-NEXT: slliw a1, a0, 4
1439 ; RV64I-NEXT: lui a2, 986895
1440 ; RV64I-NEXT: addiw a2, a2, 240
1441 ; RV64I-NEXT: and a1, a1, a2
1442 ; RV64I-NEXT: srli a0, a0, 4
1443 ; RV64I-NEXT: lui a2, 61681
1444 ; RV64I-NEXT: addiw a2, a2, -241
1445 ; RV64I-NEXT: and a0, a0, a2
1446 ; RV64I-NEXT: or a0, a1, a0
1447 ; RV64I-NEXT: ret
1448 ;
1449 ; RV64ZBP-LABEL: grev5_i32:
1450 ; RV64ZBP: # %bb.0:
1451 ; RV64ZBP-NEXT: greviw a0, a0, 5
1452 ; RV64ZBP-NEXT: ret
1453 %and1 = shl i32 %a, 1
1454 %shl1 = and i32 %and1, -1431655766
1455 %and1b = lshr i32 %a, 1
1456 %shr1 = and i32 %and1b, 1431655765
1457 %or1 = or i32 %shl1, %shr1
1458 %and2 = shl i32 %or1, 4
1459 %shl2 = and i32 %and2, -252645136
1460 %and2b = lshr i32 %or1, 4
1461 %shr2 = and i32 %and2b, 252645135
1462 %or2 = or i32 %shl2, %shr2
1463 ret i32 %or2
1464 }
1466 define i64 @grev5_i64(i64 %a) nounwind {
1467 ; RV64I-LABEL: grev5_i64:
1468 ; RV64I: # %bb.0:
1469 ; RV64I-NEXT: lui a1, %hi(.LCPI40_0)
1470 ; RV64I-NEXT: ld a1, %lo(.LCPI40_0)(a1)
1471 ; RV64I-NEXT: lui a2, %hi(.LCPI40_1)
1472 ; RV64I-NEXT: ld a2, %lo(.LCPI40_1)(a2)
1473 ; RV64I-NEXT: slli a3, a0, 1
1474 ; RV64I-NEXT: and a1, a3, a1
1475 ; RV64I-NEXT: srli a0, a0, 1
1476 ; RV64I-NEXT: and a0, a0, a2
1477 ; RV64I-NEXT: or a0, a1, a0
1478 ; RV64I-NEXT: lui a1, %hi(.LCPI40_2)
1479 ; RV64I-NEXT: ld a1, %lo(.LCPI40_2)(a1)
1480 ; RV64I-NEXT: lui a2, %hi(.LCPI40_3)
1481 ; RV64I-NEXT: ld a2, %lo(.LCPI40_3)(a2)
1482 ; RV64I-NEXT: slli a3, a0, 4
1483 ; RV64I-NEXT: and a1, a3, a1
1484 ; RV64I-NEXT: srli a0, a0, 4
1485 ; RV64I-NEXT: and a0, a0, a2
1486 ; RV64I-NEXT: or a0, a1, a0
1487 ; RV64I-NEXT: ret
1488 ;
1489 ; RV64ZBP-LABEL: grev5_i64:
1490 ; RV64ZBP: # %bb.0:
1491 ; RV64ZBP-NEXT: grevi a0, a0, 5
1492 ; RV64ZBP-NEXT: ret
1493 %and1 = shl i64 %a, 1
1494 %shl1 = and i64 %and1, -6148914691236517206
1495 %and1b = lshr i64 %a, 1
1496 %shr1 = and i64 %and1b, 6148914691236517205
1497 %or1 = or i64 %shl1, %shr1
1499 %and2 = shl i64 %or1, 4
1500 %shl2 = and i64 %and2, -1085102592571150096
1501 %and2b = lshr i64 %or1, 4
1502 %shr2 = and i64 %and2b, 1085102592571150095
1503 %or2 = or i64 %shl2, %shr2
1504 ret i64 %or2
1505 }
1507 define signext i32 @grev6_i32(i32 signext %a) nounwind {
1508 ; RV64I-LABEL: grev6_i32:
1509 ; RV64I: # %bb.0:
1510 ; RV64I-NEXT: slliw a1, a0, 2
1511 ; RV64I-NEXT: lui a2, 838861
1512 ; RV64I-NEXT: addiw a2, a2, -820
1513 ; RV64I-NEXT: and a1, a1, a2
1514 ; RV64I-NEXT: srli a0, a0, 2
1515 ; RV64I-NEXT: lui a2, 209715
1516 ; RV64I-NEXT: addiw a2, a2, 819
1517 ; RV64I-NEXT: and a0, a0, a2
1518 ; RV64I-NEXT: or a0, a1, a0
1519 ; RV64I-NEXT: slliw a1, a0, 4
1520 ; RV64I-NEXT: lui a2, 986895
1521 ; RV64I-NEXT: addiw a2, a2, 240
1522 ; RV64I-NEXT: and a1, a1, a2
1523 ; RV64I-NEXT: srli a0, a0, 4
1524 ; RV64I-NEXT: lui a2, 61681
1525 ; RV64I-NEXT: addiw a2, a2, -241
1526 ; RV64I-NEXT: and a0, a0, a2
1527 ; RV64I-NEXT: or a0, a1, a0
1528 ; RV64I-NEXT: ret
1529 ;
1530 ; RV64ZBP-LABEL: grev6_i32:
1531 ; RV64ZBP: # %bb.0:
1532 ; RV64ZBP-NEXT: greviw a0, a0, 6
1533 ; RV64ZBP-NEXT: ret
1534 %and1 = shl i32 %a, 2
1535 %shl1 = and i32 %and1, -858993460
1536 %and1b = lshr i32 %a, 2
1537 %shr1 = and i32 %and1b, 858993459
1538 %or1 = or i32 %shl1, %shr1
1539 %and2 = shl i32 %or1, 4
1540 %shl2 = and i32 %and2, -252645136
1541 %and2b = lshr i32 %or1, 4
1542 %shr2 = and i32 %and2b, 252645135
1543 %or2 = or i32 %shl2, %shr2
1544 ret i32 %or2
1545 }
1547 define i64 @grev6_i64(i64 %a) nounwind {
1548 ; RV64I-LABEL: grev6_i64:
1549 ; RV64I: # %bb.0:
1550 ; RV64I-NEXT: lui a1, %hi(.LCPI42_0)
1551 ; RV64I-NEXT: ld a1, %lo(.LCPI42_0)(a1)
1552 ; RV64I-NEXT: lui a2, %hi(.LCPI42_1)
1553 ; RV64I-NEXT: ld a2, %lo(.LCPI42_1)(a2)
1554 ; RV64I-NEXT: slli a3, a0, 2
1555 ; RV64I-NEXT: and a1, a3, a1
1556 ; RV64I-NEXT: srli a0, a0, 2
1557 ; RV64I-NEXT: and a0, a0, a2
1558 ; RV64I-NEXT: or a0, a1, a0
1559 ; RV64I-NEXT: lui a1, %hi(.LCPI42_2)
1560 ; RV64I-NEXT: ld a1, %lo(.LCPI42_2)(a1)
1561 ; RV64I-NEXT: lui a2, %hi(.LCPI42_3)
1562 ; RV64I-NEXT: ld a2, %lo(.LCPI42_3)(a2)
1563 ; RV64I-NEXT: slli a3, a0, 4
1564 ; RV64I-NEXT: and a1, a3, a1
1565 ; RV64I-NEXT: srli a0, a0, 4
1566 ; RV64I-NEXT: and a0, a0, a2
1567 ; RV64I-NEXT: or a0, a1, a0
1568 ; RV64I-NEXT: ret
1569 ;
1570 ; RV64ZBP-LABEL: grev6_i64:
1571 ; RV64ZBP: # %bb.0:
1572 ; RV64ZBP-NEXT: rev2.b a0, a0
1573 ; RV64ZBP-NEXT: ret
1574 %and1 = shl i64 %a, 2
1575 %shl1 = and i64 %and1, -3689348814741910324
1576 %and1b = lshr i64 %a, 2
1577 %shr1 = and i64 %and1b, 3689348814741910323
1578 %or1 = or i64 %shl1, %shr1
1579 %and2 = shl i64 %or1, 4
1580 %shl2 = and i64 %and2, -1085102592571150096
1581 %and2b = lshr i64 %or1, 4
1582 %shr2 = and i64 %and2b, 1085102592571150095
1583 %or2 = or i64 %shl2, %shr2
1584 ret i64 %or2
1585 }
1587 define signext i32 @grev7_i32(i32 signext %a) nounwind {
1588 ; RV64I-LABEL: grev7_i32:
1589 ; RV64I: # %bb.0:
1590 ; RV64I-NEXT: slliw a1, a0, 1
1591 ; RV64I-NEXT: lui a2, 699051
1592 ; RV64I-NEXT: addiw a2, a2, -1366
1593 ; RV64I-NEXT: and a1, a1, a2
1594 ; RV64I-NEXT: srli a0, a0, 1
1595 ; RV64I-NEXT: lui a2, 349525
1596 ; RV64I-NEXT: addiw a2, a2, 1365
1597 ; RV64I-NEXT: and a0, a0, a2
1598 ; RV64I-NEXT: or a0, a1, a0
1599 ; RV64I-NEXT: slliw a1, a0, 2
1600 ; RV64I-NEXT: lui a2, 838861
1601 ; RV64I-NEXT: addiw a2, a2, -820
1602 ; RV64I-NEXT: and a1, a1, a2
1603 ; RV64I-NEXT: srli a0, a0, 2
1604 ; RV64I-NEXT: lui a2, 209715
1605 ; RV64I-NEXT: addiw a2, a2, 819
1606 ; RV64I-NEXT: and a0, a0, a2
1607 ; RV64I-NEXT: or a0, a1, a0
1608 ; RV64I-NEXT: slliw a1, a0, 4
1609 ; RV64I-NEXT: lui a2, 986895
1610 ; RV64I-NEXT: addiw a2, a2, 240
1611 ; RV64I-NEXT: and a1, a1, a2
1612 ; RV64I-NEXT: srli a0, a0, 4
1613 ; RV64I-NEXT: lui a2, 61681
1614 ; RV64I-NEXT: addiw a2, a2, -241
1615 ; RV64I-NEXT: and a0, a0, a2
1616 ; RV64I-NEXT: or a0, a1, a0
1617 ; RV64I-NEXT: ret
1618 ;
1619 ; RV64ZBP-LABEL: grev7_i32:
1620 ; RV64ZBP: # %bb.0:
1621 ; RV64ZBP-NEXT: greviw a0, a0, 7
1622 ; RV64ZBP-NEXT: ret
1623 %and1 = shl i32 %a, 1
1624 %shl1 = and i32 %and1, -1431655766
1625 %and1b = lshr i32 %a, 1
1626 %shr1 = and i32 %and1b, 1431655765
1627 %or1 = or i32 %shl1, %shr1
1628 %and2 = shl i32 %or1, 2
1629 %shl2 = and i32 %and2, -858993460
1630 %and2b = lshr i32 %or1, 2
1631 %shr2 = and i32 %and2b, 858993459
1632 %or2 = or i32 %shl2, %shr2
1633 %and3 = shl i32 %or2, 4
1634 %shl3 = and i32 %and3, -252645136
1635 %and3b = lshr i32 %or2, 4
1636 %shr3 = and i32 %and3b, 252645135
1637 %or3 = or i32 %shl3, %shr3
1638 ret i32 %or3
1639 }
1641 define zeroext i32 @grev7_i32_zext(i32 zeroext %a) nounwind {
1642 ; RV64I-LABEL: grev7_i32_zext:
1643 ; RV64I: # %bb.0:
1644 ; RV64I-NEXT: slliw a1, a0, 1
1645 ; RV64I-NEXT: lui a2, 699051
1646 ; RV64I-NEXT: addiw a2, a2, -1366
1647 ; RV64I-NEXT: and a1, a1, a2
1648 ; RV64I-NEXT: srli a0, a0, 1
1649 ; RV64I-NEXT: lui a2, 349525
1650 ; RV64I-NEXT: addiw a2, a2, 1365
1651 ; RV64I-NEXT: and a0, a0, a2
1652 ; RV64I-NEXT: or a0, a1, a0
1653 ; RV64I-NEXT: slliw a1, a0, 2
1654 ; RV64I-NEXT: lui a2, 838861
1655 ; RV64I-NEXT: addiw a2, a2, -820
1656 ; RV64I-NEXT: and a1, a1, a2
1657 ; RV64I-NEXT: srli a0, a0, 2
1658 ; RV64I-NEXT: lui a2, 209715
1659 ; RV64I-NEXT: addiw a2, a2, 819
1660 ; RV64I-NEXT: and a0, a0, a2
1661 ; RV64I-NEXT: or a0, a1, a0
1662 ; RV64I-NEXT: slli a1, a0, 4
1663 ; RV64I-NEXT: lui a2, 61681
1664 ; RV64I-NEXT: addiw a2, a2, -241
1665 ; RV64I-NEXT: slli a3, a2, 4
1666 ; RV64I-NEXT: and a1, a1, a3
1667 ; RV64I-NEXT: srli a0, a0, 4
1668 ; RV64I-NEXT: and a0, a0, a2
1669 ; RV64I-NEXT: or a0, a1, a0
1670 ; RV64I-NEXT: ret
1671 ;
1672 ; RV64ZBP-LABEL: grev7_i32_zext:
1673 ; RV64ZBP: # %bb.0:
1674 ; RV64ZBP-NEXT: rev.b a0, a0
1675 ; RV64ZBP-NEXT: ret
1676 %and1 = shl i32 %a, 1
1677 %shl1 = and i32 %and1, -1431655766
1678 %and1b = lshr i32 %a, 1
1679 %shr1 = and i32 %and1b, 1431655765
1680 %or1 = or i32 %shl1, %shr1
1681 %and2 = shl i32 %or1, 2
1682 %shl2 = and i32 %and2, -858993460
1683 %and2b = lshr i32 %or1, 2
1684 %shr2 = and i32 %and2b, 858993459
1685 %or2 = or i32 %shl2, %shr2
1686 %and3 = shl i32 %or2, 4
1687 %shl3 = and i32 %and3, -252645136
1688 %and3b = lshr i32 %or2, 4
1689 %shr3 = and i32 %and3b, 252645135
1690 %or3 = or i32 %shl3, %shr3
1691 ret i32 %or3
1692 }
1694 define i64 @grev7_i64(i64 %a) nounwind {
1695 ; RV64I-LABEL: grev7_i64:
1696 ; RV64I: # %bb.0:
1697 ; RV64I-NEXT: lui a1, %hi(.LCPI45_0)
1698 ; RV64I-NEXT: ld a1, %lo(.LCPI45_0)(a1)
1699 ; RV64I-NEXT: lui a2, %hi(.LCPI45_1)
1700 ; RV64I-NEXT: ld a2, %lo(.LCPI45_1)(a2)
1701 ; RV64I-NEXT: slli a3, a0, 1
1702 ; RV64I-NEXT: and a1, a3, a1
1703 ; RV64I-NEXT: srli a0, a0, 1
1704 ; RV64I-NEXT: and a0, a0, a2
1705 ; RV64I-NEXT: or a0, a1, a0
1706 ; RV64I-NEXT: lui a1, %hi(.LCPI45_2)
1707 ; RV64I-NEXT: ld a1, %lo(.LCPI45_2)(a1)
1708 ; RV64I-NEXT: lui a2, %hi(.LCPI45_3)
1709 ; RV64I-NEXT: ld a2, %lo(.LCPI45_3)(a2)
1710 ; RV64I-NEXT: slli a3, a0, 2
1711 ; RV64I-NEXT: and a1, a3, a1
1712 ; RV64I-NEXT: srli a0, a0, 2
1713 ; RV64I-NEXT: and a0, a0, a2
1714 ; RV64I-NEXT: or a0, a1, a0
1715 ; RV64I-NEXT: lui a1, %hi(.LCPI45_4)
1716 ; RV64I-NEXT: ld a1, %lo(.LCPI45_4)(a1)
1717 ; RV64I-NEXT: lui a2, %hi(.LCPI45_5)
1718 ; RV64I-NEXT: ld a2, %lo(.LCPI45_5)(a2)
1719 ; RV64I-NEXT: slli a3, a0, 4
1720 ; RV64I-NEXT: and a1, a3, a1
1721 ; RV64I-NEXT: srli a0, a0, 4
1722 ; RV64I-NEXT: and a0, a0, a2
1723 ; RV64I-NEXT: or a0, a1, a0
1724 ; RV64I-NEXT: ret
1725 ;
1726 ; RV64ZBP-LABEL: grev7_i64:
1727 ; RV64ZBP: # %bb.0:
1728 ; RV64ZBP-NEXT: rev.b a0, a0
1729 ; RV64ZBP-NEXT: ret
1730 %and1 = shl i64 %a, 1
1731 %shl1 = and i64 %and1, -6148914691236517206
1732 %and1b = lshr i64 %a, 1
1733 %shr1 = and i64 %and1b, 6148914691236517205
1734 %or1 = or i64 %shl1, %shr1
1735 %and2 = shl i64 %or1, 2
1736 %shl2 = and i64 %and2, -3689348814741910324
1737 %and2b = lshr i64 %or1, 2
1738 %shr2 = and i64 %and2b, 3689348814741910323
1739 %or2 = or i64 %shl2, %shr2
1740 %and3 = shl i64 %or2, 4
1741 %shl3 = and i64 %and3, -1085102592571150096
1742 %and3b = lshr i64 %or2, 4
1743 %shr3 = and i64 %and3b, 1085102592571150095
1744 %or3 = or i64 %shl3, %shr3
1745 ret i64 %or3
1746 }
1748 define signext i32 @grev8_i32(i32 signext %a) nounwind {
1749 ; RV64I-LABEL: grev8_i32:
1750 ; RV64I: # %bb.0:
1751 ; RV64I-NEXT: slliw a1, a0, 8
1752 ; RV64I-NEXT: lui a2, 1044496
1753 ; RV64I-NEXT: addiw a2, a2, -256
1754 ; RV64I-NEXT: and a1, a1, a2
1755 ; RV64I-NEXT: srli a0, a0, 8
1756 ; RV64I-NEXT: lui a2, 4080
1757 ; RV64I-NEXT: addiw a2, a2, 255
1758 ; RV64I-NEXT: and a0, a0, a2
1759 ; RV64I-NEXT: or a0, a1, a0
1760 ; RV64I-NEXT: ret
1761 ;
1762 ; RV64ZBP-LABEL: grev8_i32:
1763 ; RV64ZBP: # %bb.0:
1764 ; RV64ZBP-NEXT: greviw a0, a0, 8
1765 ; RV64ZBP-NEXT: ret
1766 %and = shl i32 %a, 8
1767 %shl = and i32 %and, -16711936
1768 %and1 = lshr i32 %a, 8
1769 %shr = and i32 %and1, 16711935
1770 %or = or i32 %shl, %shr
1771 ret i32 %or
1772 }
1774 define i64 @grev8_i64(i64 %a) nounwind {
1775 ; RV64I-LABEL: grev8_i64:
1776 ; RV64I: # %bb.0:
1777 ; RV64I-NEXT: lui a1, %hi(.LCPI47_0)
1778 ; RV64I-NEXT: ld a1, %lo(.LCPI47_0)(a1)
1779 ; RV64I-NEXT: lui a2, %hi(.LCPI47_1)
1780 ; RV64I-NEXT: ld a2, %lo(.LCPI47_1)(a2)
1781 ; RV64I-NEXT: slli a3, a0, 8
1782 ; RV64I-NEXT: and a1, a3, a1
1783 ; RV64I-NEXT: srli a0, a0, 8
1784 ; RV64I-NEXT: and a0, a0, a2
1785 ; RV64I-NEXT: or a0, a1, a0
1786 ; RV64I-NEXT: ret
1787 ;
1788 ; RV64ZBP-LABEL: grev8_i64:
1789 ; RV64ZBP: # %bb.0:
1790 ; RV64ZBP-NEXT: rev8.h a0, a0
1791 ; RV64ZBP-NEXT: ret
1792 %and = shl i64 %a, 8
1793 %shl = and i64 %and, -71777214294589696
1794 %and1 = lshr i64 %a, 8
1795 %shr = and i64 %and1, 71777214294589695
1796 %or = or i64 %shl, %shr
1797 ret i64 %or
1798 }
1800 define signext i32 @grev12_i32(i32 signext %a) nounwind {
1801 ; RV64I-LABEL: grev12_i32:
1802 ; RV64I: # %bb.0:
1803 ; RV64I-NEXT: slliw a1, a0, 4
1804 ; RV64I-NEXT: lui a2, 986895
1805 ; RV64I-NEXT: addiw a2, a2, 240
1806 ; RV64I-NEXT: and a1, a1, a2
1807 ; RV64I-NEXT: srli a0, a0, 4
1808 ; RV64I-NEXT: lui a2, 61681
1809 ; RV64I-NEXT: addiw a2, a2, -241
1810 ; RV64I-NEXT: and a0, a0, a2
1811 ; RV64I-NEXT: or a0, a1, a0
1812 ; RV64I-NEXT: slliw a1, a0, 8
1813 ; RV64I-NEXT: lui a2, 1044496
1814 ; RV64I-NEXT: addiw a2, a2, -256
1815 ; RV64I-NEXT: and a1, a1, a2
1816 ; RV64I-NEXT: srli a0, a0, 8
1817 ; RV64I-NEXT: lui a2, 4080
1818 ; RV64I-NEXT: addiw a2, a2, 255
1819 ; RV64I-NEXT: and a0, a0, a2
1820 ; RV64I-NEXT: or a0, a1, a0
1821 ; RV64I-NEXT: ret
1822 ;
1823 ; RV64ZBP-LABEL: grev12_i32:
1824 ; RV64ZBP: # %bb.0:
1825 ; RV64ZBP-NEXT: greviw a0, a0, 12
1826 ; RV64ZBP-NEXT: ret
1827 %and1 = shl i32 %a, 4
1828 %shl1 = and i32 %and1, -252645136
1829 %and1b = lshr i32 %a, 4
1830 %shr1 = and i32 %and1b, 252645135
1831 %or1 = or i32 %shl1, %shr1
1832 %and2 = shl i32 %or1, 8
1833 %shl2 = and i32 %and2, -16711936
1834 %and2b = lshr i32 %or1, 8
1835 %shr2 = and i32 %and2b, 16711935
1836 %or2 = or i32 %shl2, %shr2
1837 ret i32 %or2
1838 }
1840 define i64 @grev12_i64(i64 %a) nounwind {
1841 ; RV64I-LABEL: grev12_i64:
1842 ; RV64I: # %bb.0:
1843 ; RV64I-NEXT: lui a1, %hi(.LCPI49_0)
1844 ; RV64I-NEXT: ld a1, %lo(.LCPI49_0)(a1)
1845 ; RV64I-NEXT: lui a2, %hi(.LCPI49_1)
1846 ; RV64I-NEXT: ld a2, %lo(.LCPI49_1)(a2)
1847 ; RV64I-NEXT: slli a3, a0, 4
1848 ; RV64I-NEXT: and a1, a3, a1
1849 ; RV64I-NEXT: srli a0, a0, 4
1850 ; RV64I-NEXT: and a0, a0, a2
1851 ; RV64I-NEXT: or a0, a1, a0
1852 ; RV64I-NEXT: lui a1, %hi(.LCPI49_2)
1853 ; RV64I-NEXT: ld a1, %lo(.LCPI49_2)(a1)
1854 ; RV64I-NEXT: lui a2, %hi(.LCPI49_3)
1855 ; RV64I-NEXT: ld a2, %lo(.LCPI49_3)(a2)
1856 ; RV64I-NEXT: slli a3, a0, 8
1857 ; RV64I-NEXT: and a1, a3, a1
1858 ; RV64I-NEXT: srli a0, a0, 8
1859 ; RV64I-NEXT: and a0, a0, a2
1860 ; RV64I-NEXT: or a0, a1, a0
1861 ; RV64I-NEXT: ret
1862 ;
1863 ; RV64ZBP-LABEL: grev12_i64:
1864 ; RV64ZBP: # %bb.0:
1865 ; RV64ZBP-NEXT: rev4.h a0, a0
1866 ; RV64ZBP-NEXT: ret
1867 %and1 = shl i64 %a, 4
1868 %shl1 = and i64 %and1, -1085102592571150096
1869 %and1b = lshr i64 %a, 4
1870 %shr1 = and i64 %and1b, 1085102592571150095
1871 %or1 = or i64 %shl1, %shr1
1872 %and2 = shl i64 %or1, 8
1873 %shl2 = and i64 %and2, -71777214294589696
1874 %and2b = lshr i64 %or1, 8
1875 %shr2 = and i64 %and2b, 71777214294589695
1876 %or2 = or i64 %shl2, %shr2
1877 ret i64 %or2
1878 }
1880 define signext i32 @grev14_i32(i32 signext %a) nounwind {
1881 ; RV64I-LABEL: grev14_i32:
1882 ; RV64I: # %bb.0:
1883 ; RV64I-NEXT: slliw a1, a0, 2
1884 ; RV64I-NEXT: lui a2, 838861
1885 ; RV64I-NEXT: addiw a2, a2, -820
1886 ; RV64I-NEXT: and a1, a1, a2
1887 ; RV64I-NEXT: srli a0, a0, 2
1888 ; RV64I-NEXT: lui a2, 209715
1889 ; RV64I-NEXT: addiw a2, a2, 819
1890 ; RV64I-NEXT: and a0, a0, a2
1891 ; RV64I-NEXT: or a0, a1, a0
1892 ; RV64I-NEXT: slliw a1, a0, 4
1893 ; RV64I-NEXT: lui a2, 986895
1894 ; RV64I-NEXT: addiw a2, a2, 240
1895 ; RV64I-NEXT: and a1, a1, a2
1896 ; RV64I-NEXT: srli a0, a0, 4
1897 ; RV64I-NEXT: lui a2, 61681
1898 ; RV64I-NEXT: addiw a2, a2, -241
1899 ; RV64I-NEXT: and a0, a0, a2
1900 ; RV64I-NEXT: or a0, a1, a0
1901 ; RV64I-NEXT: slliw a1, a0, 8
1902 ; RV64I-NEXT: lui a2, 1044496
1903 ; RV64I-NEXT: addiw a2, a2, -256
1904 ; RV64I-NEXT: and a1, a1, a2
1905 ; RV64I-NEXT: srli a0, a0, 8
1906 ; RV64I-NEXT: lui a2, 4080
1907 ; RV64I-NEXT: addiw a2, a2, 255
1908 ; RV64I-NEXT: and a0, a0, a2
1909 ; RV64I-NEXT: or a0, a1, a0
1910 ; RV64I-NEXT: ret
1911 ;
1912 ; RV64ZBP-LABEL: grev14_i32:
1913 ; RV64ZBP: # %bb.0:
1914 ; RV64ZBP-NEXT: greviw a0, a0, 14
1915 ; RV64ZBP-NEXT: ret
1916 %and1 = shl i32 %a, 2
1917 %shl1 = and i32 %and1, -858993460
1918 %and1b = lshr i32 %a, 2
1919 %shr1 = and i32 %and1b, 858993459
1920 %or1 = or i32 %shl1, %shr1
1921 %and2 = shl i32 %or1, 4
1922 %shl2 = and i32 %and2, -252645136
1923 %and2b = lshr i32 %or1, 4
1924 %shr2 = and i32 %and2b, 252645135
1925 %or2 = or i32 %shl2, %shr2
1926 %and3 = shl i32 %or2, 8
1927 %shl3 = and i32 %and3, -16711936
1928 %and3b = lshr i32 %or2, 8
1929 %shr3 = and i32 %and3b, 16711935
1930 %or3 = or i32 %shl3, %shr3
1931 ret i32 %or3
1932 }
1934 define i64 @grev14_i64(i64 %a) nounwind {
1935 ; RV64I-LABEL: grev14_i64:
1936 ; RV64I: # %bb.0:
1937 ; RV64I-NEXT: lui a1, %hi(.LCPI51_0)
1938 ; RV64I-NEXT: ld a1, %lo(.LCPI51_0)(a1)
1939 ; RV64I-NEXT: lui a2, %hi(.LCPI51_1)
1940 ; RV64I-NEXT: ld a2, %lo(.LCPI51_1)(a2)
1941 ; RV64I-NEXT: slli a3, a0, 2
1942 ; RV64I-NEXT: and a1, a3, a1
1943 ; RV64I-NEXT: srli a0, a0, 2
1944 ; RV64I-NEXT: and a0, a0, a2
1945 ; RV64I-NEXT: or a0, a1, a0
1946 ; RV64I-NEXT: lui a1, %hi(.LCPI51_2)
1947 ; RV64I-NEXT: ld a1, %lo(.LCPI51_2)(a1)
1948 ; RV64I-NEXT: lui a2, %hi(.LCPI51_3)
1949 ; RV64I-NEXT: ld a2, %lo(.LCPI51_3)(a2)
1950 ; RV64I-NEXT: slli a3, a0, 4
1951 ; RV64I-NEXT: and a1, a3, a1
1952 ; RV64I-NEXT: srli a0, a0, 4
1953 ; RV64I-NEXT: and a0, a0, a2
1954 ; RV64I-NEXT: or a0, a1, a0
1955 ; RV64I-NEXT: lui a1, %hi(.LCPI51_4)
1956 ; RV64I-NEXT: ld a1, %lo(.LCPI51_4)(a1)
1957 ; RV64I-NEXT: lui a2, %hi(.LCPI51_5)
1958 ; RV64I-NEXT: ld a2, %lo(.LCPI51_5)(a2)
1959 ; RV64I-NEXT: slli a3, a0, 8
1960 ; RV64I-NEXT: and a1, a3, a1
1961 ; RV64I-NEXT: srli a0, a0, 8
1962 ; RV64I-NEXT: and a0, a0, a2
1963 ; RV64I-NEXT: or a0, a1, a0
1964 ; RV64I-NEXT: ret
1965 ;
1966 ; RV64ZBP-LABEL: grev14_i64:
1967 ; RV64ZBP: # %bb.0:
1968 ; RV64ZBP-NEXT: rev2.h a0, a0
1969 ; RV64ZBP-NEXT: ret
1970 %and1 = shl i64 %a, 2
1971 %shl1 = and i64 %and1, -3689348814741910324
1972 %and1b = lshr i64 %a, 2
1973 %shr1 = and i64 %and1b, 3689348814741910323
1974 %or1 = or i64 %shl1, %shr1
1975 %and2 = shl i64 %or1, 4
1976 %shl2 = and i64 %and2, -1085102592571150096
1977 %and2b = lshr i64 %or1, 4
1978 %shr2 = and i64 %and2b, 1085102592571150095
1979 %or2 = or i64 %shl2, %shr2
1980 %and3 = shl i64 %or2, 8
1981 %shl3 = and i64 %and3, -71777214294589696
1982 %and3b = lshr i64 %or2, 8
1983 %shr3 = and i64 %and3b, 71777214294589695
1984 %or3 = or i64 %shl3, %shr3
1985 ret i64 %or3
1986 }
1988 define signext i32 @grev16_i32(i32 signext %a) nounwind {
1989 ; RV64I-LABEL: grev16_i32:
1990 ; RV64I: # %bb.0:
1991 ; RV64I-NEXT: srliw a1, a0, 16
1992 ; RV64I-NEXT: slliw a0, a0, 16
1993 ; RV64I-NEXT: or a0, a0, a1
1994 ; RV64I-NEXT: ret
1995 ;
1996 ; RV64ZBP-LABEL: grev16_i32:
1997 ; RV64ZBP: # %bb.0:
1998 ; RV64ZBP-NEXT: roriw a0, a0, 16
1999 ; RV64ZBP-NEXT: ret
2000 %shl = shl i32 %a, 16
2001 %shr = lshr i32 %a, 16
2002 %or = or i32 %shl, %shr
2003 ret i32 %or
2004 }
2006 declare i32 @llvm.fshl.i32(i32, i32, i32)
2007 declare i32 @llvm.fshr.i32(i32, i32, i32)
2009 define signext i32 @grev16_i32_fshl(i32 signext %a) nounwind {
2010 ; RV64I-LABEL: grev16_i32_fshl:
2011 ; RV64I: # %bb.0:
2012 ; RV64I-NEXT: srliw a1, a0, 16
2013 ; RV64I-NEXT: slliw a0, a0, 16
2014 ; RV64I-NEXT: or a0, a0, a1
2015 ; RV64I-NEXT: ret
2016 ;
2017 ; RV64ZBP-LABEL: grev16_i32_fshl:
2018 ; RV64ZBP: # %bb.0:
2019 ; RV64ZBP-NEXT: roriw a0, a0, 16
2020 ; RV64ZBP-NEXT: ret
2021 %or = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 16)
2022 ret i32 %or
2023 }
2025 define signext i32 @grev16_i32_fshr(i32 signext %a) nounwind {
2026 ; RV64I-LABEL: grev16_i32_fshr:
2027 ; RV64I: # %bb.0:
2028 ; RV64I-NEXT: slliw a1, a0, 16
2029 ; RV64I-NEXT: srliw a0, a0, 16
2030 ; RV64I-NEXT: or a0, a0, a1
2031 ; RV64I-NEXT: ret
2032 ;
2033 ; RV64ZBP-LABEL: grev16_i32_fshr:
2034 ; RV64ZBP: # %bb.0:
2035 ; RV64ZBP-NEXT: roriw a0, a0, 16
2036 ; RV64ZBP-NEXT: ret
2037 %or = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 16)
2038 ret i32 %or
2039 }
2041 define i64 @grev16_i64(i64 %a) nounwind {
2042 ; RV64I-LABEL: grev16_i64:
2043 ; RV64I: # %bb.0:
2044 ; RV64I-NEXT: slli a1, a0, 16
2045 ; RV64I-NEXT: lui a2, 983041
2046 ; RV64I-NEXT: slli a3, a2, 4
2047 ; RV64I-NEXT: addi a3, a3, -1
2048 ; RV64I-NEXT: slli a3, a3, 16
2049 ; RV64I-NEXT: and a1, a1, a3
2050 ; RV64I-NEXT: srli a0, a0, 16
2051 ; RV64I-NEXT: slli a2, a2, 20
2052 ; RV64I-NEXT: addi a2, a2, -1
2053 ; RV64I-NEXT: srli a2, a2, 16
2054 ; RV64I-NEXT: and a0, a0, a2
2055 ; RV64I-NEXT: or a0, a1, a0
2056 ; RV64I-NEXT: ret
2057 ;
2058 ; RV64ZBP-LABEL: grev16_i64:
2059 ; RV64ZBP: # %bb.0:
2060 ; RV64ZBP-NEXT: rev16.w a0, a0
2061 ; RV64ZBP-NEXT: ret
2062 %and = shl i64 %a, 16
2063 %shl = and i64 %and, -281470681808896
2064 %and1 = lshr i64 %a, 16
2065 %shr = and i64 %and1, 281470681808895
2066 %or = or i64 %shl, %shr
2067 ret i64 %or
2068 }
2070 define i64 @grev32(i64 %a) nounwind {
2071 ; RV64I-LABEL: grev32:
2072 ; RV64I: # %bb.0:
2073 ; RV64I-NEXT: srli a1, a0, 32
2074 ; RV64I-NEXT: slli a0, a0, 32
2075 ; RV64I-NEXT: or a0, a0, a1
2076 ; RV64I-NEXT: ret
2077 ;
2078 ; RV64ZBP-LABEL: grev32:
2079 ; RV64ZBP: # %bb.0:
2080 ; RV64ZBP-NEXT: rori a0, a0, 32
2081 ; RV64ZBP-NEXT: ret
2082 %shl = shl i64 %a, 32
2083 %shr = lshr i64 %a, 32
2084 %or = or i64 %shl, %shr
2085 ret i64 %or
2086 }
2088 define signext i32 @grev3b_i32(i32 signext %a) nounwind {
2089 ; RV64I-LABEL: grev3b_i32:
2090 ; RV64I: # %bb.0:
2091 ; RV64I-NEXT: slliw a1, a0, 2
2092 ; RV64I-NEXT: lui a2, 838861
2093 ; RV64I-NEXT: addiw a2, a2, -820
2094 ; RV64I-NEXT: and a1, a1, a2
2095 ; RV64I-NEXT: srli a0, a0, 2
2096 ; RV64I-NEXT: lui a2, 209715
2097 ; RV64I-NEXT: addiw a2, a2, 819
2098 ; RV64I-NEXT: and a0, a0, a2
2099 ; RV64I-NEXT: or a0, a1, a0
2100 ; RV64I-NEXT: slliw a1, a0, 1
2101 ; RV64I-NEXT: lui a2, 699051
2102 ; RV64I-NEXT: addiw a2, a2, -1366
2103 ; RV64I-NEXT: and a1, a1, a2
2104 ; RV64I-NEXT: srli a0, a0, 1
2105 ; RV64I-NEXT: lui a2, 349525
2106 ; RV64I-NEXT: addiw a2, a2, 1365
2107 ; RV64I-NEXT: and a0, a0, a2
2108 ; RV64I-NEXT: or a0, a1, a0
2109 ; RV64I-NEXT: ret
2110 ;
2111 ; RV64ZBP-LABEL: grev3b_i32:
2112 ; RV64ZBP: # %bb.0:
2113 ; RV64ZBP-NEXT: greviw a0, a0, 3
2114 ; RV64ZBP-NEXT: ret
2115 %and2 = shl i32 %a, 2
2116 %shl2 = and i32 %and2, -858993460
2117 %and2b = lshr i32 %a, 2
2118 %shr2 = and i32 %and2b, 858993459
2119 %or2 = or i32 %shl2, %shr2
2120 %and1 = shl i32 %or2, 1
2121 %shl1 = and i32 %and1, -1431655766
2122 %and1b = lshr i32 %or2, 1
2123 %shr1 = and i32 %and1b, 1431655765
2124 %or1 = or i32 %shl1, %shr1
2125 ret i32 %or1
2126 }
2128 define i64 @grev3b_i64(i64 %a) nounwind {
2129 ; RV64I-LABEL: grev3b_i64:
2130 ; RV64I: # %bb.0:
2131 ; RV64I-NEXT: lui a1, %hi(.LCPI58_0)
2132 ; RV64I-NEXT: ld a1, %lo(.LCPI58_0)(a1)
2133 ; RV64I-NEXT: lui a2, %hi(.LCPI58_1)
2134 ; RV64I-NEXT: ld a2, %lo(.LCPI58_1)(a2)
2135 ; RV64I-NEXT: slli a3, a0, 2
2136 ; RV64I-NEXT: and a1, a3, a1
2137 ; RV64I-NEXT: srli a0, a0, 2
2138 ; RV64I-NEXT: and a0, a0, a2
2139 ; RV64I-NEXT: or a0, a1, a0
2140 ; RV64I-NEXT: lui a1, %hi(.LCPI58_2)
2141 ; RV64I-NEXT: ld a1, %lo(.LCPI58_2)(a1)
2142 ; RV64I-NEXT: lui a2, %hi(.LCPI58_3)
2143 ; RV64I-NEXT: ld a2, %lo(.LCPI58_3)(a2)
2144 ; RV64I-NEXT: slli a3, a0, 1
2145 ; RV64I-NEXT: and a1, a3, a1
2146 ; RV64I-NEXT: srli a0, a0, 1
2147 ; RV64I-NEXT: and a0, a0, a2
2148 ; RV64I-NEXT: or a0, a1, a0
2149 ; RV64I-NEXT: ret
2150 ;
2151 ; RV64ZBP-LABEL: grev3b_i64:
2152 ; RV64ZBP: # %bb.0:
2153 ; RV64ZBP-NEXT: rev.n a0, a0
2154 ; RV64ZBP-NEXT: ret
2155 %and2 = shl i64 %a, 2
2156 %shl2 = and i64 %and2, -3689348814741910324
2157 %and2b = lshr i64 %a, 2
2158 %shr2 = and i64 %and2b, 3689348814741910323
2159 %or2 = or i64 %shl2, %shr2
2160 %and1 = shl i64 %or2, 1
2161 %shl1 = and i64 %and1, -6148914691236517206
2162 %and1b = lshr i64 %or2, 1
2163 %shr1 = and i64 %and1b, 6148914691236517205
2164 %or1 = or i64 %shl1, %shr1
2165 ret i64 %or1
2166 }
2168 ; grev1, grev2, grev1 -> grev2
2169 define signext i32 @grev2b_i32(i32 signext %a) nounwind {
2170 ; RV64I-LABEL: grev2b_i32:
2171 ; RV64I: # %bb.0:
2172 ; RV64I-NEXT: slliw a1, a0, 1
2173 ; RV64I-NEXT: lui a2, 699051
2174 ; RV64I-NEXT: addiw a2, a2, -1366
2175 ; RV64I-NEXT: and a1, a1, a2
2176 ; RV64I-NEXT: srli a0, a0, 1
2177 ; RV64I-NEXT: lui a3, 349525
2178 ; RV64I-NEXT: addiw a3, a3, 1365
2179 ; RV64I-NEXT: and a0, a0, a3
2180 ; RV64I-NEXT: or a0, a1, a0
2181 ; RV64I-NEXT: slliw a1, a0, 2
2182 ; RV64I-NEXT: lui a4, 838861
2183 ; RV64I-NEXT: addiw a4, a4, -820
2184 ; RV64I-NEXT: and a1, a1, a4
2185 ; RV64I-NEXT: srli a0, a0, 2
2186 ; RV64I-NEXT: lui a4, 209715
2187 ; RV64I-NEXT: addiw a4, a4, 819
2188 ; RV64I-NEXT: and a0, a0, a4
2189 ; RV64I-NEXT: or a0, a1, a0
2190 ; RV64I-NEXT: slliw a1, a0, 1
2191 ; RV64I-NEXT: and a1, a1, a2
2192 ; RV64I-NEXT: srli a0, a0, 1
2193 ; RV64I-NEXT: and a0, a0, a3
2194 ; RV64I-NEXT: or a0, a1, a0
2195 ; RV64I-NEXT: ret
2196 ;
2197 ; RV64ZBP-LABEL: grev2b_i32:
2198 ; RV64ZBP: # %bb.0:
2199 ; RV64ZBP-NEXT: greviw a0, a0, 2
2200 ; RV64ZBP-NEXT: ret
2201 %and1 = shl i32 %a, 1
2202 %shl1 = and i32 %and1, -1431655766
2203 %and1b = lshr i32 %a, 1
2204 %shr1 = and i32 %and1b, 1431655765
2205 %or1 = or i32 %shl1, %shr1
2206 %and2 = shl i32 %or1, 2
2207 %shl2 = and i32 %and2, -858993460
2208 %and2b = lshr i32 %or1, 2
2209 %shr2 = and i32 %and2b, 858993459
2210 %or2 = or i32 %shl2, %shr2
2211 %and3 = shl i32 %or2, 1
2212 %shl3 = and i32 %and3, -1431655766
2213 %and3b = lshr i32 %or2, 1
2214 %shr3 = and i32 %and3b, 1431655765
2215 %or3 = or i32 %shl3, %shr3
2216 ret i32 %or3
2217 }
2219 ; grev1, grev2, grev1 -> grev2
2220 define i64 @grev2b_i64(i64 %a) nounwind {
2221 ; RV64I-LABEL: grev2b_i64:
2222 ; RV64I: # %bb.0:
2223 ; RV64I-NEXT: lui a1, %hi(.LCPI60_0)
2224 ; RV64I-NEXT: ld a1, %lo(.LCPI60_0)(a1)
2225 ; RV64I-NEXT: lui a2, %hi(.LCPI60_1)
2226 ; RV64I-NEXT: ld a2, %lo(.LCPI60_1)(a2)
2227 ; RV64I-NEXT: slli a3, a0, 1
2228 ; RV64I-NEXT: and a3, a3, a1
2229 ; RV64I-NEXT: srli a0, a0, 1
2230 ; RV64I-NEXT: and a0, a0, a2
2231 ; RV64I-NEXT: or a0, a3, a0
2232 ; RV64I-NEXT: lui a3, %hi(.LCPI60_2)
2233 ; RV64I-NEXT: ld a3, %lo(.LCPI60_2)(a3)
2234 ; RV64I-NEXT: lui a4, %hi(.LCPI60_3)
2235 ; RV64I-NEXT: ld a4, %lo(.LCPI60_3)(a4)
2236 ; RV64I-NEXT: slli a5, a0, 2
2237 ; RV64I-NEXT: and a3, a5, a3
2238 ; RV64I-NEXT: srli a0, a0, 2
2239 ; RV64I-NEXT: and a0, a0, a4
2240 ; RV64I-NEXT: or a0, a3, a0
2241 ; RV64I-NEXT: slli a3, a0, 1
2242 ; RV64I-NEXT: and a1, a3, a1
2243 ; RV64I-NEXT: srli a0, a0, 1
2244 ; RV64I-NEXT: and a0, a0, a2
2245 ; RV64I-NEXT: or a0, a1, a0
2246 ; RV64I-NEXT: ret
2247 ;
2248 ; RV64ZBP-LABEL: grev2b_i64:
2249 ; RV64ZBP: # %bb.0:
2250 ; RV64ZBP-NEXT: rev2.n a0, a0
2251 ; RV64ZBP-NEXT: ret
2252 %and1 = shl i64 %a, 1
2253 %shl1 = and i64 %and1, -6148914691236517206
2254 %and1b = lshr i64 %a, 1
2255 %shr1 = and i64 %and1b, 6148914691236517205
2256 %or1 = or i64 %shl1, %shr1
2257 %and2 = shl i64 %or1, 2
2258 %shl2 = and i64 %and2, -3689348814741910324
2259 %and2b = lshr i64 %or1, 2
2260 %shr2 = and i64 %and2b, 3689348814741910323
2261 %or2 = or i64 %shl2, %shr2
2262 %and3 = shl i64 %or2, 1
2263 %shl3 = and i64 %and3, -6148914691236517206
2264 %and3b = lshr i64 %or2, 1
2265 %shr3 = and i64 %and3b, 6148914691236517205
2266 %or3 = or i64 %shl3, %shr3
2267 ret i64 %or3
2268 }
2270 ; grev1, grev2, grev1, grev2 -> identity
2271 define signext i32 @grev0_i32(i32 signext %a) nounwind {
2272 ; RV64I-LABEL: grev0_i32:
2273 ; RV64I: # %bb.0:
2274 ; RV64I-NEXT: slliw a1, a0, 1
2275 ; RV64I-NEXT: lui a2, 699051
2276 ; RV64I-NEXT: addiw a2, a2, -1366
2277 ; RV64I-NEXT: and a1, a1, a2
2278 ; RV64I-NEXT: srli a0, a0, 1
2279 ; RV64I-NEXT: lui a3, 349525
2280 ; RV64I-NEXT: addiw a3, a3, 1365
2281 ; RV64I-NEXT: and a0, a0, a3
2282 ; RV64I-NEXT: or a0, a1, a0
2283 ; RV64I-NEXT: slliw a1, a0, 2
2284 ; RV64I-NEXT: lui a4, 838861
2285 ; RV64I-NEXT: addiw a4, a4, -820
2286 ; RV64I-NEXT: and a1, a1, a4
2287 ; RV64I-NEXT: srli a0, a0, 2
2288 ; RV64I-NEXT: lui a5, 209715
2289 ; RV64I-NEXT: addiw a5, a5, 819
2290 ; RV64I-NEXT: and a0, a0, a5
2291 ; RV64I-NEXT: or a0, a1, a0
2292 ; RV64I-NEXT: slliw a1, a0, 1
2293 ; RV64I-NEXT: and a1, a1, a2
2294 ; RV64I-NEXT: srli a0, a0, 1
2295 ; RV64I-NEXT: and a0, a0, a3
2296 ; RV64I-NEXT: or a0, a1, a0
2297 ; RV64I-NEXT: slliw a1, a0, 2
2298 ; RV64I-NEXT: and a1, a1, a4
2299 ; RV64I-NEXT: srli a0, a0, 2
2300 ; RV64I-NEXT: and a0, a0, a5
2301 ; RV64I-NEXT: or a0, a1, a0
2302 ; RV64I-NEXT: ret
2303 ;
2304 ; RV64ZBP-LABEL: grev0_i32:
2305 ; RV64ZBP: # %bb.0:
2306 ; RV64ZBP-NEXT: ret
2307 %and1 = shl i32 %a, 1
2308 %shl1 = and i32 %and1, -1431655766
2309 %and1b = lshr i32 %a, 1
2310 %shr1 = and i32 %and1b, 1431655765
2311 %or1 = or i32 %shl1, %shr1
2312 %and2 = shl i32 %or1, 2
2313 %shl2 = and i32 %and2, -858993460
2314 %and2b = lshr i32 %or1, 2
2315 %shr2 = and i32 %and2b, 858993459
2316 %or2 = or i32 %shl2, %shr2
2317 %and3 = shl i32 %or2, 1
2318 %shl3 = and i32 %and3, -1431655766
2319 %and3b = lshr i32 %or2, 1
2320 %shr3 = and i32 %and3b, 1431655765
2321 %or3 = or i32 %shl3, %shr3
2322 %and4 = shl i32 %or3, 2
2323 %shl4 = and i32 %and4, -858993460
2324 %and4b = lshr i32 %or3, 2
2325 %shr4 = and i32 %and4b, 858993459
2326 %or4 = or i32 %shl4, %shr4
2327 ret i32 %or4
2328 }
2330 ; grev1, grev2, grev1, grev2 -> identity
2331 define i64 @grev0_i64(i64 %a) nounwind {
2332 ; RV64I-LABEL: grev0_i64:
2333 ; RV64I: # %bb.0:
2334 ; RV64I-NEXT: lui a1, %hi(.LCPI62_0)
2335 ; RV64I-NEXT: ld a1, %lo(.LCPI62_0)(a1)
2336 ; RV64I-NEXT: lui a2, %hi(.LCPI62_1)
2337 ; RV64I-NEXT: ld a2, %lo(.LCPI62_1)(a2)
2338 ; RV64I-NEXT: slli a3, a0, 1
2339 ; RV64I-NEXT: and a3, a3, a1
2340 ; RV64I-NEXT: srli a0, a0, 1
2341 ; RV64I-NEXT: and a0, a0, a2
2342 ; RV64I-NEXT: or a0, a3, a0
2343 ; RV64I-NEXT: lui a3, %hi(.LCPI62_2)
2344 ; RV64I-NEXT: ld a3, %lo(.LCPI62_2)(a3)
2345 ; RV64I-NEXT: lui a4, %hi(.LCPI62_3)
2346 ; RV64I-NEXT: ld a4, %lo(.LCPI62_3)(a4)
2347 ; RV64I-NEXT: slli a5, a0, 2
2348 ; RV64I-NEXT: and a5, a5, a3
2349 ; RV64I-NEXT: srli a0, a0, 2
2350 ; RV64I-NEXT: and a0, a0, a4
2351 ; RV64I-NEXT: or a0, a5, a0
2352 ; RV64I-NEXT: slli a5, a0, 1
2353 ; RV64I-NEXT: and a1, a5, a1
2354 ; RV64I-NEXT: srli a0, a0, 1
2355 ; RV64I-NEXT: and a0, a0, a2
2356 ; RV64I-NEXT: or a0, a1, a0
2357 ; RV64I-NEXT: slli a1, a0, 2
2358 ; RV64I-NEXT: and a1, a1, a3
2359 ; RV64I-NEXT: srli a0, a0, 2
2360 ; RV64I-NEXT: and a0, a0, a4
2361 ; RV64I-NEXT: or a0, a1, a0
2362 ; RV64I-NEXT: ret
2363 ;
2364 ; RV64ZBP-LABEL: grev0_i64:
2365 ; RV64ZBP: # %bb.0:
2366 ; RV64ZBP-NEXT: ret
2367 %and1 = shl i64 %a, 1
2368 %shl1 = and i64 %and1, -6148914691236517206
2369 %and1b = lshr i64 %a, 1
2370 %shr1 = and i64 %and1b, 6148914691236517205
2371 %or1 = or i64 %shl1, %shr1
2372 %and2 = shl i64 %or1, 2
2373 %shl2 = and i64 %and2, -3689348814741910324
2374 %and2b = lshr i64 %or1, 2
2375 %shr2 = and i64 %and2b, 3689348814741910323
2376 %or2 = or i64 %shl2, %shr2
2377 %and3 = shl i64 %or2, 1
2378 %shl3 = and i64 %and3, -6148914691236517206
2379 %and3b = lshr i64 %or2, 1
2380 %shr3 = and i64 %and3b, 6148914691236517205
2381 %or3 = or i64 %shl3, %shr3
2382 %and4 = shl i64 %or3, 2
2383 %shl4 = and i64 %and4, -3689348814741910324
2384 %and4b = lshr i64 %or3, 2
2385 %shr4 = and i64 %and4b, 3689348814741910323
2386 %or4 = or i64 %shl4, %shr4
2387 ret i64 %or4
2388 }
2390 declare i64 @llvm.fshl.i64(i64, i64, i64)
2391 declare i64 @llvm.fshr.i64(i64, i64, i64)
2393 define i64 @grev32_fshl(i64 %a) nounwind {
2394 ; RV64I-LABEL: grev32_fshl:
2395 ; RV64I: # %bb.0:
2396 ; RV64I-NEXT: srli a1, a0, 32
2397 ; RV64I-NEXT: slli a0, a0, 32
2398 ; RV64I-NEXT: or a0, a0, a1
2399 ; RV64I-NEXT: ret
2400 ;
2401 ; RV64ZBP-LABEL: grev32_fshl:
2402 ; RV64ZBP: # %bb.0:
2403 ; RV64ZBP-NEXT: rori a0, a0, 32
2404 ; RV64ZBP-NEXT: ret
2405 %or = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 32)
2406 ret i64 %or
2407 }
2409 define i64 @grev32_fshr(i64 %a) nounwind {
2410 ; RV64I-LABEL: grev32_fshr:
2411 ; RV64I: # %bb.0:
2412 ; RV64I-NEXT: slli a1, a0, 32
2413 ; RV64I-NEXT: srli a0, a0, 32
2414 ; RV64I-NEXT: or a0, a0, a1
2415 ; RV64I-NEXT: ret
2416 ;
2417 ; RV64ZBP-LABEL: grev32_fshr:
2418 ; RV64ZBP: # %bb.0:
2419 ; RV64ZBP-NEXT: rori a0, a0, 32
2420 ; RV64ZBP-NEXT: ret
2421 %or = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 32)
2422 ret i64 %or
2423 }
2425 declare i16 @llvm.bswap.i16(i16)
2427 define zeroext i16 @bswap_i16(i16 zeroext %a) nounwind {
2428 ; RV64I-LABEL: bswap_i16:
2429 ; RV64I: # %bb.0:
2430 ; RV64I-NEXT: srli a1, a0, 8
2431 ; RV64I-NEXT: slli a0, a0, 8
2432 ; RV64I-NEXT: or a0, a0, a1
2433 ; RV64I-NEXT: slli a0, a0, 48
2434 ; RV64I-NEXT: srli a0, a0, 48
2435 ; RV64I-NEXT: ret
2436 ;
2437 ; RV64ZBP-LABEL: bswap_i16:
2438 ; RV64ZBP: # %bb.0:
2439 ; RV64ZBP-NEXT: rev8.h a0, a0
2440 ; RV64ZBP-NEXT: ret
2441 %1 = tail call i16 @llvm.bswap.i16(i16 %a)
2442 ret i16 %1
2443 }
2445 declare i32 @llvm.bswap.i32(i32)
2447 define signext i32 @bswap_i32(i32 signext %a) nounwind {
2448 ; RV64I-LABEL: bswap_i32:
2449 ; RV64I: # %bb.0:
2450 ; RV64I-NEXT: srli a1, a0, 8
2451 ; RV64I-NEXT: lui a2, 16
2452 ; RV64I-NEXT: addiw a2, a2, -256
2453 ; RV64I-NEXT: and a1, a1, a2
2454 ; RV64I-NEXT: srliw a2, a0, 24
2455 ; RV64I-NEXT: or a1, a1, a2
2456 ; RV64I-NEXT: slli a2, a0, 8
2457 ; RV64I-NEXT: lui a3, 4080
2458 ; RV64I-NEXT: and a2, a2, a3
2459 ; RV64I-NEXT: slliw a0, a0, 24
2460 ; RV64I-NEXT: or a0, a0, a2
2461 ; RV64I-NEXT: or a0, a0, a1
2462 ; RV64I-NEXT: ret
2463 ;
2464 ; RV64ZBP-LABEL: bswap_i32:
2465 ; RV64ZBP: # %bb.0:
2466 ; RV64ZBP-NEXT: greviw a0, a0, 24
2467 ; RV64ZBP-NEXT: ret
2468 %1 = tail call i32 @llvm.bswap.i32(i32 %a)
2469 ret i32 %1
2470 }
2472 ; Similar to bswap_i32 but the result is not sign extended.
2473 define void @bswap_i32_nosext(i32 signext %a, i32* %x) nounwind {
2474 ; RV64I-LABEL: bswap_i32_nosext:
2475 ; RV64I: # %bb.0:
2476 ; RV64I-NEXT: srli a2, a0, 8
2477 ; RV64I-NEXT: lui a3, 16
2478 ; RV64I-NEXT: addiw a3, a3, -256
2479 ; RV64I-NEXT: and a2, a2, a3
2480 ; RV64I-NEXT: srliw a3, a0, 24
2481 ; RV64I-NEXT: or a2, a2, a3
2482 ; RV64I-NEXT: slli a3, a0, 8
2483 ; RV64I-NEXT: lui a4, 4080
2484 ; RV64I-NEXT: and a3, a3, a4
2485 ; RV64I-NEXT: slli a0, a0, 24
2486 ; RV64I-NEXT: or a0, a0, a3
2487 ; RV64I-NEXT: or a0, a0, a2
2488 ; RV64I-NEXT: sw a0, 0(a1)
2489 ; RV64I-NEXT: ret
2490 ;
2491 ; RV64ZBP-LABEL: bswap_i32_nosext:
2492 ; RV64ZBP: # %bb.0:
2493 ; RV64ZBP-NEXT: greviw a0, a0, 24
2494 ; RV64ZBP-NEXT: sw a0, 0(a1)
2495 ; RV64ZBP-NEXT: ret
2496 %1 = tail call i32 @llvm.bswap.i32(i32 %a)
2497 store i32 %1, i32* %x
2498 ret void
2499 }
2501 declare i64 @llvm.bswap.i64(i64)
2503 define i64 @bswap_i64(i64 %a) {
2504 ; RV64I-LABEL: bswap_i64:
2505 ; RV64I: # %bb.0:
2506 ; RV64I-NEXT: srli a1, a0, 24
2507 ; RV64I-NEXT: lui a2, 4080
2508 ; RV64I-NEXT: and a1, a1, a2
2509 ; RV64I-NEXT: srli a2, a0, 8
2510 ; RV64I-NEXT: li a3, 255
2511 ; RV64I-NEXT: slli a4, a3, 24
2512 ; RV64I-NEXT: and a2, a2, a4
2513 ; RV64I-NEXT: or a1, a2, a1
2514 ; RV64I-NEXT: srli a2, a0, 40
2515 ; RV64I-NEXT: lui a4, 16
2516 ; RV64I-NEXT: addiw a4, a4, -256
2517 ; RV64I-NEXT: and a2, a2, a4
2518 ; RV64I-NEXT: srli a4, a0, 56
2519 ; RV64I-NEXT: or a2, a2, a4
2520 ; RV64I-NEXT: or a1, a1, a2
2521 ; RV64I-NEXT: slli a2, a0, 24
2522 ; RV64I-NEXT: slli a4, a3, 40
2523 ; RV64I-NEXT: and a2, a2, a4
2524 ; RV64I-NEXT: srliw a4, a0, 24
2525 ; RV64I-NEXT: slli a4, a4, 32
2526 ; RV64I-NEXT: or a2, a2, a4
2527 ; RV64I-NEXT: slli a4, a0, 40
2528 ; RV64I-NEXT: slli a3, a3, 48
2529 ; RV64I-NEXT: and a3, a4, a3
2530 ; RV64I-NEXT: slli a0, a0, 56
2531 ; RV64I-NEXT: or a0, a0, a3
2532 ; RV64I-NEXT: or a0, a0, a2
2533 ; RV64I-NEXT: or a0, a0, a1
2534 ; RV64I-NEXT: ret
2535 ;
2536 ; RV64ZBP-LABEL: bswap_i64:
2537 ; RV64ZBP: # %bb.0:
2538 ; RV64ZBP-NEXT: rev8 a0, a0
2539 ; RV64ZBP-NEXT: ret
2540 %1 = call i64 @llvm.bswap.i64(i64 %a)
2541 ret i64 %1
2542 }
2544 declare i8 @llvm.bitreverse.i8(i8)
2546 define zeroext i8 @bitreverse_i8(i8 zeroext %a) nounwind {
2547 ; RV64I-LABEL: bitreverse_i8:
2548 ; RV64I: # %bb.0:
2549 ; RV64I-NEXT: srli a1, a0, 4
2550 ; RV64I-NEXT: andi a0, a0, 15
2551 ; RV64I-NEXT: slli a0, a0, 4
2552 ; RV64I-NEXT: or a0, a1, a0
2553 ; RV64I-NEXT: andi a1, a0, 51
2554 ; RV64I-NEXT: slli a1, a1, 2
2555 ; RV64I-NEXT: srli a0, a0, 2
2556 ; RV64I-NEXT: andi a0, a0, 51
2557 ; RV64I-NEXT: or a0, a0, a1
2558 ; RV64I-NEXT: andi a1, a0, 85
2559 ; RV64I-NEXT: slli a1, a1, 1
2560 ; RV64I-NEXT: srli a0, a0, 1
2561 ; RV64I-NEXT: andi a0, a0, 85
2562 ; RV64I-NEXT: or a0, a0, a1
2563 ; RV64I-NEXT: ret
2564 ;
2565 ; RV64ZBP-LABEL: bitreverse_i8:
2566 ; RV64ZBP: # %bb.0:
2567 ; RV64ZBP-NEXT: rev.b a0, a0
2568 ; RV64ZBP-NEXT: ret
2569 %1 = tail call i8 @llvm.bitreverse.i8(i8 %a)
2570 ret i8 %1
2571 }
2573 declare i16 @llvm.bitreverse.i16(i16)
2575 define zeroext i16 @bitreverse_i16(i16 zeroext %a) nounwind {
2576 ; RV64I-LABEL: bitreverse_i16:
2577 ; RV64I: # %bb.0:
2578 ; RV64I-NEXT: srli a1, a0, 8
2579 ; RV64I-NEXT: slli a0, a0, 8
2580 ; RV64I-NEXT: or a0, a0, a1
2581 ; RV64I-NEXT: srli a1, a0, 4
2582 ; RV64I-NEXT: lui a2, 1
2583 ; RV64I-NEXT: addiw a2, a2, -241
2584 ; RV64I-NEXT: and a1, a1, a2
2585 ; RV64I-NEXT: and a0, a0, a2
2586 ; RV64I-NEXT: slli a0, a0, 4
2587 ; RV64I-NEXT: or a0, a1, a0
2588 ; RV64I-NEXT: srli a1, a0, 2
2589 ; RV64I-NEXT: lui a2, 3
2590 ; RV64I-NEXT: addiw a2, a2, 819
2591 ; RV64I-NEXT: and a1, a1, a2
2592 ; RV64I-NEXT: and a0, a0, a2
2593 ; RV64I-NEXT: slli a0, a0, 2
2594 ; RV64I-NEXT: or a0, a1, a0
2595 ; RV64I-NEXT: srli a1, a0, 1
2596 ; RV64I-NEXT: lui a2, 5
2597 ; RV64I-NEXT: addiw a2, a2, 1365
2598 ; RV64I-NEXT: and a1, a1, a2
2599 ; RV64I-NEXT: and a0, a0, a2
2600 ; RV64I-NEXT: slli a0, a0, 1
2601 ; RV64I-NEXT: or a0, a1, a0
2602 ; RV64I-NEXT: ret
2603 ;
2604 ; RV64ZBP-LABEL: bitreverse_i16:
2605 ; RV64ZBP: # %bb.0:
2606 ; RV64ZBP-NEXT: rev.h a0, a0
2607 ; RV64ZBP-NEXT: ret
2608 %1 = tail call i16 @llvm.bitreverse.i16(i16 %a)
2609 ret i16 %1
2610 }
2612 declare i32 @llvm.bitreverse.i32(i32)
2614 define signext i32 @bitreverse_i32(i32 signext %a) nounwind {
2615 ; RV64I-LABEL: bitreverse_i32:
2616 ; RV64I: # %bb.0:
2617 ; RV64I-NEXT: srli a1, a0, 8
2618 ; RV64I-NEXT: lui a2, 16
2619 ; RV64I-NEXT: addiw a2, a2, -256
2620 ; RV64I-NEXT: and a1, a1, a2
2621 ; RV64I-NEXT: srliw a2, a0, 24
2622 ; RV64I-NEXT: or a1, a1, a2
2623 ; RV64I-NEXT: slli a2, a0, 8
2624 ; RV64I-NEXT: lui a3, 4080
2625 ; RV64I-NEXT: and a2, a2, a3
2626 ; RV64I-NEXT: slliw a0, a0, 24
2627 ; RV64I-NEXT: or a0, a0, a2
2628 ; RV64I-NEXT: or a0, a0, a1
2629 ; RV64I-NEXT: srli a1, a0, 4
2630 ; RV64I-NEXT: lui a2, 61681
2631 ; RV64I-NEXT: addiw a2, a2, -241
2632 ; RV64I-NEXT: and a1, a1, a2
2633 ; RV64I-NEXT: and a0, a0, a2
2634 ; RV64I-NEXT: slliw a0, a0, 4
2635 ; RV64I-NEXT: or a0, a1, a0
2636 ; RV64I-NEXT: srli a1, a0, 2
2637 ; RV64I-NEXT: lui a2, 209715
2638 ; RV64I-NEXT: addiw a2, a2, 819
2639 ; RV64I-NEXT: and a1, a1, a2
2640 ; RV64I-NEXT: and a0, a0, a2
2641 ; RV64I-NEXT: slliw a0, a0, 2
2642 ; RV64I-NEXT: or a0, a1, a0
2643 ; RV64I-NEXT: srli a1, a0, 1
2644 ; RV64I-NEXT: lui a2, 349525
2645 ; RV64I-NEXT: addiw a2, a2, 1365
2646 ; RV64I-NEXT: and a1, a1, a2
2647 ; RV64I-NEXT: and a0, a0, a2
2648 ; RV64I-NEXT: slliw a0, a0, 1
2649 ; RV64I-NEXT: or a0, a1, a0
2650 ; RV64I-NEXT: ret
2651 ;
2652 ; RV64ZBP-LABEL: bitreverse_i32:
2653 ; RV64ZBP: # %bb.0:
2654 ; RV64ZBP-NEXT: greviw a0, a0, 31
2655 ; RV64ZBP-NEXT: ret
2656 %1 = tail call i32 @llvm.bitreverse.i32(i32 %a)
2657 ret i32 %1
2658 }
2660 ; Similar to bitreverse_i32 but the result is not sign extended.
2661 define void @bitreverse_i32_nosext(i32 signext %a, i32* %x) nounwind {
2662 ; RV64I-LABEL: bitreverse_i32_nosext:
2663 ; RV64I: # %bb.0:
2664 ; RV64I-NEXT: srli a2, a0, 8
2665 ; RV64I-NEXT: lui a3, 16
2666 ; RV64I-NEXT: addiw a3, a3, -256
2667 ; RV64I-NEXT: and a2, a2, a3
2668 ; RV64I-NEXT: srliw a3, a0, 24
2669 ; RV64I-NEXT: or a2, a2, a3
2670 ; RV64I-NEXT: slli a3, a0, 8
2671 ; RV64I-NEXT: lui a4, 4080
2672 ; RV64I-NEXT: and a3, a3, a4
2673 ; RV64I-NEXT: slliw a0, a0, 24
2674 ; RV64I-NEXT: or a0, a0, a3
2675 ; RV64I-NEXT: or a0, a0, a2
2676 ; RV64I-NEXT: srli a2, a0, 4
2677 ; RV64I-NEXT: lui a3, 61681
2678 ; RV64I-NEXT: addiw a3, a3, -241
2679 ; RV64I-NEXT: and a2, a2, a3
2680 ; RV64I-NEXT: and a0, a0, a3
2681 ; RV64I-NEXT: slliw a0, a0, 4
2682 ; RV64I-NEXT: or a0, a2, a0
2683 ; RV64I-NEXT: srli a2, a0, 2
2684 ; RV64I-NEXT: lui a3, 209715
2685 ; RV64I-NEXT: addiw a3, a3, 819
2686 ; RV64I-NEXT: and a2, a2, a3
2687 ; RV64I-NEXT: and a0, a0, a3
2688 ; RV64I-NEXT: slliw a0, a0, 2
2689 ; RV64I-NEXT: or a0, a2, a0
2690 ; RV64I-NEXT: srli a2, a0, 1
2691 ; RV64I-NEXT: lui a3, 349525
2692 ; RV64I-NEXT: addiw a3, a3, 1365
2693 ; RV64I-NEXT: and a2, a2, a3
2694 ; RV64I-NEXT: and a0, a0, a3
2695 ; RV64I-NEXT: slli a0, a0, 1
2696 ; RV64I-NEXT: or a0, a2, a0
2697 ; RV64I-NEXT: sw a0, 0(a1)
2698 ; RV64I-NEXT: ret
2699 ;
2700 ; RV64ZBP-LABEL: bitreverse_i32_nosext:
2701 ; RV64ZBP: # %bb.0:
2702 ; RV64ZBP-NEXT: greviw a0, a0, 31
2703 ; RV64ZBP-NEXT: sw a0, 0(a1)
2704 ; RV64ZBP-NEXT: ret
2705 %1 = tail call i32 @llvm.bitreverse.i32(i32 %a)
2706 store i32 %1, i32* %x
2707 ret void
2708 }
2710 declare i64 @llvm.bitreverse.i64(i64)
2712 define i64 @bitreverse_i64(i64 %a) nounwind {
2713 ; RV64I-LABEL: bitreverse_i64:
2714 ; RV64I: # %bb.0:
2715 ; RV64I-NEXT: srli a1, a0, 24
2716 ; RV64I-NEXT: lui a2, 4080
2717 ; RV64I-NEXT: and a1, a1, a2
2718 ; RV64I-NEXT: srli a2, a0, 8
2719 ; RV64I-NEXT: li a3, 255
2720 ; RV64I-NEXT: slli a4, a3, 24
2721 ; RV64I-NEXT: and a2, a2, a4
2722 ; RV64I-NEXT: or a1, a2, a1
2723 ; RV64I-NEXT: srli a2, a0, 40
2724 ; RV64I-NEXT: lui a4, 16
2725 ; RV64I-NEXT: addiw a4, a4, -256
2726 ; RV64I-NEXT: and a2, a2, a4
2727 ; RV64I-NEXT: srli a4, a0, 56
2728 ; RV64I-NEXT: or a2, a2, a4
2729 ; RV64I-NEXT: or a1, a1, a2
2730 ; RV64I-NEXT: slli a2, a0, 24
2731 ; RV64I-NEXT: slli a4, a3, 40
2732 ; RV64I-NEXT: and a2, a2, a4
2733 ; RV64I-NEXT: srliw a4, a0, 24
2734 ; RV64I-NEXT: slli a4, a4, 32
2735 ; RV64I-NEXT: or a2, a2, a4
2736 ; RV64I-NEXT: slli a4, a0, 40
2737 ; RV64I-NEXT: slli a3, a3, 48
2738 ; RV64I-NEXT: and a3, a4, a3
2739 ; RV64I-NEXT: slli a0, a0, 56
2740 ; RV64I-NEXT: or a0, a0, a3
2741 ; RV64I-NEXT: lui a3, %hi(.LCPI73_0)
2742 ; RV64I-NEXT: ld a3, %lo(.LCPI73_0)(a3)
2743 ; RV64I-NEXT: or a0, a0, a2
2744 ; RV64I-NEXT: or a0, a0, a1
2745 ; RV64I-NEXT: srli a1, a0, 4
2746 ; RV64I-NEXT: and a1, a1, a3
2747 ; RV64I-NEXT: and a0, a0, a3
2748 ; RV64I-NEXT: lui a2, %hi(.LCPI73_1)
2749 ; RV64I-NEXT: ld a2, %lo(.LCPI73_1)(a2)
2750 ; RV64I-NEXT: slli a0, a0, 4
2751 ; RV64I-NEXT: or a0, a1, a0
2752 ; RV64I-NEXT: srli a1, a0, 2
2753 ; RV64I-NEXT: and a1, a1, a2
2754 ; RV64I-NEXT: and a0, a0, a2
2755 ; RV64I-NEXT: lui a2, %hi(.LCPI73_2)
2756 ; RV64I-NEXT: ld a2, %lo(.LCPI73_2)(a2)
2757 ; RV64I-NEXT: slli a0, a0, 2
2758 ; RV64I-NEXT: or a0, a1, a0
2759 ; RV64I-NEXT: srli a1, a0, 1
2760 ; RV64I-NEXT: and a1, a1, a2
2761 ; RV64I-NEXT: and a0, a0, a2
2762 ; RV64I-NEXT: slli a0, a0, 1
2763 ; RV64I-NEXT: or a0, a1, a0
2764 ; RV64I-NEXT: ret
2765 ;
2766 ; RV64ZBP-LABEL: bitreverse_i64:
2767 ; RV64ZBP: # %bb.0:
2768 ; RV64ZBP-NEXT: rev a0, a0
2769 ; RV64ZBP-NEXT: ret
2770 %1 = call i64 @llvm.bitreverse.i64(i64 %a)
2771 ret i64 %1
2772 }
2774 define i32 @bswap_rotr_i32(i32 %a) {
2775 ; RV64I-LABEL: bswap_rotr_i32:
2776 ; RV64I: # %bb.0:
2777 ; RV64I-NEXT: slli a1, a0, 8
2778 ; RV64I-NEXT: lui a2, 4080
2779 ; RV64I-NEXT: and a1, a1, a2
2780 ; RV64I-NEXT: slli a2, a0, 24
2781 ; RV64I-NEXT: or a1, a2, a1
2782 ; RV64I-NEXT: srliw a2, a0, 24
2783 ; RV64I-NEXT: srli a0, a0, 16
2784 ; RV64I-NEXT: slli a0, a0, 8
2785 ; RV64I-NEXT: or a0, a0, a2
2786 ; RV64I-NEXT: slliw a0, a0, 16
2787 ; RV64I-NEXT: srliw a1, a1, 16
2788 ; RV64I-NEXT: or a0, a1, a0
2789 ; RV64I-NEXT: ret
2790 ;
2791 ; RV64ZBP-LABEL: bswap_rotr_i32:
2792 ; RV64ZBP: # %bb.0:
2793 ; RV64ZBP-NEXT: greviw a0, a0, 8
2794 ; RV64ZBP-NEXT: ret
2795 %1 = call i32 @llvm.bswap.i32(i32 %a)
2796 %2 = call i32 @llvm.fshr.i32(i32 %1, i32 %1, i32 16)
2797 ret i32 %2
2798 }
2800 define i32 @bswap_rotl_i32(i32 %a) {
2801 ; RV64I-LABEL: bswap_rotl_i32:
2802 ; RV64I: # %bb.0:
2803 ; RV64I-NEXT: srliw a1, a0, 24
2804 ; RV64I-NEXT: srli a2, a0, 16
2805 ; RV64I-NEXT: slli a2, a2, 8
2806 ; RV64I-NEXT: or a1, a2, a1
2807 ; RV64I-NEXT: slli a2, a0, 8
2808 ; RV64I-NEXT: lui a3, 4080
2809 ; RV64I-NEXT: and a2, a2, a3
2810 ; RV64I-NEXT: slli a0, a0, 24
2811 ; RV64I-NEXT: or a0, a0, a2
2812 ; RV64I-NEXT: srliw a0, a0, 16
2813 ; RV64I-NEXT: slliw a1, a1, 16
2814 ; RV64I-NEXT: or a0, a1, a0
2815 ; RV64I-NEXT: ret
2816 ;
2817 ; RV64ZBP-LABEL: bswap_rotl_i32:
2818 ; RV64ZBP: # %bb.0:
2819 ; RV64ZBP-NEXT: greviw a0, a0, 8
2820 ; RV64ZBP-NEXT: ret
2821 %1 = call i32 @llvm.bswap.i32(i32 %a)
2822 %2 = call i32 @llvm.fshl.i32(i32 %1, i32 %1, i32 16)
2823 ret i32 %2
2824 }
2826 define i64 @bswap_rotr_i64(i64 %a) {
2827 ; RV64I-LABEL: bswap_rotr_i64:
2828 ; RV64I: # %bb.0:
2829 ; RV64I-NEXT: slli a1, a0, 24
2830 ; RV64I-NEXT: li a2, 255
2831 ; RV64I-NEXT: slli a3, a2, 40
2832 ; RV64I-NEXT: and a1, a1, a3
2833 ; RV64I-NEXT: srliw a3, a0, 24
2834 ; RV64I-NEXT: slli a3, a3, 32
2835 ; RV64I-NEXT: or a1, a1, a3
2836 ; RV64I-NEXT: slli a3, a0, 40
2837 ; RV64I-NEXT: slli a2, a2, 48
2838 ; RV64I-NEXT: and a2, a3, a2
2839 ; RV64I-NEXT: slli a3, a0, 56
2840 ; RV64I-NEXT: or a2, a3, a2
2841 ; RV64I-NEXT: or a1, a2, a1
2842 ; RV64I-NEXT: srli a2, a0, 40
2843 ; RV64I-NEXT: lui a3, 16
2844 ; RV64I-NEXT: addiw a3, a3, -256
2845 ; RV64I-NEXT: and a2, a2, a3
2846 ; RV64I-NEXT: srli a3, a0, 56
2847 ; RV64I-NEXT: or a2, a2, a3
2848 ; RV64I-NEXT: srli a3, a0, 24
2849 ; RV64I-NEXT: lui a4, 4080
2850 ; RV64I-NEXT: and a3, a3, a4
2851 ; RV64I-NEXT: srli a0, a0, 32
2852 ; RV64I-NEXT: slli a0, a0, 24
2853 ; RV64I-NEXT: or a0, a0, a3
2854 ; RV64I-NEXT: or a0, a0, a2
2855 ; RV64I-NEXT: slli a0, a0, 32
2856 ; RV64I-NEXT: srli a1, a1, 32
2857 ; RV64I-NEXT: or a0, a1, a0
2858 ; RV64I-NEXT: ret
2859 ;
2860 ; RV64ZBP-LABEL: bswap_rotr_i64:
2861 ; RV64ZBP: # %bb.0:
2862 ; RV64ZBP-NEXT: rev8.w a0, a0
2863 ; RV64ZBP-NEXT: ret
2864 %1 = call i64 @llvm.bswap.i64(i64 %a)
2865 %2 = call i64 @llvm.fshr.i64(i64 %1, i64 %1, i64 32)
2866 ret i64 %2
2867 }
2869 define i64 @bswap_rotl_i64(i64 %a) {
2870 ; RV64I-LABEL: bswap_rotl_i64:
2871 ; RV64I: # %bb.0:
2872 ; RV64I-NEXT: srli a1, a0, 40
2873 ; RV64I-NEXT: lui a2, 16
2874 ; RV64I-NEXT: addiw a2, a2, -256
2875 ; RV64I-NEXT: and a1, a1, a2
2876 ; RV64I-NEXT: srli a2, a0, 56
2877 ; RV64I-NEXT: or a1, a1, a2
2878 ; RV64I-NEXT: srli a2, a0, 24
2879 ; RV64I-NEXT: lui a3, 4080
2880 ; RV64I-NEXT: and a2, a2, a3
2881 ; RV64I-NEXT: srli a3, a0, 32
2882 ; RV64I-NEXT: slli a3, a3, 24
2883 ; RV64I-NEXT: or a2, a3, a2
2884 ; RV64I-NEXT: or a1, a2, a1
2885 ; RV64I-NEXT: slli a2, a0, 24
2886 ; RV64I-NEXT: li a3, 255
2887 ; RV64I-NEXT: slli a4, a3, 40
2888 ; RV64I-NEXT: and a2, a2, a4
2889 ; RV64I-NEXT: srliw a4, a0, 24
2890 ; RV64I-NEXT: slli a4, a4, 32
2891 ; RV64I-NEXT: or a2, a2, a4
2892 ; RV64I-NEXT: slli a4, a0, 40
2893 ; RV64I-NEXT: slli a3, a3, 48
2894 ; RV64I-NEXT: and a3, a4, a3
2895 ; RV64I-NEXT: slli a0, a0, 56
2896 ; RV64I-NEXT: or a0, a0, a3
2897 ; RV64I-NEXT: or a0, a0, a2
2898 ; RV64I-NEXT: srli a0, a0, 32
2899 ; RV64I-NEXT: slli a1, a1, 32
2900 ; RV64I-NEXT: or a0, a1, a0
2901 ; RV64I-NEXT: ret
2902 ;
2903 ; RV64ZBP-LABEL: bswap_rotl_i64:
2904 ; RV64ZBP: # %bb.0:
2905 ; RV64ZBP-NEXT: rev8.w a0, a0
2906 ; RV64ZBP-NEXT: ret
2907 %1 = call i64 @llvm.bswap.i64(i64 %a)
2908 %2 = call i64 @llvm.fshl.i64(i64 %1, i64 %1, i64 32)
2909 ret i64 %2
2910 }
2912 define i32 @bitreverse_bswap_i32(i32 %a) {
2913 ; RV64I-LABEL: bitreverse_bswap_i32:
2914 ; RV64I: # %bb.0:
2915 ; RV64I-NEXT: srli a1, a0, 4
2916 ; RV64I-NEXT: lui a2, 61681
2917 ; RV64I-NEXT: addiw a2, a2, -241
2918 ; RV64I-NEXT: and a1, a1, a2
2919 ; RV64I-NEXT: and a0, a0, a2
2920 ; RV64I-NEXT: slliw a0, a0, 4
2921 ; RV64I-NEXT: or a0, a1, a0
2922 ; RV64I-NEXT: srli a1, a0, 2
2923 ; RV64I-NEXT: lui a2, 209715
2924 ; RV64I-NEXT: addiw a2, a2, 819
2925 ; RV64I-NEXT: and a1, a1, a2
2926 ; RV64I-NEXT: and a0, a0, a2
2927 ; RV64I-NEXT: slliw a0, a0, 2
2928 ; RV64I-NEXT: or a0, a1, a0
2929 ; RV64I-NEXT: srli a1, a0, 1
2930 ; RV64I-NEXT: lui a2, 349525
2931 ; RV64I-NEXT: addiw a2, a2, 1365
2932 ; RV64I-NEXT: and a1, a1, a2
2933 ; RV64I-NEXT: and a0, a0, a2
2934 ; RV64I-NEXT: slliw a0, a0, 1
2935 ; RV64I-NEXT: or a0, a1, a0
2936 ; RV64I-NEXT: ret
2937 ;
2938 ; RV64ZBP-LABEL: bitreverse_bswap_i32:
2939 ; RV64ZBP: # %bb.0:
2940 ; RV64ZBP-NEXT: rev.b a0, a0
2941 ; RV64ZBP-NEXT: ret
2942 %1 = call i32 @llvm.bitreverse.i32(i32 %a)
2943 %2 = call i32 @llvm.bswap.i32(i32 %1)
2944 ret i32 %2
2945 }
2947 define i64 @bitreverse_bswap_i64(i64 %a) {
2948 ; RV64I-LABEL: bitreverse_bswap_i64:
2949 ; RV64I: # %bb.0:
2950 ; RV64I-NEXT: lui a1, %hi(.LCPI79_0)
2951 ; RV64I-NEXT: ld a1, %lo(.LCPI79_0)(a1)
2952 ; RV64I-NEXT: srli a2, a0, 4
2953 ; RV64I-NEXT: and a2, a2, a1
2954 ; RV64I-NEXT: and a0, a0, a1
2955 ; RV64I-NEXT: lui a1, %hi(.LCPI79_1)
2956 ; RV64I-NEXT: ld a1, %lo(.LCPI79_1)(a1)
2957 ; RV64I-NEXT: slli a0, a0, 4
2958 ; RV64I-NEXT: or a0, a2, a0
2959 ; RV64I-NEXT: srli a2, a0, 2
2960 ; RV64I-NEXT: and a2, a2, a1
2961 ; RV64I-NEXT: and a0, a0, a1
2962 ; RV64I-NEXT: lui a1, %hi(.LCPI79_2)
2963 ; RV64I-NEXT: ld a1, %lo(.LCPI79_2)(a1)
2964 ; RV64I-NEXT: slli a0, a0, 2
2965 ; RV64I-NEXT: or a0, a2, a0
2966 ; RV64I-NEXT: srli a2, a0, 1
2967 ; RV64I-NEXT: and a2, a2, a1
2968 ; RV64I-NEXT: and a0, a0, a1
2969 ; RV64I-NEXT: slli a0, a0, 1
2970 ; RV64I-NEXT: or a0, a2, a0
2971 ; RV64I-NEXT: ret
2972 ;
2973 ; RV64ZBP-LABEL: bitreverse_bswap_i64:
2974 ; RV64ZBP: # %bb.0:
2975 ; RV64ZBP-NEXT: rev.b a0, a0
2976 ; RV64ZBP-NEXT: ret
2977 %1 = call i64 @llvm.bitreverse.i64(i64 %a)
2978 %2 = call i64 @llvm.bswap.i64(i64 %1)
2979 ret i64 %2
2980 }
2982 define signext i32 @shfl1_i32(i32 signext %a, i32 signext %b) nounwind {
2983 ; RV64I-LABEL: shfl1_i32:
2984 ; RV64I: # %bb.0:
2985 ; RV64I-NEXT: lui a1, 629146
2986 ; RV64I-NEXT: addiw a1, a1, -1639
2987 ; RV64I-NEXT: and a1, a0, a1
2988 ; RV64I-NEXT: slli a2, a0, 1
2989 ; RV64I-NEXT: lui a3, 279620
2990 ; RV64I-NEXT: addiw a3, a3, 1092
2991 ; RV64I-NEXT: and a2, a2, a3
2992 ; RV64I-NEXT: or a1, a2, a1
2993 ; RV64I-NEXT: srli a0, a0, 1
2994 ; RV64I-NEXT: lui a2, 139810
2995 ; RV64I-NEXT: addiw a2, a2, 546
2996 ; RV64I-NEXT: and a0, a0, a2
2997 ; RV64I-NEXT: or a0, a1, a0
2998 ; RV64I-NEXT: ret
2999 ;
3000 ; RV64ZBP-LABEL: shfl1_i32:
3001 ; RV64ZBP: # %bb.0:
3002 ; RV64ZBP-NEXT: zip.n a0, a0
3003 ; RV64ZBP-NEXT: ret
3004 %and = and i32 %a, -1717986919
3005 %shl = shl i32 %a, 1
3006 %and1 = and i32 %shl, 1145324612
3007 %or = or i32 %and1, %and
3008 %shr = lshr i32 %a, 1
3009 %and2 = and i32 %shr, 572662306
3010 %or3 = or i32 %or, %and2
3011 ret i32 %or3
3012 }
3014 define i64 @shfl1_i64(i64 %a, i64 %b) nounwind {
3015 ; RV64I-LABEL: shfl1_i64:
3016 ; RV64I: # %bb.0:
3017 ; RV64I-NEXT: lui a1, %hi(.LCPI81_1)
3018 ; RV64I-NEXT: ld a1, %lo(.LCPI81_1)(a1)
3019 ; RV64I-NEXT: lui a2, %hi(.LCPI81_0)
3020 ; RV64I-NEXT: ld a2, %lo(.LCPI81_0)(a2)
3021 ; RV64I-NEXT: slli a3, a0, 1
3022 ; RV64I-NEXT: and a1, a3, a1
3023 ; RV64I-NEXT: lui a3, %hi(.LCPI81_2)
3024 ; RV64I-NEXT: ld a3, %lo(.LCPI81_2)(a3)
3025 ; RV64I-NEXT: and a2, a0, a2
3026 ; RV64I-NEXT: or a1, a2, a1
3027 ; RV64I-NEXT: srli a0, a0, 1
3028 ; RV64I-NEXT: and a0, a0, a3
3029 ; RV64I-NEXT: or a0, a1, a0
3030 ; RV64I-NEXT: ret
3031 ;
3032 ; RV64ZBP-LABEL: shfl1_i64:
3033 ; RV64ZBP: # %bb.0:
3034 ; RV64ZBP-NEXT: zip.n a0, a0
3035 ; RV64ZBP-NEXT: ret
3036 %and = and i64 %a, -7378697629483820647
3037 %shl = shl i64 %a, 1
3038 %and1 = and i64 %shl, 4919131752989213764
3039 %or = or i64 %and, %and1
3040 %shr = lshr i64 %a, 1
3041 %and2 = and i64 %shr, 2459565876494606882
3042 %or3 = or i64 %or, %and2
3043 ret i64 %or3
3044 }
3046 define signext i32 @shfl2_i32(i32 signext %a, i32 signext %b) nounwind {
3047 ; RV64I-LABEL: shfl2_i32:
3048 ; RV64I: # %bb.0:
3049 ; RV64I-NEXT: lui a1, 801852
3050 ; RV64I-NEXT: addiw a1, a1, 963
3051 ; RV64I-NEXT: and a1, a0, a1
3052 ; RV64I-NEXT: slli a2, a0, 2
3053 ; RV64I-NEXT: lui a3, 197379
3054 ; RV64I-NEXT: addiw a3, a3, 48
3055 ; RV64I-NEXT: and a2, a2, a3
3056 ; RV64I-NEXT: or a1, a2, a1
3057 ; RV64I-NEXT: srli a0, a0, 2
3058 ; RV64I-NEXT: lui a2, 49345
3059 ; RV64I-NEXT: addiw a2, a2, -1012
3060 ; RV64I-NEXT: and a0, a0, a2
3061 ; RV64I-NEXT: or a0, a0, a1
3062 ; RV64I-NEXT: ret
3063 ;
3064 ; RV64ZBP-LABEL: shfl2_i32:
3065 ; RV64ZBP: # %bb.0:
3066 ; RV64ZBP-NEXT: zip2.b a0, a0
3067 ; RV64ZBP-NEXT: ret
3068 %and = and i32 %a, -1010580541
3069 %shl = shl i32 %a, 2
3070 %and1 = and i32 %shl, 808464432
3071 %or = or i32 %and1, %and
3072 %shr = lshr i32 %a, 2
3073 %and2 = and i32 %shr, 202116108
3074 %or3 = or i32 %and2, %or
3075 ret i32 %or3
3076 }
3078 define i64 @shfl2_i64(i64 %a, i64 %b) nounwind {
3079 ; RV64I-LABEL: shfl2_i64:
3080 ; RV64I: # %bb.0:
3081 ; RV64I-NEXT: lui a1, %hi(.LCPI83_1)
3082 ; RV64I-NEXT: ld a1, %lo(.LCPI83_1)(a1)
3083 ; RV64I-NEXT: lui a2, %hi(.LCPI83_0)
3084 ; RV64I-NEXT: ld a2, %lo(.LCPI83_0)(a2)
3085 ; RV64I-NEXT: slli a3, a0, 2
3086 ; RV64I-NEXT: and a1, a3, a1
3087 ; RV64I-NEXT: lui a3, %hi(.LCPI83_2)
3088 ; RV64I-NEXT: ld a3, %lo(.LCPI83_2)(a3)
3089 ; RV64I-NEXT: and a2, a0, a2
3090 ; RV64I-NEXT: or a1, a2, a1
3091 ; RV64I-NEXT: srli a0, a0, 2
3092 ; RV64I-NEXT: and a0, a0, a3
3093 ; RV64I-NEXT: or a0, a0, a1
3094 ; RV64I-NEXT: ret
3095 ;
3096 ; RV64ZBP-LABEL: shfl2_i64:
3097 ; RV64ZBP: # %bb.0:
3098 ; RV64ZBP-NEXT: zip2.b a0, a0
3099 ; RV64ZBP-NEXT: ret
3100 %and = and i64 %a, -4340410370284600381
3101 %shl = shl i64 %a, 2
3102 %and1 = and i64 %shl, 3472328296227680304
3103 %or = or i64 %and, %and1
3104 %shr = lshr i64 %a, 2
3105 %and2 = and i64 %shr, 868082074056920076
3106 %or3 = or i64 %and2, %or
3107 ret i64 %or3
3108 }
3110 define signext i32 @shfl4_i32(i32 signext %a, i32 signext %b) nounwind {
3111 ; RV64I-LABEL: shfl4_i32:
3112 ; RV64I: # %bb.0:
3113 ; RV64I-NEXT: lui a1, 983295
3114 ; RV64I-NEXT: addiw a1, a1, 15
3115 ; RV64I-NEXT: and a1, a0, a1
3116 ; RV64I-NEXT: slli a2, a0, 4
3117 ; RV64I-NEXT: lui a3, 61441
3118 ; RV64I-NEXT: addiw a3, a3, -256
3119 ; RV64I-NEXT: and a2, a2, a3
3120 ; RV64I-NEXT: srli a0, a0, 4
3121 ; RV64I-NEXT: lui a3, 3840
3122 ; RV64I-NEXT: addiw a3, a3, 240
3123 ; RV64I-NEXT: and a0, a0, a3
3124 ; RV64I-NEXT: or a0, a0, a1
3125 ; RV64I-NEXT: or a0, a0, a2
3126 ; RV64I-NEXT: ret
3127 ;
3128 ; RV64ZBP-LABEL: shfl4_i32:
3129 ; RV64ZBP: # %bb.0:
3130 ; RV64ZBP-NEXT: zip4.h a0, a0
3131 ; RV64ZBP-NEXT: ret
3132 %and = and i32 %a, -267390961
3133 %shl = shl i32 %a, 4
3134 %and1 = and i32 %shl, 251662080
3135 %shr = lshr i32 %a, 4
3136 %and2 = and i32 %shr, 15728880
3137 %or = or i32 %and2, %and
3138 %or3 = or i32 %or, %and1
3139 ret i32 %or3
3140 }
3142 define i64 @shfl4_i64(i64 %a, i64 %b) nounwind {
3143 ; RV64I-LABEL: shfl4_i64:
3144 ; RV64I: # %bb.0:
3145 ; RV64I-NEXT: lui a1, %hi(.LCPI85_0)
3146 ; RV64I-NEXT: ld a1, %lo(.LCPI85_0)(a1)
3147 ; RV64I-NEXT: lui a2, %hi(.LCPI85_1)
3148 ; RV64I-NEXT: ld a2, %lo(.LCPI85_1)(a2)
3149 ; RV64I-NEXT: slli a3, a0, 4
3150 ; RV64I-NEXT: lui a4, %hi(.LCPI85_2)
3151 ; RV64I-NEXT: ld a4, %lo(.LCPI85_2)(a4)
3152 ; RV64I-NEXT: and a2, a3, a2
3153 ; RV64I-NEXT: and a1, a0, a1
3154 ; RV64I-NEXT: srli a0, a0, 4
3155 ; RV64I-NEXT: and a0, a0, a4
3156 ; RV64I-NEXT: or a0, a2, a0
3157 ; RV64I-NEXT: or a0, a0, a1
3158 ; RV64I-NEXT: ret
3159 ;
3160 ; RV64ZBP-LABEL: shfl4_i64:
3161 ; RV64ZBP: # %bb.0:
3162 ; RV64ZBP-NEXT: zip4.h a0, a0
3163 ; RV64ZBP-NEXT: ret
3164 %and = and i64 %a, -1148435428713435121
3165 %shl = shl i64 %a, 4
3166 %and1 = and i64 %shl, 1080880403494997760
3167 %shr = lshr i64 %a, 4
3168 %and2 = and i64 %shr, 67555025218437360
3169 %or = or i64 %and1, %and2
3170 %or3 = or i64 %or, %and
3171 ret i64 %or3
3172 }
3174 define signext i32 @shfl8_i32(i32 signext %a, i32 signext %b) nounwind {
3175 ; RV64I-LABEL: shfl8_i32:
3176 ; RV64I: # %bb.0:
3177 ; RV64I-NEXT: lui a1, 1044480
3178 ; RV64I-NEXT: addiw a1, a1, 255
3179 ; RV64I-NEXT: and a1, a0, a1
3180 ; RV64I-NEXT: slli a2, a0, 8
3181 ; RV64I-NEXT: lui a3, 4080
3182 ; RV64I-NEXT: and a2, a2, a3
3183 ; RV64I-NEXT: srli a0, a0, 8
3184 ; RV64I-NEXT: lui a3, 16
3185 ; RV64I-NEXT: addiw a3, a3, -256
3186 ; RV64I-NEXT: and a0, a0, a3
3187 ; RV64I-NEXT: or a0, a1, a0
3188 ; RV64I-NEXT: or a0, a0, a2
3189 ; RV64I-NEXT: ret
3190 ;
3191 ; RV64ZBP-LABEL: shfl8_i32:
3192 ; RV64ZBP: # %bb.0:
3193 ; RV64ZBP-NEXT: zip8.w a0, a0
3194 ; RV64ZBP-NEXT: ret
3195 %and = and i32 %a, -16776961
3196 %shl = shl i32 %a, 8
3197 %and1 = and i32 %shl, 16711680
3198 %shr = lshr i32 %a, 8
3199 %and2 = and i32 %shr, 65280
3200 %or = or i32 %and, %and2
3201 %or3 = or i32 %or, %and1
3202 ret i32 %or3
3203 }
3205 define i64 @shfl8_i64(i64 %a, i64 %b) nounwind {
3206 ; RV64I-LABEL: shfl8_i64:
3207 ; RV64I: # %bb.0:
3208 ; RV64I-NEXT: lui a1, 983041
3209 ; RV64I-NEXT: slli a1, a1, 4
3210 ; RV64I-NEXT: addi a1, a1, -1
3211 ; RV64I-NEXT: slli a1, a1, 24
3212 ; RV64I-NEXT: addi a1, a1, 255
3213 ; RV64I-NEXT: and a1, a0, a1
3214 ; RV64I-NEXT: slli a2, a0, 8
3215 ; RV64I-NEXT: li a3, 255
3216 ; RV64I-NEXT: slli a3, a3, 32
3217 ; RV64I-NEXT: addi a3, a3, 255
3218 ; RV64I-NEXT: slli a4, a3, 16
3219 ; RV64I-NEXT: and a2, a2, a4
3220 ; RV64I-NEXT: srli a0, a0, 8
3221 ; RV64I-NEXT: slli a3, a3, 8
3222 ; RV64I-NEXT: and a0, a0, a3
3223 ; RV64I-NEXT: or a0, a0, a1
3224 ; RV64I-NEXT: or a0, a2, a0
3225 ; RV64I-NEXT: ret
3226 ;
3227 ; RV64ZBP-LABEL: shfl8_i64:
3228 ; RV64ZBP: # %bb.0:
3229 ; RV64ZBP-NEXT: zip8.w a0, a0
3230 ; RV64ZBP-NEXT: ret
3231 %and = and i64 %a, -72056494543077121
3232 %shl = shl i64 %a, 8
3233 %and1 = and i64 %shl, 71776119077928960
3234 %shr = lshr i64 %a, 8
3235 %and2 = and i64 %shr, 280375465148160
3236 %or = or i64 %and2, %and
3237 %or3 = or i64 %and1, %or
3238 ret i64 %or3
3239 }
3241 define i64 @shfl16(i64 %a, i64 %b) nounwind {
3242 ; RV64I-LABEL: shfl16:
3243 ; RV64I: # %bb.0:
3244 ; RV64I-NEXT: li a1, -1
3245 ; RV64I-NEXT: slli a1, a1, 32
3246 ; RV64I-NEXT: addi a1, a1, 1
3247 ; RV64I-NEXT: slli a1, a1, 16
3248 ; RV64I-NEXT: addi a1, a1, -1
3249 ; RV64I-NEXT: and a1, a0, a1
3250 ; RV64I-NEXT: srliw a2, a0, 16
3251 ; RV64I-NEXT: slli a2, a2, 32
3252 ; RV64I-NEXT: or a1, a2, a1
3253 ; RV64I-NEXT: srli a0, a0, 16
3254 ; RV64I-NEXT: lui a2, 65535
3255 ; RV64I-NEXT: slli a2, a2, 4
3256 ; RV64I-NEXT: and a0, a0, a2
3257 ; RV64I-NEXT: or a0, a1, a0
3258 ; RV64I-NEXT: ret
3259 ;
3260 ; RV64ZBP-LABEL: shfl16:
3261 ; RV64ZBP: # %bb.0:
3262 ; RV64ZBP-NEXT: zip16 a0, a0
3263 ; RV64ZBP-NEXT: ret
3264 %and = and i64 %a, -281474976645121
3265 %shl = shl i64 %a, 16
3266 %and1 = and i64 %shl, 281470681743360
3267 %or = or i64 %and1, %and
3268 %shr = lshr i64 %a, 16
3269 %and2 = and i64 %shr, 4294901760
3270 %or3 = or i64 %or, %and2
3271 ret i64 %or3
3272 }
3274 define signext i32 @packu_i32(i32 signext %a, i32 signext %b) nounwind {
3275 ; RV64I-LABEL: packu_i32:
3276 ; RV64I: # %bb.0:
3277 ; RV64I-NEXT: srliw a0, a0, 16
3278 ; RV64I-NEXT: lui a2, 1048560
3279 ; RV64I-NEXT: and a1, a1, a2
3280 ; RV64I-NEXT: or a0, a1, a0
3281 ; RV64I-NEXT: ret
3282 ;
3283 ; RV64ZBP-LABEL: packu_i32:
3284 ; RV64ZBP: # %bb.0:
3285 ; RV64ZBP-NEXT: packuw a0, a0, a1
3286 ; RV64ZBP-NEXT: ret
3287 %shr = lshr i32 %a, 16
3288 %shr1 = and i32 %b, -65536
3289 %or = or i32 %shr1, %shr
3290 ret i32 %or
3291 }
3293 define i64 @packu_i64(i64 %a, i64 %b) nounwind {
3294 ; RV64I-LABEL: packu_i64:
3295 ; RV64I: # %bb.0:
3296 ; RV64I-NEXT: srli a0, a0, 32
3297 ; RV64I-NEXT: srli a1, a1, 32
3298 ; RV64I-NEXT: slli a1, a1, 32
3299 ; RV64I-NEXT: or a0, a1, a0
3300 ; RV64I-NEXT: ret
3301 ;
3302 ; RV64ZBP-LABEL: packu_i64:
3303 ; RV64ZBP: # %bb.0:
3304 ; RV64ZBP-NEXT: packu a0, a0, a1
3305 ; RV64ZBP-NEXT: ret
3306 %shr = lshr i64 %a, 32
3307 %shr1 = and i64 %b, -4294967296
3308 %or = or i64 %shr1, %shr
3309 ret i64 %or
3310 }
3312 define i32 @zexth_i32(i32 %a) nounwind {
3313 ; RV64I-LABEL: zexth_i32:
3314 ; RV64I: # %bb.0:
3315 ; RV64I-NEXT: slli a0, a0, 48
3316 ; RV64I-NEXT: srli a0, a0, 48
3317 ; RV64I-NEXT: ret
3318 ;
3319 ; RV64ZBP-LABEL: zexth_i32:
3320 ; RV64ZBP: # %bb.0:
3321 ; RV64ZBP-NEXT: zext.h a0, a0
3322 ; RV64ZBP-NEXT: ret
3323 %and = and i32 %a, 65535
3324 ret i32 %and
3325 }
3327 define i64 @zexth_i64(i64 %a) nounwind {
3328 ; RV64I-LABEL: zexth_i64:
3329 ; RV64I: # %bb.0:
3330 ; RV64I-NEXT: slli a0, a0, 48
3331 ; RV64I-NEXT: srli a0, a0, 48
3332 ; RV64I-NEXT: ret
3333 ;
3334 ; RV64ZBP-LABEL: zexth_i64:
3335 ; RV64ZBP: # %bb.0:
3336 ; RV64ZBP-NEXT: zext.h a0, a0
3337 ; RV64ZBP-NEXT: ret
3338 %and = and i64 %a, 65535
3339 ret i64 %and
3340 }