1 ; Test 32-bit multiplication in which the second operand is a sign-extended
4 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
6 ; Check the low end of the MH range.
7 define i32 @f1(i32 %lhs, i16 *%src) {
9 ; CHECK: mh %r2, 0(%r3)
11 %half = load i16, i16 *%src
12 %rhs = sext i16 %half to i32
13 %res = mul i32 %lhs, %rhs
17 ; Check the high end of the aligned MH range.
18 define i32 @f2(i32 %lhs, i16 *%src) {
20 ; CHECK: mh %r2, 4094(%r3)
22 %ptr = getelementptr i16, i16 *%src, i64 2047
23 %half = load i16, i16 *%ptr
24 %rhs = sext i16 %half to i32
25 %res = mul i32 %lhs, %rhs
29 ; Check the next halfword up, which should use MHY instead of MH.
30 define i32 @f3(i32 %lhs, i16 *%src) {
32 ; CHECK: mhy %r2, 4096(%r3)
34 %ptr = getelementptr i16, i16 *%src, i64 2048
35 %half = load i16, i16 *%ptr
36 %rhs = sext i16 %half to i32
37 %res = mul i32 %lhs, %rhs
41 ; Check the high end of the aligned MHY range.
42 define i32 @f4(i32 %lhs, i16 *%src) {
44 ; CHECK: mhy %r2, 524286(%r3)
46 %ptr = getelementptr i16, i16 *%src, i64 262143
47 %half = load i16, i16 *%ptr
48 %rhs = sext i16 %half to i32
49 %res = mul i32 %lhs, %rhs
53 ; Check the next halfword up, which needs separate address logic.
54 ; Other sequences besides this one would be OK.
55 define i32 @f5(i32 %lhs, i16 *%src) {
57 ; CHECK: agfi %r3, 524288
58 ; CHECK: mh %r2, 0(%r3)
60 %ptr = getelementptr i16, i16 *%src, i64 262144
61 %half = load i16, i16 *%ptr
62 %rhs = sext i16 %half to i32
63 %res = mul i32 %lhs, %rhs
67 ; Check the high end of the negative aligned MHY range.
68 define i32 @f6(i32 %lhs, i16 *%src) {
70 ; CHECK: mhy %r2, -2(%r3)
72 %ptr = getelementptr i16, i16 *%src, i64 -1
73 %half = load i16, i16 *%ptr
74 %rhs = sext i16 %half to i32
75 %res = mul i32 %lhs, %rhs
79 ; Check the low end of the MHY range.
80 define i32 @f7(i32 %lhs, i16 *%src) {
82 ; CHECK: mhy %r2, -524288(%r3)
84 %ptr = getelementptr i16, i16 *%src, i64 -262144
85 %half = load i16, i16 *%ptr
86 %rhs = sext i16 %half to i32
87 %res = mul i32 %lhs, %rhs
91 ; Check the next halfword down, which needs separate address logic.
92 ; Other sequences besides this one would be OK.
93 define i32 @f8(i32 %lhs, i16 *%src) {
95 ; CHECK: agfi %r3, -524290
96 ; CHECK: mh %r2, 0(%r3)
98 %ptr = getelementptr i16, i16 *%src, i64 -262145
99 %half = load i16, i16 *%ptr
100 %rhs = sext i16 %half to i32
101 %res = mul i32 %lhs, %rhs
105 ; Check that MH allows an index.
106 define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
108 ; CHECK: mh %r2, 4094({{%r4,%r3|%r3,%r4}})
110 %add1 = add i64 %src, %index
111 %add2 = add i64 %add1, 4094
112 %ptr = inttoptr i64 %add2 to i16 *
113 %half = load i16, i16 *%ptr
114 %rhs = sext i16 %half to i32
115 %res = mul i32 %lhs, %rhs
119 ; Check that MHY allows an index.
120 define i32 @f10(i32 %lhs, i64 %src, i64 %index) {
122 ; CHECK: mhy %r2, 4096({{%r4,%r3|%r3,%r4}})
124 %add1 = add i64 %src, %index
125 %add2 = add i64 %add1, 4096
126 %ptr = inttoptr i64 %add2 to i16 *
127 %half = load i16, i16 *%ptr
128 %rhs = sext i16 %half to i32
129 %res = mul i32 %lhs, %rhs