1 // RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
3 // Test to check the bare minimum pressure sets.
4 // At least one register pressure set is required for the target.
5 // Allowed the pset only for D_32 regclass and ignored it for all
6 // other classes including the tuples.
7 include "llvm/Target/Target.td"
9 class MyClass<int size, list<ValueType> types, dag registers>
10 : RegisterClass<"MyTarget", types, size, registers> {
14 def sub0 : SubRegIndex<32>;
15 def sub1 : SubRegIndex<32, 32>;
17 let Namespace = "MyTarget" in {
18 def D : Register<"d">;
19 foreach Index = 0-7 in {
20 def S#Index : Register <"s"#Index>;
24 // Should generate psets for D_32
25 def D_32 : MyClass<32, [i32], (add D)>;
27 let GeneratePressureSet = 0 in {
28 def S_32 : MyClass<32, [i32], (sequence "S%u", 0, 7)>;
29 def SD_32 : MyClass<32, [i32], (add S_32, D_32)>;
32 def S_64 : RegisterTuples<[sub0, sub1],
33 [(decimate (shl S_32, 0), 1),
34 (decimate (shl S_32, 1), 1)
37 def SReg_64 : MyClass<64, [i64], (add S_64)> {
38 let GeneratePressureSet = 0;
41 def MyTarget : Target;
43 // CHECK-LABEL: // Register pressure sets enum.
44 // CHECK-NEXT: namespace MyTarget {
45 // CHECK-NEXT: enum RegisterPressureSets {
46 // CHECK-NEXT: D_32 = 0,
48 // NAMESPACE-NEXT: } // end namespace TestNamespace
50 // CHECK-LABEL: getRegPressureSetName(unsigned Idx) const {
51 // CHECK-NEXT: static const char *PressureNameTable[] = {
52 // CHECK-NEXT: "D_32",
54 // CHECK-NEXT: return PressureNameTable[Idx];
57 // CHECK: unsigned MyTargetGenRegisterInfo::
58 // CHECK-NEXT: getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
59 // CHECK-NEXT: static const uint8_t PressureLimitTable[] = {
60 // CHECK-NEXT: {{[0-9]+}}, // 0: D_32
62 // CHECK-NEXT: return PressureLimitTable[Idx];
65 // CHECK: static const int RCSetsTable[] = {
66 // CHECK-NEXT: /* 0 */ 0, -1,