compiler-rt/lib/xray/xray_mips.cpp

   1 //===-- xray_mips.cpp -------------------------------------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file is a part of XRay, a dynamic runtime instrumentation system.
  10 //
  11 // Implementation of MIPS-specific routines (32-bit).
  12 //
  13 //===----------------------------------------------------------------------===//
  14 #include "sanitizer_common/sanitizer_common.h"
  15 #include "xray_defs.h"
  16 #include "xray_interface_internal.h"
  17 #include <atomic>
  18
  19 namespace __xray {
  20
  21 // The machine codes for some instructions used in runtime patching.
  22 enum PatchOpcodes : uint32_t {
  23   PO_ADDIU = 0x24000000, // addiu rt, rs, imm
  24   PO_SW = 0xAC000000,    // sw rt, offset(sp)
  25   PO_LUI = 0x3C000000,   // lui rs, %hi(address)
  26   PO_ORI = 0x34000000,   // ori rt, rs, %lo(address)
  27   PO_JALR = 0x0000F809,  // jalr rs
  28   PO_LW = 0x8C000000,    // lw rt, offset(address)
  29   PO_B44 = 0x1000000b,   // b #44
  30   PO_NOP = 0x0,          // nop
  31 };
  32
  33 enum RegNum : uint32_t {
  34   RN_T0 = 0x8,
  35   RN_T9 = 0x19,
  36   RN_RA = 0x1F,
  37   RN_SP = 0x1D,
  38 };
  39
  40 inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs,
  41                                          uint32_t Rt,
  42                                          uint32_t Imm) XRAY_NEVER_INSTRUMENT {
  43   return (Opcode | Rs << 21 | Rt << 16 | Imm);
  44 }
  45
  46 inline static uint32_t
  47 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd,
  48                          uint32_t Imm) XRAY_NEVER_INSTRUMENT {
  49   return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode);
  50 }
  51
  52 inline static bool patchSled(const bool Enable, const uint32_t FuncId,
  53                              const XRaySledEntry &Sled,
  54                              void (*TracingHook)()) XRAY_NEVER_INSTRUMENT {
  55   // When |Enable| == true,
  56   // We replace the following compile-time stub (sled):
  57   //
  58   // xray_sled_n:
  59   //    B .tmpN
  60   //    11 NOPs (44 bytes)
  61   //    .tmpN
  62   //    ADDIU T9, T9, 44
  63   //
  64   // With the following runtime patch:
  65   //
  66   // xray_sled_n (32-bit):
  67   //    addiu sp, sp, -8                        ;create stack frame
  68   //    nop
  69   //    sw ra, 4(sp)                            ;save return address
  70   //    sw t9, 0(sp)                            ;save register t9
  71   //    lui t9, %hi(__xray_FunctionEntry/Exit)
  72   //    ori t9, t9, %lo(__xray_FunctionEntry/Exit)
  73   //    lui t0, %hi(function_id)
  74   //    jalr t9                                 ;call Tracing hook
  75   //    ori t0, t0, %lo(function_id)            ;pass function id (delay slot)
  76   //    lw t9, 0(sp)                            ;restore register t9
  77   //    lw ra, 4(sp)                            ;restore return address
  78   //    addiu sp, sp, 8                         ;delete stack frame
  79   //
  80   // We add 44 bytes to t9 because we want to adjust the function pointer to
  81   // the actual start of function i.e. the address just after the noop sled.
  82   // We do this because gp displacement relocation is emitted at the start of
  83   // of the function i.e after the nop sled and to correctly calculate the
  84   // global offset table address, t9 must hold the address of the instruction
  85   // containing the gp displacement relocation.
  86   // FIXME: Is this correct for the static relocation model?
  87   //
  88   // Replacement of the first 4-byte instruction should be the last and atomic
  89   // operation, so that the user code which reaches the sled concurrently
  90   // either jumps over the whole sled, or executes the whole sled when the
  91   // latter is ready.
  92   //
  93   // When |Enable|==false, we set back the first instruction in the sled to be
  94   //   B #44
  95
  96   if (Enable) {
  97     uint32_t LoTracingHookAddr =
  98         reinterpret_cast<int32_t>(TracingHook) & 0xffff;
  99     uint32_t HiTracingHookAddr =
 100         (reinterpret_cast<int32_t>(TracingHook) >> 16) & 0xffff;
 101     uint32_t LoFunctionID = FuncId & 0xffff;
 102     uint32_t HiFunctionID = (FuncId >> 16) & 0xffff;
 103     *reinterpret_cast<uint32_t *>(Sled.Address + 8) = encodeInstruction(
 104         PatchOpcodes::PO_SW, RegNum::RN_SP, RegNum::RN_RA, 0x4);
 105     *reinterpret_cast<uint32_t *>(Sled.Address + 12) = encodeInstruction(
 106         PatchOpcodes::PO_SW, RegNum::RN_SP, RegNum::RN_T9, 0x0);
 107     *reinterpret_cast<uint32_t *>(Sled.Address + 16) = encodeInstruction(
 108         PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9, HiTracingHookAddr);
 109     *reinterpret_cast<uint32_t *>(Sled.Address + 20) = encodeInstruction(
 110         PatchOpcodes::PO_ORI, RegNum::RN_T9, RegNum::RN_T9, LoTracingHookAddr);
 111     *reinterpret_cast<uint32_t *>(Sled.Address + 24) = encodeInstruction(
 112         PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T0, HiFunctionID);
 113     *reinterpret_cast<uint32_t *>(Sled.Address + 28) = encodeSpecialInstruction(
 114         PatchOpcodes::PO_JALR, RegNum::RN_T9, 0x0, RegNum::RN_RA, 0X0);
 115     *reinterpret_cast<uint32_t *>(Sled.Address + 32) = encodeInstruction(
 116         PatchOpcodes::PO_ORI, RegNum::RN_T0, RegNum::RN_T0, LoFunctionID);
 117     *reinterpret_cast<uint32_t *>(Sled.Address + 36) = encodeInstruction(
 118         PatchOpcodes::PO_LW, RegNum::RN_SP, RegNum::RN_T9, 0x0);
 119     *reinterpret_cast<uint32_t *>(Sled.Address + 40) = encodeInstruction(
 120         PatchOpcodes::PO_LW, RegNum::RN_SP, RegNum::RN_RA, 0x4);
 121     *reinterpret_cast<uint32_t *>(Sled.Address + 44) = encodeInstruction(
 122         PatchOpcodes::PO_ADDIU, RegNum::RN_SP, RegNum::RN_SP, 0x8);
 123     uint32_t CreateStackSpaceInstr = encodeInstruction(
 124         PatchOpcodes::PO_ADDIU, RegNum::RN_SP, RegNum::RN_SP, 0xFFF8);
 125     std::atomic_store_explicit(
 126         reinterpret_cast<std::atomic<uint32_t> *>(Sled.Address),
 127         uint32_t(CreateStackSpaceInstr), std::memory_order_release);
 128   } else {
 129     std::atomic_store_explicit(
 130         reinterpret_cast<std::atomic<uint32_t> *>(Sled.Address),
 131         uint32_t(PatchOpcodes::PO_B44), std::memory_order_release);
 132   }
 133   return true;
 134 }
 135
 136 bool patchFunctionEntry(const bool Enable, const uint32_t FuncId,
 137                         const XRaySledEntry &Sled,
 138                         void (*Trampoline)()) XRAY_NEVER_INSTRUMENT {
 139   return patchSled(Enable, FuncId, Sled, Trampoline);
 140 }
 141
 142 bool patchFunctionExit(const bool Enable, const uint32_t FuncId,
 143                        const XRaySledEntry &Sled) XRAY_NEVER_INSTRUMENT {
 144   return patchSled(Enable, FuncId, Sled, __xray_FunctionExit);
 145 }
 146
 147 bool patchFunctionTailExit(const bool Enable, const uint32_t FuncId,
 148                            const XRaySledEntry &Sled) XRAY_NEVER_INSTRUMENT {
 149   // FIXME: In the future we'd need to distinguish between non-tail exits and
 150   // tail exits for better information preservation.
 151   return patchSled(Enable, FuncId, Sled, __xray_FunctionExit);
 152 }
 153
 154 bool patchCustomEvent(const bool Enable, const uint32_t FuncId,
 155                       const XRaySledEntry &Sled) XRAY_NEVER_INSTRUMENT {
 156   // FIXME: Implement in mips?
 157   return false;
 158 }
 159
 160 bool patchTypedEvent(const bool Enable, const uint32_t FuncId,
 161                      const XRaySledEntry &Sled) XRAY_NEVER_INSTRUMENT {
 162   // FIXME: Implement in mips?
 163   return false;
 164 }
 165
 166 } // namespace __xray
 167
 168 extern "C" void __xray_ArgLoggerEntry() XRAY_NEVER_INSTRUMENT {
 169   // FIXME: this will have to be implemented in the trampoline assembly file
 170 }