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[PowerPC] Collect some CallLowering arguments into a struct. [NFC]
[llvm-project.git] / llvm / lib / Target / AArch64 / AArch64AsmPrinter.cpp
blob00e321f9b8509995dd993fcc9d8eaee151aa0700
1 //===- AArch64AsmPrinter.cpp - AArch64 LLVM assembly writer ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a printer that converts from our internal representation
10 // of machine-dependent LLVM code to the AArch64 assembly language.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "AArch64.h"
15 #include "AArch64MCInstLower.h"
16 #include "AArch64MachineFunctionInfo.h"
17 #include "AArch64RegisterInfo.h"
18 #include "AArch64Subtarget.h"
19 #include "AArch64TargetObjectFile.h"
20 #include "MCTargetDesc/AArch64AddressingModes.h"
21 #include "MCTargetDesc/AArch64InstPrinter.h"
22 #include "MCTargetDesc/AArch64MCExpr.h"
23 #include "MCTargetDesc/AArch64MCTargetDesc.h"
24 #include "MCTargetDesc/AArch64TargetStreamer.h"
25 #include "TargetInfo/AArch64TargetInfo.h"
26 #include "Utils/AArch64BaseInfo.h"
27 #include "llvm/ADT/SmallString.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/ADT/StringRef.h"
30 #include "llvm/ADT/Triple.h"
31 #include "llvm/ADT/Twine.h"
32 #include "llvm/BinaryFormat/COFF.h"
33 #include "llvm/BinaryFormat/ELF.h"
34 #include "llvm/CodeGen/AsmPrinter.h"
35 #include "llvm/CodeGen/MachineBasicBlock.h"
36 #include "llvm/CodeGen/MachineFunction.h"
37 #include "llvm/CodeGen/MachineInstr.h"
38 #include "llvm/CodeGen/MachineJumpTableInfo.h"
39 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
40 #include "llvm/CodeGen/MachineOperand.h"
41 #include "llvm/CodeGen/StackMaps.h"
42 #include "llvm/CodeGen/TargetRegisterInfo.h"
43 #include "llvm/IR/DataLayout.h"
44 #include "llvm/IR/DebugInfoMetadata.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCInst.h"
48 #include "llvm/MC/MCInstBuilder.h"
49 #include "llvm/MC/MCSectionELF.h"
50 #include "llvm/MC/MCStreamer.h"
51 #include "llvm/MC/MCSymbol.h"
52 #include "llvm/Support/Casting.h"
53 #include "llvm/Support/ErrorHandling.h"
54 #include "llvm/Support/TargetRegistry.h"
55 #include "llvm/Support/raw_ostream.h"
56 #include "llvm/Target/TargetMachine.h"
57 #include <algorithm>
58 #include <cassert>
59 #include <cstdint>
60 #include <map>
61 #include <memory>
62
63 using namespace llvm;
64
65 #define DEBUG_TYPE "asm-printer"
66
67 namespace {
68
69 class AArch64AsmPrinter : public AsmPrinter {
70 AArch64MCInstLower MCInstLowering;
71 StackMaps SM;
72 const AArch64Subtarget *STI;
73
74 public:
75 AArch64AsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
76 : AsmPrinter(TM, std::move(Streamer)), MCInstLowering(OutContext, *this),
77 SM(*this) {}
78
79 StringRef getPassName() const override { return "AArch64 Assembly Printer"; }
80
81 /// Wrapper for MCInstLowering.lowerOperand() for the
82 /// tblgen'erated pseudo lowering.
83 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
84 return MCInstLowering.lowerOperand(MO, MCOp);
85 }
86
87 void EmitStartOfAsmFile(Module &M) override;
88 void EmitJumpTableInfo() override;
89 void emitJumpTableEntry(const MachineJumpTableInfo *MJTI,
90 const MachineBasicBlock *MBB, unsigned JTI);
91
92 void LowerJumpTableDestSmall(MCStreamer &OutStreamer, const MachineInstr &MI);
93
94 void LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
95 const MachineInstr &MI);
96 void LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
97 const MachineInstr &MI);
98
99 void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI);
100 void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI);
101 void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI);
102
103 typedef std::tuple<unsigned, bool, uint32_t> HwasanMemaccessTuple;
104 std::map<HwasanMemaccessTuple, MCSymbol *> HwasanMemaccessSymbols;
105 void LowerHWASAN_CHECK_MEMACCESS(const MachineInstr &MI);
106 void EmitHwasanMemaccessSymbols(Module &M);
107
108 void EmitSled(const MachineInstr &MI, SledKind Kind);
109
110 /// tblgen'erated driver function for lowering simple MI->MC
111 /// pseudo instructions.
112 bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
113 const MachineInstr *MI);
114
115 void EmitInstruction(const MachineInstr *MI) override;
116
117 void getAnalysisUsage(AnalysisUsage &AU) const override {
118 AsmPrinter::getAnalysisUsage(AU);
119 AU.setPreservesAll();
120 }
121
122 bool runOnMachineFunction(MachineFunction &MF) override {
123 AArch64FI = MF.getInfo<AArch64FunctionInfo>();
124 STI = static_cast<const AArch64Subtarget*>(&MF.getSubtarget());
125
126 SetupMachineFunction(MF);
127
128 if (STI->isTargetCOFF()) {
129 bool Internal = MF.getFunction().hasInternalLinkage();
130 COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
131 : COFF::IMAGE_SYM_CLASS_EXTERNAL;
132 int Type =
133 COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
134
135 OutStreamer->BeginCOFFSymbolDef(CurrentFnSym);
136 OutStreamer->EmitCOFFSymbolStorageClass(Scl);
137 OutStreamer->EmitCOFFSymbolType(Type);
138 OutStreamer->EndCOFFSymbolDef();
139 }
140
141 // Emit the rest of the function body.
142 EmitFunctionBody();
143
144 // Emit the XRay table for this function.
145 emitXRayTable();
146
147 // We didn't modify anything.
148 return false;
149 }
150
151 private:
152 void printOperand(const MachineInstr *MI, unsigned OpNum, raw_ostream &O);
153 bool printAsmMRegister(const MachineOperand &MO, char Mode, raw_ostream &O);
154 bool printAsmRegInClass(const MachineOperand &MO,
155 const TargetRegisterClass *RC, unsigned AltName,
156 raw_ostream &O);
157
158 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
159 const char *ExtraCode, raw_ostream &O) override;
160 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
161 const char *ExtraCode, raw_ostream &O) override;
162
163 void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
164
165 void EmitFunctionBodyEnd() override;
166
167 MCSymbol *GetCPISymbol(unsigned CPID) const override;
168 void EmitEndOfAsmFile(Module &M) override;
169
170 AArch64FunctionInfo *AArch64FI = nullptr;
171
172 /// Emit the LOHs contained in AArch64FI.
173 void EmitLOHs();
174
175 /// Emit instruction to set float register to zero.
176 void EmitFMov0(const MachineInstr &MI);
177
178 using MInstToMCSymbol = std::map<const MachineInstr *, MCSymbol *>;
179
180 MInstToMCSymbol LOHInstToLabel;
181 };
182
183 } // end anonymous namespace
184
185 void AArch64AsmPrinter::EmitStartOfAsmFile(Module &M) {
186 if (!TM.getTargetTriple().isOSBinFormatELF())
187 return;
188
189 // Assemble feature flags that may require creation of a note section.
190 unsigned Flags = ELF::GNU_PROPERTY_AARCH64_FEATURE_1_BTI |
191 ELF::GNU_PROPERTY_AARCH64_FEATURE_1_PAC;
192
193 if (any_of(M, [](const Function &F) {
194 return !F.isDeclaration() &&
195 !F.hasFnAttribute("branch-target-enforcement");
196 })) {
197 Flags &= ~ELF::GNU_PROPERTY_AARCH64_FEATURE_1_BTI;
198 }
199
200 if ((Flags & ELF::GNU_PROPERTY_AARCH64_FEATURE_1_BTI) == 0 &&
201 any_of(M, [](const Function &F) {
202 return F.hasFnAttribute("branch-target-enforcement");
203 })) {
204 errs() << "warning: some functions compiled with BTI and some compiled "
205 "without BTI\n"
206 << "warning: not setting BTI in feature flags\n";
207 }
208
209 if (any_of(M, [](const Function &F) {
210 if (F.isDeclaration())
211 return false;
212 Attribute A = F.getFnAttribute("sign-return-address");
213 return !A.isStringAttribute() || A.getValueAsString() == "none";
214 })) {
215 Flags &= ~ELF::GNU_PROPERTY_AARCH64_FEATURE_1_PAC;
216 }
217
218 if (Flags == 0)
219 return;
220
221 // Emit a .note.gnu.property section with the flags.
222 MCSection *Cur = OutStreamer->getCurrentSectionOnly();
223 MCSection *Nt = MMI->getContext().getELFSection(
224 ".note.gnu.property", ELF::SHT_NOTE, ELF::SHF_ALLOC);
225 OutStreamer->SwitchSection(Nt);
226
227 // Emit the note header.
228 EmitAlignment(Align(8));
229 OutStreamer->EmitIntValue(4, 4); // data size for "GNU\0"
230 OutStreamer->EmitIntValue(4 * 4, 4); // Elf_Prop size
231 OutStreamer->EmitIntValue(ELF::NT_GNU_PROPERTY_TYPE_0, 4);
232 OutStreamer->EmitBytes(StringRef("GNU", 4)); // note name
233
234 // Emit the PAC/BTI properties.
235 OutStreamer->EmitIntValue(ELF::GNU_PROPERTY_AARCH64_FEATURE_1_AND, 4);
236 OutStreamer->EmitIntValue(4, 4); // data size
237 OutStreamer->EmitIntValue(Flags, 4); // data
238 OutStreamer->EmitIntValue(0, 4); // pad
239
240 OutStreamer->endSection(Nt);
241 OutStreamer->SwitchSection(Cur);
242 }
243
244 void AArch64AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
245 {
246 const Function &F = MF->getFunction();
247 if (F.hasFnAttribute("patchable-function-entry")) {
248 unsigned Num;
249 if (F.getFnAttribute("patchable-function-entry")
250 .getValueAsString()
251 .getAsInteger(10, Num))
252 return;
253 for (; Num; --Num)
254 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
255 return;
256 }
257
258 EmitSled(MI, SledKind::FUNCTION_ENTER);
259 }
260
261 void AArch64AsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
262 {
263 EmitSled(MI, SledKind::FUNCTION_EXIT);
264 }
265
266 void AArch64AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
267 {
268 EmitSled(MI, SledKind::TAIL_CALL);
269 }
270
271 void AArch64AsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind)
272 {
273 static const int8_t NoopsInSledCount = 7;
274 // We want to emit the following pattern:
275 //
276 // .Lxray_sled_N:
277 // ALIGN
278 // B #32
279 // ; 7 NOP instructions (28 bytes)
280 // .tmpN
281 //
282 // We need the 28 bytes (7 instructions) because at runtime, we'd be patching
283 // over the full 32 bytes (8 instructions) with the following pattern:
284 //
285 // STP X0, X30, [SP, #-16]! ; push X0 and the link register to the stack
286 // LDR W0, #12 ; W0 := function ID
287 // LDR X16,#12 ; X16 := addr of __xray_FunctionEntry or __xray_FunctionExit
288 // BLR X16 ; call the tracing trampoline
289 // ;DATA: 32 bits of function ID
290 // ;DATA: lower 32 bits of the address of the trampoline
291 // ;DATA: higher 32 bits of the address of the trampoline
292 // LDP X0, X30, [SP], #16 ; pop X0 and the link register from the stack
293 //
294 OutStreamer->EmitCodeAlignment(4);
295 auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
296 OutStreamer->EmitLabel(CurSled);
297 auto Target = OutContext.createTempSymbol();
298
299 // Emit "B #32" instruction, which jumps over the next 28 bytes.
300 // The operand has to be the number of 4-byte instructions to jump over,
301 // including the current instruction.
302 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::B).addImm(8));
303
304 for (int8_t I = 0; I < NoopsInSledCount; I++)
305 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
306
307 OutStreamer->EmitLabel(Target);
308 recordSled(CurSled, MI, Kind);
309 }
310
311 void AArch64AsmPrinter::LowerHWASAN_CHECK_MEMACCESS(const MachineInstr &MI) {
312 Register Reg = MI.getOperand(0).getReg();
313 bool IsShort =
314 MI.getOpcode() == AArch64::HWASAN_CHECK_MEMACCESS_SHORTGRANULES;
315 uint32_t AccessInfo = MI.getOperand(1).getImm();
316 MCSymbol *&Sym =
317 HwasanMemaccessSymbols[HwasanMemaccessTuple(Reg, IsShort, AccessInfo)];
318 if (!Sym) {
319 // FIXME: Make this work on non-ELF.
320 if (!TM.getTargetTriple().isOSBinFormatELF())
321 report_fatal_error("llvm.hwasan.check.memaccess only supported on ELF");
322
323 std::string SymName = "__hwasan_check_x" + utostr(Reg - AArch64::X0) + "_" +
324 utostr(AccessInfo);
325 if (IsShort)
326 SymName += "_short";
327 Sym = OutContext.getOrCreateSymbol(SymName);
328 }
329
330 EmitToStreamer(*OutStreamer,
331 MCInstBuilder(AArch64::BL)
332 .addExpr(MCSymbolRefExpr::create(Sym, OutContext)));
333 }
334
335 void AArch64AsmPrinter::EmitHwasanMemaccessSymbols(Module &M) {
336 if (HwasanMemaccessSymbols.empty())
337 return;
338
339 const Triple &TT = TM.getTargetTriple();
340 assert(TT.isOSBinFormatELF());
341 std::unique_ptr<MCSubtargetInfo> STI(
342 TM.getTarget().createMCSubtargetInfo(TT.str(), "", ""));
343
344 MCSymbol *HwasanTagMismatchV1Sym =
345 OutContext.getOrCreateSymbol("__hwasan_tag_mismatch");
346 MCSymbol *HwasanTagMismatchV2Sym =
347 OutContext.getOrCreateSymbol("__hwasan_tag_mismatch_v2");
348
349 const MCSymbolRefExpr *HwasanTagMismatchV1Ref =
350 MCSymbolRefExpr::create(HwasanTagMismatchV1Sym, OutContext);
351 const MCSymbolRefExpr *HwasanTagMismatchV2Ref =
352 MCSymbolRefExpr::create(HwasanTagMismatchV2Sym, OutContext);
353
354 for (auto &P : HwasanMemaccessSymbols) {
355 unsigned Reg = std::get<0>(P.first);
356 bool IsShort = std::get<1>(P.first);
357 uint32_t AccessInfo = std::get<2>(P.first);
358 const MCSymbolRefExpr *HwasanTagMismatchRef =
359 IsShort ? HwasanTagMismatchV2Ref : HwasanTagMismatchV1Ref;
360 MCSymbol *Sym = P.second;
361
362 OutStreamer->SwitchSection(OutContext.getELFSection(
363 ".text.hot", ELF::SHT_PROGBITS,
364 ELF::SHF_EXECINSTR | ELF::SHF_ALLOC | ELF::SHF_GROUP, 0,
365 Sym->getName()));
366
367 OutStreamer->EmitSymbolAttribute(Sym, MCSA_ELF_TypeFunction);
368 OutStreamer->EmitSymbolAttribute(Sym, MCSA_Weak);
369 OutStreamer->EmitSymbolAttribute(Sym, MCSA_Hidden);
370 OutStreamer->EmitLabel(Sym);
371
372 OutStreamer->EmitInstruction(MCInstBuilder(AArch64::UBFMXri)
373 .addReg(AArch64::X16)
374 .addReg(Reg)
375 .addImm(4)
376 .addImm(55),
377 *STI);
378 OutStreamer->EmitInstruction(MCInstBuilder(AArch64::LDRBBroX)
379 .addReg(AArch64::W16)
380 .addReg(AArch64::X9)
381 .addReg(AArch64::X16)
382 .addImm(0)
383 .addImm(0),
384 *STI);
385 OutStreamer->EmitInstruction(
386 MCInstBuilder(AArch64::SUBSXrs)
387 .addReg(AArch64::XZR)
388 .addReg(AArch64::X16)
389 .addReg(Reg)
390 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56)),
391 *STI);
392 MCSymbol *HandleMismatchOrPartialSym = OutContext.createTempSymbol();
393 OutStreamer->EmitInstruction(
394 MCInstBuilder(AArch64::Bcc)
395 .addImm(AArch64CC::NE)
396 .addExpr(MCSymbolRefExpr::create(HandleMismatchOrPartialSym,
397 OutContext)),
398 *STI);
399 MCSymbol *ReturnSym = OutContext.createTempSymbol();
400 OutStreamer->EmitLabel(ReturnSym);
401 OutStreamer->EmitInstruction(
402 MCInstBuilder(AArch64::RET).addReg(AArch64::LR), *STI);
403 OutStreamer->EmitLabel(HandleMismatchOrPartialSym);
404
405 if (IsShort) {
406 OutStreamer->EmitInstruction(MCInstBuilder(AArch64::SUBSWri)
407 .addReg(AArch64::WZR)
408 .addReg(AArch64::W16)
409 .addImm(15)
410 .addImm(0),
411 *STI);
412 MCSymbol *HandleMismatchSym = OutContext.createTempSymbol();
413 OutStreamer->EmitInstruction(
414 MCInstBuilder(AArch64::Bcc)
415 .addImm(AArch64CC::HI)
416 .addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
417 *STI);
418
419 OutStreamer->EmitInstruction(
420 MCInstBuilder(AArch64::ANDXri)
421 .addReg(AArch64::X17)
422 .addReg(Reg)
423 .addImm(AArch64_AM::encodeLogicalImmediate(0xf, 64)),
424 *STI);
425 unsigned Size = 1 << (AccessInfo & 0xf);
426 if (Size != 1)
427 OutStreamer->EmitInstruction(MCInstBuilder(AArch64::ADDXri)
428 .addReg(AArch64::X17)
429 .addReg(AArch64::X17)
430 .addImm(Size - 1)
431 .addImm(0),
432 *STI);
433 OutStreamer->EmitInstruction(MCInstBuilder(AArch64::SUBSWrs)
434 .addReg(AArch64::WZR)
435 .addReg(AArch64::W16)
436 .addReg(AArch64::W17)
437 .addImm(0),
438 *STI);
439 OutStreamer->EmitInstruction(
440 MCInstBuilder(AArch64::Bcc)
441 .addImm(AArch64CC::LS)
442 .addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
443 *STI);
444
445 OutStreamer->EmitInstruction(
446 MCInstBuilder(AArch64::ORRXri)
447 .addReg(AArch64::X16)
448 .addReg(Reg)
449 .addImm(AArch64_AM::encodeLogicalImmediate(0xf, 64)),
450 *STI);
451 OutStreamer->EmitInstruction(MCInstBuilder(AArch64::LDRBBui)
452 .addReg(AArch64::W16)
453 .addReg(AArch64::X16)
454 .addImm(0),
455 *STI);
456 OutStreamer->EmitInstruction(
457 MCInstBuilder(AArch64::SUBSXrs)
458 .addReg(AArch64::XZR)
459 .addReg(AArch64::X16)
460 .addReg(Reg)
461 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56)),
462 *STI);
463 OutStreamer->EmitInstruction(
464 MCInstBuilder(AArch64::Bcc)
465 .addImm(AArch64CC::EQ)
466 .addExpr(MCSymbolRefExpr::create(ReturnSym, OutContext)),
467 *STI);
468
469 OutStreamer->EmitLabel(HandleMismatchSym);
470 }
471
472 OutStreamer->EmitInstruction(MCInstBuilder(AArch64::STPXpre)
473 .addReg(AArch64::SP)
474 .addReg(AArch64::X0)
475 .addReg(AArch64::X1)
476 .addReg(AArch64::SP)
477 .addImm(-32),
478 *STI);
479 OutStreamer->EmitInstruction(MCInstBuilder(AArch64::STPXi)
480 .addReg(AArch64::FP)
481 .addReg(AArch64::LR)
482 .addReg(AArch64::SP)
483 .addImm(29),
484 *STI);
485
486 if (Reg != AArch64::X0)
487 OutStreamer->EmitInstruction(MCInstBuilder(AArch64::ORRXrs)
488 .addReg(AArch64::X0)
489 .addReg(AArch64::XZR)
490 .addReg(Reg)
491 .addImm(0),
492 *STI);
493 OutStreamer->EmitInstruction(MCInstBuilder(AArch64::MOVZXi)
494 .addReg(AArch64::X1)
495 .addImm(AccessInfo)
496 .addImm(0),
497 *STI);
498
499 // Intentionally load the GOT entry and branch to it, rather than possibly
500 // late binding the function, which may clobber the registers before we have
501 // a chance to save them.
502 OutStreamer->EmitInstruction(
503 MCInstBuilder(AArch64::ADRP)
504 .addReg(AArch64::X16)
505 .addExpr(AArch64MCExpr::create(
506 HwasanTagMismatchRef, AArch64MCExpr::VariantKind::VK_GOT_PAGE,
507 OutContext)),
508 *STI);
509 OutStreamer->EmitInstruction(
510 MCInstBuilder(AArch64::LDRXui)
511 .addReg(AArch64::X16)
512 .addReg(AArch64::X16)
513 .addExpr(AArch64MCExpr::create(
514 HwasanTagMismatchRef, AArch64MCExpr::VariantKind::VK_GOT_LO12,
515 OutContext)),
516 *STI);
517 OutStreamer->EmitInstruction(
518 MCInstBuilder(AArch64::BR).addReg(AArch64::X16), *STI);
519 }
520 }
521
522 void AArch64AsmPrinter::EmitEndOfAsmFile(Module &M) {
523 EmitHwasanMemaccessSymbols(M);
524
525 const Triple &TT = TM.getTargetTriple();
526 if (TT.isOSBinFormatMachO()) {
527 // Funny Darwin hack: This flag tells the linker that no global symbols
528 // contain code that falls through to other global symbols (e.g. the obvious
529 // implementation of multiple entry points). If this doesn't occur, the
530 // linker can safely perform dead code stripping. Since LLVM never
531 // generates code that does this, it is always safe to set.
532 OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
533 }
534 emitStackMaps(SM);
535 }
536
537 void AArch64AsmPrinter::EmitLOHs() {
538 SmallVector<MCSymbol *, 3> MCArgs;
539
540 for (const auto &D : AArch64FI->getLOHContainer()) {
541 for (const MachineInstr *MI : D.getArgs()) {
542 MInstToMCSymbol::iterator LabelIt = LOHInstToLabel.find(MI);
543 assert(LabelIt != LOHInstToLabel.end() &&
544 "Label hasn't been inserted for LOH related instruction");
545 MCArgs.push_back(LabelIt->second);
546 }
547 OutStreamer->EmitLOHDirective(D.getKind(), MCArgs);
548 MCArgs.clear();
549 }
550 }
551
552 void AArch64AsmPrinter::EmitFunctionBodyEnd() {
553 if (!AArch64FI->getLOHRelated().empty())
554 EmitLOHs();
555 }
556
557 /// GetCPISymbol - Return the symbol for the specified constant pool entry.
558 MCSymbol *AArch64AsmPrinter::GetCPISymbol(unsigned CPID) const {
559 // Darwin uses a linker-private symbol name for constant-pools (to
560 // avoid addends on the relocation?), ELF has no such concept and
561 // uses a normal private symbol.
562 if (!getDataLayout().getLinkerPrivateGlobalPrefix().empty())
563 return OutContext.getOrCreateSymbol(
564 Twine(getDataLayout().getLinkerPrivateGlobalPrefix()) + "CPI" +
565 Twine(getFunctionNumber()) + "_" + Twine(CPID));
566
567 return AsmPrinter::GetCPISymbol(CPID);
568 }
569
570 void AArch64AsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNum,
571 raw_ostream &O) {
572 const MachineOperand &MO = MI->getOperand(OpNum);
573 switch (MO.getType()) {
574 default:
575 llvm_unreachable("<unknown operand type>");
576 case MachineOperand::MO_Register: {
577 Register Reg = MO.getReg();
578 assert(Register::isPhysicalRegister(Reg));
579 assert(!MO.getSubReg() && "Subregs should be eliminated!");
580 O << AArch64InstPrinter::getRegisterName(Reg);
581 break;
582 }
583 case MachineOperand::MO_Immediate: {
584 O << MO.getImm();
585 break;
586 }
587 case MachineOperand::MO_GlobalAddress: {
588 PrintSymbolOperand(MO, O);
589 break;
590 }
591 case MachineOperand::MO_BlockAddress: {
592 MCSymbol *Sym = GetBlockAddressSymbol(MO.getBlockAddress());
593 Sym->print(O, MAI);
594 break;
595 }
596 }
597 }
598
599 bool AArch64AsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode,
600 raw_ostream &O) {
601 Register Reg = MO.getReg();
602 switch (Mode) {
603 default:
604 return true; // Unknown mode.
605 case 'w':
606 Reg = getWRegFromXReg(Reg);
607 break;
608 case 'x':
609 Reg = getXRegFromWReg(Reg);
610 break;
611 }
612
613 O << AArch64InstPrinter::getRegisterName(Reg);
614 return false;
615 }
616
617 // Prints the register in MO using class RC using the offset in the
618 // new register class. This should not be used for cross class
619 // printing.
620 bool AArch64AsmPrinter::printAsmRegInClass(const MachineOperand &MO,
621 const TargetRegisterClass *RC,
622 unsigned AltName, raw_ostream &O) {
623 assert(MO.isReg() && "Should only get here with a register!");
624 const TargetRegisterInfo *RI = STI->getRegisterInfo();
625 Register Reg = MO.getReg();
626 unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg));
627 assert(RI->regsOverlap(RegToPrint, Reg));
628 O << AArch64InstPrinter::getRegisterName(RegToPrint, AltName);
629 return false;
630 }
631
632 bool AArch64AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
633 const char *ExtraCode, raw_ostream &O) {
634 const MachineOperand &MO = MI->getOperand(OpNum);
635
636 // First try the generic code, which knows about modifiers like 'c' and 'n'.
637 if (!AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O))
638 return false;
639
640 // Does this asm operand have a single letter operand modifier?
641 if (ExtraCode && ExtraCode[0]) {
642 if (ExtraCode[1] != 0)
643 return true; // Unknown modifier.
644
645 switch (ExtraCode[0]) {
646 default:
647 return true; // Unknown modifier.
648 case 'w': // Print W register
649 case 'x': // Print X register
650 if (MO.isReg())
651 return printAsmMRegister(MO, ExtraCode[0], O);
652 if (MO.isImm() && MO.getImm() == 0) {
653 unsigned Reg = ExtraCode[0] == 'w' ? AArch64::WZR : AArch64::XZR;
654 O << AArch64InstPrinter::getRegisterName(Reg);
655 return false;
656 }
657 printOperand(MI, OpNum, O);
658 return false;
659 case 'b': // Print B register.
660 case 'h': // Print H register.
661 case 's': // Print S register.
662 case 'd': // Print D register.
663 case 'q': // Print Q register.
664 case 'z': // Print Z register.
665 if (MO.isReg()) {
666 const TargetRegisterClass *RC;
667 switch (ExtraCode[0]) {
668 case 'b':
669 RC = &AArch64::FPR8RegClass;
670 break;
671 case 'h':
672 RC = &AArch64::FPR16RegClass;
673 break;
674 case 's':
675 RC = &AArch64::FPR32RegClass;
676 break;
677 case 'd':
678 RC = &AArch64::FPR64RegClass;
679 break;
680 case 'q':
681 RC = &AArch64::FPR128RegClass;
682 break;
683 case 'z':
684 RC = &AArch64::ZPRRegClass;
685 break;
686 default:
687 return true;
688 }
689 return printAsmRegInClass(MO, RC, AArch64::NoRegAltName, O);
690 }
691 printOperand(MI, OpNum, O);
692 return false;
693 }
694 }
695
696 // According to ARM, we should emit x and v registers unless we have a
697 // modifier.
698 if (MO.isReg()) {
699 Register Reg = MO.getReg();
700
701 // If this is a w or x register, print an x register.
702 if (AArch64::GPR32allRegClass.contains(Reg) ||
703 AArch64::GPR64allRegClass.contains(Reg))
704 return printAsmMRegister(MO, 'x', O);
705
706 unsigned AltName = AArch64::NoRegAltName;
707 const TargetRegisterClass *RegClass;
708 if (AArch64::ZPRRegClass.contains(Reg)) {
709 RegClass = &AArch64::ZPRRegClass;
710 } else if (AArch64::PPRRegClass.contains(Reg)) {
711 RegClass = &AArch64::PPRRegClass;
712 } else {
713 RegClass = &AArch64::FPR128RegClass;
714 AltName = AArch64::vreg;
715 }
716
717 // If this is a b, h, s, d, or q register, print it as a v register.
718 return printAsmRegInClass(MO, RegClass, AltName, O);
719 }
720
721 printOperand(MI, OpNum, O);
722 return false;
723 }
724
725 bool AArch64AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
726 unsigned OpNum,
727 const char *ExtraCode,
728 raw_ostream &O) {
729 if (ExtraCode && ExtraCode[0] && ExtraCode[0] != 'a')
730 return true; // Unknown modifier.
731
732 const MachineOperand &MO = MI->getOperand(OpNum);
733 assert(MO.isReg() && "unexpected inline asm memory operand");
734 O << "[" << AArch64InstPrinter::getRegisterName(MO.getReg()) << "]";
735 return false;
736 }
737
738 void AArch64AsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
739 raw_ostream &OS) {
740 unsigned NOps = MI->getNumOperands();
741 assert(NOps == 4);
742 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
743 // cast away const; DIetc do not take const operands for some reason.
744 OS << cast<DILocalVariable>(MI->getOperand(NOps - 2).getMetadata())
745 ->getName();
746 OS << " <- ";
747 // Frame address. Currently handles register +- offset only.
748 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
749 OS << '[';
750 printOperand(MI, 0, OS);
751 OS << '+';
752 printOperand(MI, 1, OS);
753 OS << ']';
754 OS << "+";
755 printOperand(MI, NOps - 2, OS);
756 }
757
758 void AArch64AsmPrinter::EmitJumpTableInfo() {
759 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
760 if (!MJTI) return;
761
762 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
763 if (JT.empty()) return;
764
765 const Function &F = MF->getFunction();
766 const TargetLoweringObjectFile &TLOF = getObjFileLowering();
767 bool JTInDiffSection =
768 !STI->isTargetCOFF() ||
769 !TLOF.shouldPutJumpTableInFunctionSection(
770 MJTI->getEntryKind() == MachineJumpTableInfo::EK_LabelDifference32,
771 F);
772 if (JTInDiffSection) {
773 // Drop it in the readonly section.
774 MCSection *ReadOnlySec = TLOF.getSectionForJumpTable(F, TM);
775 OutStreamer->SwitchSection(ReadOnlySec);
776 }
777
778 auto AFI = MF->getInfo<AArch64FunctionInfo>();
779 for (unsigned JTI = 0, e = JT.size(); JTI != e; ++JTI) {
780 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
781
782 // If this jump table was deleted, ignore it.
783 if (JTBBs.empty()) continue;
784
785 unsigned Size = AFI->getJumpTableEntrySize(JTI);
786 EmitAlignment(Align(Size));
787 OutStreamer->EmitLabel(GetJTISymbol(JTI));
788
789 for (auto *JTBB : JTBBs)
790 emitJumpTableEntry(MJTI, JTBB, JTI);
791 }
792 }
793
794 void AArch64AsmPrinter::emitJumpTableEntry(const MachineJumpTableInfo *MJTI,
795 const MachineBasicBlock *MBB,
796 unsigned JTI) {
797 const MCExpr *Value = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
798 auto AFI = MF->getInfo<AArch64FunctionInfo>();
799 unsigned Size = AFI->getJumpTableEntrySize(JTI);
800
801 if (Size == 4) {
802 // .word LBB - LJTI
803 const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
804 const MCExpr *Base = TLI->getPICJumpTableRelocBaseExpr(MF, JTI, OutContext);
805 Value = MCBinaryExpr::createSub(Value, Base, OutContext);
806 } else {
807 // .byte (LBB - LBB) >> 2 (or .hword)
808 const MCSymbol *BaseSym = AFI->getJumpTableEntryPCRelSymbol(JTI);
809 const MCExpr *Base = MCSymbolRefExpr::create(BaseSym, OutContext);
810 Value = MCBinaryExpr::createSub(Value, Base, OutContext);
811 Value = MCBinaryExpr::createLShr(
812 Value, MCConstantExpr::create(2, OutContext), OutContext);
813 }
814
815 OutStreamer->EmitValue(Value, Size);
816 }
817
818 /// Small jump tables contain an unsigned byte or half, representing the offset
819 /// from the lowest-addressed possible destination to the desired basic
820 /// block. Since all instructions are 4-byte aligned, this is further compressed
821 /// by counting in instructions rather than bytes (i.e. divided by 4). So, to
822 /// materialize the correct destination we need:
823 ///
824 /// adr xDest, .LBB0_0
825 /// ldrb wScratch, [xTable, xEntry] (with "lsl #1" for ldrh).
826 /// add xDest, xDest, xScratch, lsl #2
827 void AArch64AsmPrinter::LowerJumpTableDestSmall(llvm::MCStreamer &OutStreamer,
828 const llvm::MachineInstr &MI) {
829 Register DestReg = MI.getOperand(0).getReg();
830 Register ScratchReg = MI.getOperand(1).getReg();
831 Register ScratchRegW =
832 STI->getRegisterInfo()->getSubReg(ScratchReg, AArch64::sub_32);
833 Register TableReg = MI.getOperand(2).getReg();
834 Register EntryReg = MI.getOperand(3).getReg();
835 int JTIdx = MI.getOperand(4).getIndex();
836 bool IsByteEntry = MI.getOpcode() == AArch64::JumpTableDest8;
837
838 // This has to be first because the compression pass based its reachability
839 // calculations on the start of the JumpTableDest instruction.
840 auto Label =
841 MF->getInfo<AArch64FunctionInfo>()->getJumpTableEntryPCRelSymbol(JTIdx);
842 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::ADR)
843 .addReg(DestReg)
844 .addExpr(MCSymbolRefExpr::create(
845 Label, MF->getContext())));
846
847 // Load the number of instruction-steps to offset from the label.
848 unsigned LdrOpcode = IsByteEntry ? AArch64::LDRBBroX : AArch64::LDRHHroX;
849 EmitToStreamer(OutStreamer, MCInstBuilder(LdrOpcode)
850 .addReg(ScratchRegW)
851 .addReg(TableReg)
852 .addReg(EntryReg)
853 .addImm(0)
854 .addImm(IsByteEntry ? 0 : 1));
855
856 // Multiply the steps by 4 and add to the already materialized base label
857 // address.
858 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::ADDXrs)
859 .addReg(DestReg)
860 .addReg(DestReg)
861 .addReg(ScratchReg)
862 .addImm(2));
863 }
864
865 void AArch64AsmPrinter::LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
866 const MachineInstr &MI) {
867 unsigned NumNOPBytes = StackMapOpers(&MI).getNumPatchBytes();
868
869 auto &Ctx = OutStreamer.getContext();
870 MCSymbol *MILabel = Ctx.createTempSymbol();
871 OutStreamer.EmitLabel(MILabel);
872
873 SM.recordStackMap(*MILabel, MI);
874 assert(NumNOPBytes % 4 == 0 && "Invalid number of NOP bytes requested!");
875
876 // Scan ahead to trim the shadow.
877 const MachineBasicBlock &MBB = *MI.getParent();
878 MachineBasicBlock::const_iterator MII(MI);
879 ++MII;
880 while (NumNOPBytes > 0) {
881 if (MII == MBB.end() || MII->isCall() ||
882 MII->getOpcode() == AArch64::DBG_VALUE ||
883 MII->getOpcode() == TargetOpcode::PATCHPOINT ||
884 MII->getOpcode() == TargetOpcode::STACKMAP)
885 break;
886 ++MII;
887 NumNOPBytes -= 4;
888 }
889
890 // Emit nops.
891 for (unsigned i = 0; i < NumNOPBytes; i += 4)
892 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
893 }
894
895 // Lower a patchpoint of the form:
896 // [<def>], <id>, <numBytes>, <target>, <numArgs>
897 void AArch64AsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
898 const MachineInstr &MI) {
899 auto &Ctx = OutStreamer.getContext();
900 MCSymbol *MILabel = Ctx.createTempSymbol();
901 OutStreamer.EmitLabel(MILabel);
902 SM.recordPatchPoint(*MILabel, MI);
903
904 PatchPointOpers Opers(&MI);
905
906 int64_t CallTarget = Opers.getCallTarget().getImm();
907 unsigned EncodedBytes = 0;
908 if (CallTarget) {
909 assert((CallTarget & 0xFFFFFFFFFFFF) == CallTarget &&
910 "High 16 bits of call target should be zero.");
911 Register ScratchReg = MI.getOperand(Opers.getNextScratchIdx()).getReg();
912 EncodedBytes = 16;
913 // Materialize the jump address:
914 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVZXi)
915 .addReg(ScratchReg)
916 .addImm((CallTarget >> 32) & 0xFFFF)
917 .addImm(32));
918 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKXi)
919 .addReg(ScratchReg)
920 .addReg(ScratchReg)
921 .addImm((CallTarget >> 16) & 0xFFFF)
922 .addImm(16));
923 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKXi)
924 .addReg(ScratchReg)
925 .addReg(ScratchReg)
926 .addImm(CallTarget & 0xFFFF)
927 .addImm(0));
928 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg));
929 }
930 // Emit padding.
931 unsigned NumBytes = Opers.getNumPatchBytes();
932 assert(NumBytes >= EncodedBytes &&
933 "Patchpoint can't request size less than the length of a call.");
934 assert((NumBytes - EncodedBytes) % 4 == 0 &&
935 "Invalid number of NOP bytes requested!");
936 for (unsigned i = EncodedBytes; i < NumBytes; i += 4)
937 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
938 }
939
940 void AArch64AsmPrinter::EmitFMov0(const MachineInstr &MI) {
941 Register DestReg = MI.getOperand(0).getReg();
942 if (STI->hasZeroCycleZeroingFP() && !STI->hasZeroCycleZeroingFPWorkaround()) {
943 // Convert H/S/D register to corresponding Q register
944 if (AArch64::H0 <= DestReg && DestReg <= AArch64::H31)
945 DestReg = AArch64::Q0 + (DestReg - AArch64::H0);
946 else if (AArch64::S0 <= DestReg && DestReg <= AArch64::S31)
947 DestReg = AArch64::Q0 + (DestReg - AArch64::S0);
948 else {
949 assert(AArch64::D0 <= DestReg && DestReg <= AArch64::D31);
950 DestReg = AArch64::Q0 + (DestReg - AArch64::D0);
951 }
952 MCInst MOVI;
953 MOVI.setOpcode(AArch64::MOVIv2d_ns);
954 MOVI.addOperand(MCOperand::createReg(DestReg));
955 MOVI.addOperand(MCOperand::createImm(0));
956 EmitToStreamer(*OutStreamer, MOVI);
957 } else {
958 MCInst FMov;
959 switch (MI.getOpcode()) {
960 default: llvm_unreachable("Unexpected opcode");
961 case AArch64::FMOVH0:
962 FMov.setOpcode(AArch64::FMOVWHr);
963 FMov.addOperand(MCOperand::createReg(DestReg));
964 FMov.addOperand(MCOperand::createReg(AArch64::WZR));
965 break;
966 case AArch64::FMOVS0:
967 FMov.setOpcode(AArch64::FMOVWSr);
968 FMov.addOperand(MCOperand::createReg(DestReg));
969 FMov.addOperand(MCOperand::createReg(AArch64::WZR));
970 break;
971 case AArch64::FMOVD0:
972 FMov.setOpcode(AArch64::FMOVXDr);
973 FMov.addOperand(MCOperand::createReg(DestReg));
974 FMov.addOperand(MCOperand::createReg(AArch64::XZR));
975 break;
976 }
977 EmitToStreamer(*OutStreamer, FMov);
978 }
979 }
980
981 // Simple pseudo-instructions have their lowering (with expansion to real
982 // instructions) auto-generated.
983 #include "AArch64GenMCPseudoLowering.inc"
984
985 void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) {
986 // Do any auto-generated pseudo lowerings.
987 if (emitPseudoExpansionLowering(*OutStreamer, MI))
988 return;
989
990 if (AArch64FI->getLOHRelated().count(MI)) {
991 // Generate a label for LOH related instruction
992 MCSymbol *LOHLabel = createTempSymbol("loh");
993 // Associate the instruction with the label
994 LOHInstToLabel[MI] = LOHLabel;
995 OutStreamer->EmitLabel(LOHLabel);
996 }
997
998 AArch64TargetStreamer *TS =
999 static_cast<AArch64TargetStreamer *>(OutStreamer->getTargetStreamer());
1000 // Do any manual lowerings.
1001 switch (MI->getOpcode()) {
1002 default:
1003 break;
1004 case AArch64::MOVMCSym: {
1005 Register DestReg = MI->getOperand(0).getReg();
1006 const MachineOperand &MO_Sym = MI->getOperand(1);
1007 MachineOperand Hi_MOSym(MO_Sym), Lo_MOSym(MO_Sym);
1008 MCOperand Hi_MCSym, Lo_MCSym;
1009
1010 Hi_MOSym.setTargetFlags(AArch64II::MO_G1 | AArch64II::MO_S);
1011 Lo_MOSym.setTargetFlags(AArch64II::MO_G0 | AArch64II::MO_NC);
1012
1013 MCInstLowering.lowerOperand(Hi_MOSym, Hi_MCSym);
1014 MCInstLowering.lowerOperand(Lo_MOSym, Lo_MCSym);
1015
1016 MCInst MovZ;
1017 MovZ.setOpcode(AArch64::MOVZXi);
1018 MovZ.addOperand(MCOperand::createReg(DestReg));
1019 MovZ.addOperand(Hi_MCSym);
1020 MovZ.addOperand(MCOperand::createImm(16));
1021 EmitToStreamer(*OutStreamer, MovZ);
1022
1023 MCInst MovK;
1024 MovK.setOpcode(AArch64::MOVKXi);
1025 MovK.addOperand(MCOperand::createReg(DestReg));
1026 MovK.addOperand(MCOperand::createReg(DestReg));
1027 MovK.addOperand(Lo_MCSym);
1028 MovK.addOperand(MCOperand::createImm(0));
1029 EmitToStreamer(*OutStreamer, MovK);
1030 return;
1031 }
1032 case AArch64::MOVIv2d_ns:
1033 // If the target has <rdar://problem/16473581>, lower this
1034 // instruction to movi.16b instead.
1035 if (STI->hasZeroCycleZeroingFPWorkaround() &&
1036 MI->getOperand(1).getImm() == 0) {
1037 MCInst TmpInst;
1038 TmpInst.setOpcode(AArch64::MOVIv16b_ns);
1039 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1040 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(1).getImm()));
1041 EmitToStreamer(*OutStreamer, TmpInst);
1042 return;
1043 }
1044 break;
1045
1046 case AArch64::DBG_VALUE: {
1047 if (isVerbose() && OutStreamer->hasRawTextSupport()) {
1048 SmallString<128> TmpStr;
1049 raw_svector_ostream OS(TmpStr);
1050 PrintDebugValueComment(MI, OS);
1051 OutStreamer->EmitRawText(StringRef(OS.str()));
1052 }
1053 return;
1054
1055 case AArch64::EMITBKEY: {
1056 ExceptionHandling ExceptionHandlingType = MAI->getExceptionHandlingType();
1057 if (ExceptionHandlingType != ExceptionHandling::DwarfCFI &&
1058 ExceptionHandlingType != ExceptionHandling::ARM)
1059 return;
1060
1061 if (needsCFIMoves() == CFI_M_None)
1062 return;
1063
1064 OutStreamer->EmitCFIBKeyFrame();
1065 return;
1066 }
1067 }
1068
1069 // Tail calls use pseudo instructions so they have the proper code-gen
1070 // attributes (isCall, isReturn, etc.). We lower them to the real
1071 // instruction here.
1072 case AArch64::TCRETURNri:
1073 case AArch64::TCRETURNriBTI:
1074 case AArch64::TCRETURNriALL: {
1075 MCInst TmpInst;
1076 TmpInst.setOpcode(AArch64::BR);
1077 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1078 EmitToStreamer(*OutStreamer, TmpInst);
1079 return;
1080 }
1081 case AArch64::TCRETURNdi: {
1082 MCOperand Dest;
1083 MCInstLowering.lowerOperand(MI->getOperand(0), Dest);
1084 MCInst TmpInst;
1085 TmpInst.setOpcode(AArch64::B);
1086 TmpInst.addOperand(Dest);
1087 EmitToStreamer(*OutStreamer, TmpInst);
1088 return;
1089 }
1090 case AArch64::TLSDESC_CALLSEQ: {
1091 /// lower this to:
1092 /// adrp x0, :tlsdesc:var
1093 /// ldr x1, [x0, #:tlsdesc_lo12:var]
1094 /// add x0, x0, #:tlsdesc_lo12:var
1095 /// .tlsdesccall var
1096 /// blr x1
1097 /// (TPIDR_EL0 offset now in x0)
1098 const MachineOperand &MO_Sym = MI->getOperand(0);
1099 MachineOperand MO_TLSDESC_LO12(MO_Sym), MO_TLSDESC(MO_Sym);
1100 MCOperand Sym, SymTLSDescLo12, SymTLSDesc;
1101 MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGEOFF);
1102 MO_TLSDESC.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGE);
1103 MCInstLowering.lowerOperand(MO_Sym, Sym);
1104 MCInstLowering.lowerOperand(MO_TLSDESC_LO12, SymTLSDescLo12);
1105 MCInstLowering.lowerOperand(MO_TLSDESC, SymTLSDesc);
1106
1107 MCInst Adrp;
1108 Adrp.setOpcode(AArch64::ADRP);
1109 Adrp.addOperand(MCOperand::createReg(AArch64::X0));
1110 Adrp.addOperand(SymTLSDesc);
1111 EmitToStreamer(*OutStreamer, Adrp);
1112
1113 MCInst Ldr;
1114 Ldr.setOpcode(AArch64::LDRXui);
1115 Ldr.addOperand(MCOperand::createReg(AArch64::X1));
1116 Ldr.addOperand(MCOperand::createReg(AArch64::X0));
1117 Ldr.addOperand(SymTLSDescLo12);
1118 Ldr.addOperand(MCOperand::createImm(0));
1119 EmitToStreamer(*OutStreamer, Ldr);
1120
1121 MCInst Add;
1122 Add.setOpcode(AArch64::ADDXri);
1123 Add.addOperand(MCOperand::createReg(AArch64::X0));
1124 Add.addOperand(MCOperand::createReg(AArch64::X0));
1125 Add.addOperand(SymTLSDescLo12);
1126 Add.addOperand(MCOperand::createImm(AArch64_AM::getShiftValue(0)));
1127 EmitToStreamer(*OutStreamer, Add);
1128
1129 // Emit a relocation-annotation. This expands to no code, but requests
1130 // the following instruction gets an R_AARCH64_TLSDESC_CALL.
1131 MCInst TLSDescCall;
1132 TLSDescCall.setOpcode(AArch64::TLSDESCCALL);
1133 TLSDescCall.addOperand(Sym);
1134 EmitToStreamer(*OutStreamer, TLSDescCall);
1135
1136 MCInst Blr;
1137 Blr.setOpcode(AArch64::BLR);
1138 Blr.addOperand(MCOperand::createReg(AArch64::X1));
1139 EmitToStreamer(*OutStreamer, Blr);
1140
1141 return;
1142 }
1143
1144 case AArch64::JumpTableDest32: {
1145 // We want:
1146 // ldrsw xScratch, [xTable, xEntry, lsl #2]
1147 // add xDest, xTable, xScratch
1148 unsigned DestReg = MI->getOperand(0).getReg(),
1149 ScratchReg = MI->getOperand(1).getReg(),
1150 TableReg = MI->getOperand(2).getReg(),
1151 EntryReg = MI->getOperand(3).getReg();
1152 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::LDRSWroX)
1153 .addReg(ScratchReg)
1154 .addReg(TableReg)
1155 .addReg(EntryReg)
1156 .addImm(0)
1157 .addImm(1));
1158 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::ADDXrs)
1159 .addReg(DestReg)
1160 .addReg(TableReg)
1161 .addReg(ScratchReg)
1162 .addImm(0));
1163 return;
1164 }
1165 case AArch64::JumpTableDest16:
1166 case AArch64::JumpTableDest8:
1167 LowerJumpTableDestSmall(*OutStreamer, *MI);
1168 return;
1169
1170 case AArch64::FMOVH0:
1171 case AArch64::FMOVS0:
1172 case AArch64::FMOVD0:
1173 EmitFMov0(*MI);
1174 return;
1175
1176 case TargetOpcode::STACKMAP:
1177 return LowerSTACKMAP(*OutStreamer, SM, *MI);
1178
1179 case TargetOpcode::PATCHPOINT:
1180 return LowerPATCHPOINT(*OutStreamer, SM, *MI);
1181
1182 case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
1183 LowerPATCHABLE_FUNCTION_ENTER(*MI);
1184 return;
1185
1186 case TargetOpcode::PATCHABLE_FUNCTION_EXIT:
1187 LowerPATCHABLE_FUNCTION_EXIT(*MI);
1188 return;
1189
1190 case TargetOpcode::PATCHABLE_TAIL_CALL:
1191 LowerPATCHABLE_TAIL_CALL(*MI);
1192 return;
1193
1194 case AArch64::HWASAN_CHECK_MEMACCESS:
1195 case AArch64::HWASAN_CHECK_MEMACCESS_SHORTGRANULES:
1196 LowerHWASAN_CHECK_MEMACCESS(*MI);
1197 return;
1198
1199 case AArch64::SEH_StackAlloc:
1200 TS->EmitARM64WinCFIAllocStack(MI->getOperand(0).getImm());
1201 return;
1202
1203 case AArch64::SEH_SaveFPLR:
1204 TS->EmitARM64WinCFISaveFPLR(MI->getOperand(0).getImm());
1205 return;
1206
1207 case AArch64::SEH_SaveFPLR_X:
1208 assert(MI->getOperand(0).getImm() < 0 &&
1209 "Pre increment SEH opcode must have a negative offset");
1210 TS->EmitARM64WinCFISaveFPLRX(-MI->getOperand(0).getImm());
1211 return;
1212
1213 case AArch64::SEH_SaveReg:
1214 TS->EmitARM64WinCFISaveReg(MI->getOperand(0).getImm(),
1215 MI->getOperand(1).getImm());
1216 return;
1217
1218 case AArch64::SEH_SaveReg_X:
1219 assert(MI->getOperand(1).getImm() < 0 &&
1220 "Pre increment SEH opcode must have a negative offset");
1221 TS->EmitARM64WinCFISaveRegX(MI->getOperand(0).getImm(),
1222 -MI->getOperand(1).getImm());
1223 return;
1224
1225 case AArch64::SEH_SaveRegP:
1226 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
1227 "Non-consecutive registers not allowed for save_regp");
1228 TS->EmitARM64WinCFISaveRegP(MI->getOperand(0).getImm(),
1229 MI->getOperand(2).getImm());
1230 return;
1231
1232 case AArch64::SEH_SaveRegP_X:
1233 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
1234 "Non-consecutive registers not allowed for save_regp_x");
1235 assert(MI->getOperand(2).getImm() < 0 &&
1236 "Pre increment SEH opcode must have a negative offset");
1237 TS->EmitARM64WinCFISaveRegPX(MI->getOperand(0).getImm(),
1238 -MI->getOperand(2).getImm());
1239 return;
1240
1241 case AArch64::SEH_SaveFReg:
1242 TS->EmitARM64WinCFISaveFReg(MI->getOperand(0).getImm(),
1243 MI->getOperand(1).getImm());
1244 return;
1245
1246 case AArch64::SEH_SaveFReg_X:
1247 assert(MI->getOperand(1).getImm() < 0 &&
1248 "Pre increment SEH opcode must have a negative offset");
1249 TS->EmitARM64WinCFISaveFRegX(MI->getOperand(0).getImm(),
1250 -MI->getOperand(1).getImm());
1251 return;
1252
1253 case AArch64::SEH_SaveFRegP:
1254 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
1255 "Non-consecutive registers not allowed for save_regp");
1256 TS->EmitARM64WinCFISaveFRegP(MI->getOperand(0).getImm(),
1257 MI->getOperand(2).getImm());
1258 return;
1259
1260 case AArch64::SEH_SaveFRegP_X:
1261 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
1262 "Non-consecutive registers not allowed for save_regp_x");
1263 assert(MI->getOperand(2).getImm() < 0 &&
1264 "Pre increment SEH opcode must have a negative offset");
1265 TS->EmitARM64WinCFISaveFRegPX(MI->getOperand(0).getImm(),
1266 -MI->getOperand(2).getImm());
1267 return;
1268
1269 case AArch64::SEH_SetFP:
1270 TS->EmitARM64WinCFISetFP();
1271 return;
1272
1273 case AArch64::SEH_AddFP:
1274 TS->EmitARM64WinCFIAddFP(MI->getOperand(0).getImm());
1275 return;
1276
1277 case AArch64::SEH_Nop:
1278 TS->EmitARM64WinCFINop();
1279 return;
1280
1281 case AArch64::SEH_PrologEnd:
1282 TS->EmitARM64WinCFIPrologEnd();
1283 return;
1284
1285 case AArch64::SEH_EpilogStart:
1286 TS->EmitARM64WinCFIEpilogStart();
1287 return;
1288
1289 case AArch64::SEH_EpilogEnd:
1290 TS->EmitARM64WinCFIEpilogEnd();
1291 return;
1292 }
1293
1294 // Finally, do the automated lowerings for everything else.
1295 MCInst TmpInst;
1296 MCInstLowering.Lower(MI, TmpInst);
1297 EmitToStreamer(*OutStreamer, TmpInst);
1298 }
1299
1300 // Force static initialization.
1301 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64AsmPrinter() {
1302 RegisterAsmPrinter<AArch64AsmPrinter> X(getTheAArch64leTarget());
1303 RegisterAsmPrinter<AArch64AsmPrinter> Y(getTheAArch64beTarget());
1304 RegisterAsmPrinter<AArch64AsmPrinter> Z(getTheARM64Target());
1305 RegisterAsmPrinter<AArch64AsmPrinter> W(getTheARM64_32Target());
1306 RegisterAsmPrinter<AArch64AsmPrinter> V(getTheAArch64_32Target());
1307 }
LLVM monorepo