llvm/lib/Target/AArch64/AArch64SchedExynosM3.td

   1 //=- AArch64SchedExynosM3.td - Samsung Exynos M3 Sched Defs --*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the machine model for the Samsung Exynos M3 to support
  10 // instruction scheduling and other instruction cost heuristics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // The Exynos-M3 is an advanced superscalar microprocessor with a 6-wide
  16 // in-order stage for decode and dispatch and a wider issue stage.
  17 // The execution units and loads and stores are out-of-order.
  18
  19 def ExynosM3Model : SchedMachineModel {
  20   let IssueWidth            =   6; // Up to 6 uops per cycle.
  21   let MicroOpBufferSize     = 228; // ROB size.
  22   let LoopMicroOpBufferSize =  40; // Based on the instruction queue size.
  23   let LoadLatency           =   4; // Optimistic load cases.
  24   let MispredictPenalty     =  16; // Minimum branch misprediction penalty.
  25   let CompleteModel         =   1; // Use the default model otherwise.
  26
  27   list<Predicate> UnsupportedFeatures = SVEUnsupported.F;
  28 }
  29
  30 //===----------------------------------------------------------------------===//
  31 // Define each kind of processor resource and number available on the Exynos-M3,
  32 // which has 12 pipelines, each with its own queue with out-of-order dispatch.
  33
  34 let SchedModel = ExynosM3Model in {
  35
  36 def M3UnitA  : ProcResource<2>; // Simple integer
  37 def M3UnitC  : ProcResource<2>; // Simple and complex integer
  38 def M3UnitD  : ProcResource<1>; // Integer division (inside C0, serialized)
  39 def M3UnitB  : ProcResource<2>; // Branch
  40 def M3UnitL  : ProcResource<2>; // Load
  41 def M3UnitS  : ProcResource<1>; // Store
  42 def M3PipeF0 : ProcResource<1>; // FP #0
  43 let Super = M3PipeF0 in {
  44   def M3UnitFMAC0 : ProcResource<1>; // FP multiplication
  45   def M3UnitFADD0 : ProcResource<1>; // Simple FP
  46   def M3UnitFCVT0 : ProcResource<1>; // FP conversion
  47   def M3UnitFSQR  : ProcResource<2>; // FP square root (serialized)
  48   def M3UnitNALU0 : ProcResource<1>; // Simple vector
  49   def M3UnitNMSC  : ProcResource<1>; // FP and vector miscellanea
  50   def M3UnitNSHT0 : ProcResource<1>; // Vector shifting
  51   def M3UnitNSHF0 : ProcResource<1>; // Vector shuffling
  52 }
  53 def M3PipeF1 : ProcResource<1>; // FP #1
  54 let Super = M3PipeF1 in {
  55   def M3UnitFMAC1 : ProcResource<1>; // FP multiplication
  56   def M3UnitFADD1 : ProcResource<1>; // Simple FP
  57   def M3UnitFDIV0 : ProcResource<2>; // FP division (serialized)
  58   def M3UnitFCVT1 : ProcResource<1>; // FP conversion
  59   def M3UnitFST0  : ProcResource<1>; // FP store
  60   def M3UnitNALU1 : ProcResource<1>; // Simple vector
  61   def M3UnitNCRY0 : ProcResource<1>; // Cryptographic
  62   def M3UnitNMUL  : ProcResource<1>; // Vector multiplication
  63   def M3UnitNSHT1 : ProcResource<1>; // Vector shifting
  64   def M3UnitNSHF1 : ProcResource<1>; // Vector shuffling
  65 }
  66 def M3PipeF2 : ProcResource<1>; // FP #2
  67 let Super = M3PipeF2 in {
  68   def M3UnitFMAC2 : ProcResource<1>; // FP multiplication
  69   def M3UnitFADD2 : ProcResource<1>; // Simple FP
  70   def M3UnitFDIV1 : ProcResource<2>; // FP division (serialized)
  71   def M3UnitFST1  : ProcResource<1>; // FP store
  72   def M3UnitNALU2 : ProcResource<1>; // Simple vector
  73   def M3UnitNCRY1 : ProcResource<1>; // Cryptographic
  74   def M3UnitNSHT2 : ProcResource<1>; // Vector shifting
  75   def M3UnitNSHF2 : ProcResource<1>; // Vector shuffling
  76 }
  77
  78
  79 def M3UnitALU  : ProcResGroup<[M3UnitA,
  80                                M3UnitC]>;
  81 def M3UnitFMAC : ProcResGroup<[M3UnitFMAC0,
  82                                M3UnitFMAC1,
  83                                M3UnitFMAC2]>;
  84 def M3UnitFADD : ProcResGroup<[M3UnitFADD0,
  85                                M3UnitFADD1,
  86                                M3UnitFADD2]>;
  87 def M3UnitFDIV : ProcResGroup<[M3UnitFDIV0,
  88                                M3UnitFDIV1]>;
  89 def M3UnitFCVT : ProcResGroup<[M3UnitFCVT0,
  90                                M3UnitFCVT1]>;
  91 def M3UnitFST  : ProcResGroup<[M3UnitFST0,
  92                                M3UnitFST1]>;
  93 def M3UnitNALU : ProcResGroup<[M3UnitNALU0,
  94                                M3UnitNALU1,
  95                                M3UnitNALU2]>;
  96 def M3UnitNCRY : ProcResGroup<[M3UnitNCRY0,
  97                                M3UnitNCRY1]>;
  98 def M3UnitNSHT : ProcResGroup<[M3UnitNSHT0,
  99                                M3UnitNSHT1,
 100                                M3UnitNSHT2]>;
 101 def M3UnitNSHF : ProcResGroup<[M3UnitNSHF0,
 102                                M3UnitNSHF1,
 103                                M3UnitNSHF2]>;
 104
 105 //===----------------------------------------------------------------------===//
 106 // Coarse scheduling model.
 107
 108 def M3WriteZ0 : SchedWriteRes<[]> { let Latency = 0;
 109                                     let NumMicroOps = 1; }
 110 def M3WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
 111                                     let NumMicroOps = 0; }
 112
 113 def M3WriteA1 : SchedWriteRes<[M3UnitALU]> { let Latency = 1; }
 114 def M3WriteAA : SchedWriteRes<[M3UnitALU]> { let Latency = 2;
 115                                              let ResourceCycles = [2]; }
 116 def M3WriteAB : SchedWriteRes<[M3UnitALU,
 117                                M3UnitC]>   { let Latency = 1;
 118                                              let NumMicroOps = 2; }
 119 def M3WriteAC : SchedWriteRes<[M3UnitALU,
 120                                M3UnitALU,
 121                                M3UnitC]>   { let Latency = 2;
 122                                              let NumMicroOps = 3; }
 123 def M3WriteAD : SchedWriteRes<[M3UnitALU,
 124                                M3UnitC]>   { let Latency = 2;
 125                                              let NumMicroOps = 2; }
 126 def M3WriteC1 : SchedWriteRes<[M3UnitC]>   { let Latency = 1; }
 127 def M3WriteC2 : SchedWriteRes<[M3UnitC]>   { let Latency = 2; }
 128 def M3WriteAU : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M3WriteZ0]>,
 129                                    SchedVar<ExynosArithPred, [M3WriteA1]>,
 130                                    SchedVar<ExynosLogicPred, [M3WriteA1]>,
 131                                    SchedVar<NoSchedPred,     [M3WriteAA]>]>;
 132 def M3WriteAV : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M3WriteZ0]>,
 133                                    SchedVar<ExynosArithPred, [M3WriteA1]>,
 134                                    SchedVar<NoSchedPred,     [M3WriteAA]>]>;
 135 def M3WriteAW : SchedWriteVariant<[SchedVar<IsZeroIdiomPred, [M3WriteZ0]>,
 136                                    SchedVar<ExynosLogicPred, [M3WriteA1]>,
 137                                    SchedVar<NoSchedPred,     [M3WriteAA]>]>;
 138 def M3WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M3WriteA1]>,
 139                                    SchedVar<ExynosLogicPred, [M3WriteA1]>,
 140                                    SchedVar<NoSchedPred,     [M3WriteAA]>]>;
 141 def M3WriteAY : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M3WriteA1]>,
 142                                    SchedVar<NoSchedPred,              [M3WriteAA]>]>;
 143
 144 def M3WriteB1 : SchedWriteRes<[M3UnitB]> { let Latency = 1; }
 145 def M3WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M3WriteAC]>,
 146                                    SchedVar<NoSchedPred,            [M3WriteAB]>]>;
 147
 148 def M3WriteL4 : SchedWriteRes<[M3UnitL]> { let Latency = 4; }
 149 def M3WriteL5 : SchedWriteRes<[M3UnitL]> { let Latency = 5; }
 150 def M3WriteLA : SchedWriteRes<[M3UnitL,
 151                                M3UnitL]> { let Latency = 5;
 152                                            let NumMicroOps = 1; }
 153 def M3WriteLB : SchedWriteRes<[M3UnitA,
 154                                M3UnitL]> { let Latency = 5;
 155                                            let NumMicroOps = 2; }
 156 def M3WriteLC : SchedWriteRes<[M3UnitA,
 157                                M3UnitL,
 158                                M3UnitL]> { let Latency = 5;
 159                                            let NumMicroOps = 2; }
 160 def M3WriteLD : SchedWriteRes<[M3UnitA,
 161                                M3UnitL]> { let Latency = 4;
 162                                            let NumMicroOps = 2; }
 163 def M3WriteLE : SchedWriteRes<[M3UnitA,
 164                                M3UnitL]> { let Latency = 6;
 165                                            let NumMicroOps = 2; }
 166 def M3WriteLH : SchedWriteRes<[]>        { let Latency = 5;
 167                                            let NumMicroOps = 0; }
 168 def M3WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteL5]>,
 169                                    SchedVar<NoSchedPred,         [M3WriteL4]>]>;
 170 def M3WriteLY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteLE]>,
 171                                    SchedVar<NoSchedPred,         [M3WriteL5]>]>;
 172
 173 def M3WriteS1 : SchedWriteRes<[M3UnitS]>   { let Latency = 1; }
 174 def M3WriteSA : SchedWriteRes<[M3UnitA,
 175                                M3UnitS,
 176                                M3UnitFST]> { let Latency = 3;
 177                                              let NumMicroOps = 2; }
 178 def M3WriteSB : SchedWriteRes<[M3UnitA,
 179                                M3UnitS]>   { let Latency = 2;
 180                                              let NumMicroOps = 2; }
 181 def M3WriteSC : SchedWriteRes<[M3UnitA,
 182                                M3UnitS,
 183                                M3UnitFST]> { let Latency = 1;
 184                                              let NumMicroOps = 2; }
 185 def M3WriteSY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteSA]>,
 186                                    SchedVar<NoSchedPred,         [WriteVST]>]>;
 187
 188 def M3ReadAdrBase : SchedReadVariant<[SchedVar<ExynosScaledIdxPred, [ReadDefault]>,
 189                                       SchedVar<NoSchedPred,         [ReadDefault]>]>;
 190
 191 // Branch instructions.
 192 def : SchedAlias<WriteBr, M3WriteZ0>;
 193 def : SchedAlias<WriteBrReg, M3WriteC1>;
 194
 195 // Arithmetic and logical integer instructions.
 196 def : SchedAlias<WriteI,     M3WriteA1>;
 197 def : SchedAlias<WriteISReg, M3WriteA1>;
 198 def : SchedAlias<WriteIEReg, M3WriteA1>;
 199 def : SchedAlias<WriteIS,    M3WriteA1>;
 200
 201 // Move instructions.
 202 def : SchedAlias<WriteImm, M3WriteA1>;
 203
 204 // Divide and multiply instructions.
 205 def : WriteRes<WriteID32, [M3UnitC,
 206                            M3UnitD]>  { let Latency = 12;
 207                                         let ResourceCycles = [1, 12]; }
 208 def : WriteRes<WriteID64, [M3UnitC,
 209                            M3UnitD]>  { let Latency = 21;
 210                                         let ResourceCycles = [1, 21]; }
 211 def : WriteRes<WriteIM32, [M3UnitC]>  { let Latency = 3; }
 212 def : WriteRes<WriteIM64, [M3UnitC]>  { let Latency = 4;
 213                                         let ResourceCycles = [2]; }
 214
 215 // Miscellaneous instructions.
 216 def : SchedAlias<WriteExtr, M3WriteAY>;
 217
 218 // Addressing modes.
 219 def : SchedAlias<WriteAdr,    M3WriteZ1>;
 220 def : SchedAlias<ReadAdrBase, M3ReadAdrBase>;
 221
 222 // Load instructions.
 223 def : SchedAlias<WriteLD, M3WriteL4>;
 224 def : WriteRes<WriteLDHi, []> { let Latency = 4;
 225                                 let NumMicroOps = 0; }
 226 def : SchedAlias<WriteLDIdx, M3WriteLB>;
 227
 228 // Store instructions.
 229 def : SchedAlias<WriteST,    M3WriteS1>;
 230 def : SchedAlias<WriteSTP,   M3WriteS1>;
 231 def : SchedAlias<WriteSTX,   M3WriteS1>;
 232 def : SchedAlias<WriteSTIdx, M3WriteSB>;
 233
 234 // FP data instructions.
 235 def : WriteRes<WriteF,    [M3UnitFADD]>  { let Latency = 2; }
 236 def : WriteRes<WriteFCmp, [M3UnitNMSC]>  { let Latency = 2; }
 237 def : WriteRes<WriteFDiv, [M3UnitFDIV]>  { let Latency = 12;
 238                                            let ResourceCycles = [12]; }
 239 def : WriteRes<WriteFMul, [M3UnitFMAC]>  { let Latency = 4; }
 240
 241 // FP miscellaneous instructions.
 242 def : WriteRes<WriteFCvt,  [M3UnitFCVT]> { let Latency = 3; }
 243 def : WriteRes<WriteFImm,  [M3UnitNALU]> { let Latency = 1; }
 244 def : WriteRes<WriteFCopy, [M3UnitNALU]> { let Latency = 1; }
 245
 246 // FP load instructions.
 247 def : SchedAlias<WriteVLD, M3WriteL5>;
 248
 249 // FP store instructions.
 250 def : WriteRes<WriteVST, [M3UnitS,
 251                           M3UnitFST]> { let Latency = 1;
 252                                         let NumMicroOps = 1; }
 253
 254 // ASIMD FP instructions.
 255 def : WriteRes<WriteV, [M3UnitNALU]> { let Latency = 3; }
 256
 257 // Other miscellaneous instructions.
 258 def : WriteRes<WriteAtomic,  []> { let Unsupported = 1; }
 259 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
 260 def : WriteRes<WriteHint,    []> { let Latency = 1; }
 261 def : WriteRes<WriteSys,     []> { let Latency = 1; }
 262
 263 //===----------------------------------------------------------------------===//
 264 // Generic fast forwarding.
 265
 266 // TODO: Add FP register forwarding rules.
 267
 268 def : ReadAdvance<ReadI,       0>;
 269 def : ReadAdvance<ReadISReg,   0>;
 270 def : ReadAdvance<ReadIEReg,   0>;
 271 def : ReadAdvance<ReadIM,      0>;
 272 // TODO: The forwarding for 32 bits actually saves 2 cycles.
 273 def : ReadAdvance<ReadIMA,     3, [WriteIM32, WriteIM64]>;
 274 def : ReadAdvance<ReadID,      0>;
 275 def : ReadAdvance<ReadExtrHi,  0>;
 276 def : ReadAdvance<ReadAdrBase, 0>;
 277 def : ReadAdvance<ReadVLD,     0>;
 278
 279 //===----------------------------------------------------------------------===//
 280 // Finer scheduling model.
 281
 282 def M3WriteNEONA   : SchedWriteRes<[M3UnitNSHF,
 283                                     M3UnitFADD]>  { let Latency = 3;
 284                                                     let NumMicroOps = 2; }
 285 def M3WriteNEONB   : SchedWriteRes<[M3UnitNALU,
 286                                     M3UnitFST]>   { let Latency = 10;
 287                                                     let NumMicroOps = 2; }
 288 def M3WriteNEOND   : SchedWriteRes<[M3UnitNSHF,
 289                                     M3UnitFST]>   { let Latency = 6;
 290                                                     let NumMicroOps = 2; }
 291 def M3WriteNEONH   : SchedWriteRes<[M3UnitNALU,
 292                                     M3UnitS]>     { let Latency = 5;
 293                                                     let NumMicroOps = 2; }
 294 def M3WriteNEONI   : SchedWriteRes<[M3UnitNSHF,
 295                                     M3UnitS]>     { let Latency = 5;
 296                                                     let NumMicroOps = 2; }
 297 def M3WriteNEONV   : SchedWriteRes<[M3UnitFDIV0,
 298                                     M3UnitFDIV1]>  { let Latency = 7;
 299                                                      let NumMicroOps = 2;
 300                                                      let ResourceCycles = [8, 8]; }
 301 def M3WriteNEONW   : SchedWriteRes<[M3UnitFDIV0,
 302                                     M3UnitFDIV1]>  { let Latency = 12;
 303                                                      let NumMicroOps = 2;
 304                                                      let ResourceCycles = [13, 13]; }
 305 def M3WriteNEONX   : SchedWriteRes<[M3UnitFSQR,
 306                                     M3UnitFSQR]>  { let Latency = 18;
 307                                                     let NumMicroOps = 2;
 308                                                     let ResourceCycles = [19, 19]; }
 309 def M3WriteNEONY   : SchedWriteRes<[M3UnitFSQR,
 310                                     M3UnitFSQR]>  { let Latency = 25;
 311                                                     let NumMicroOps = 2;
 312                                                     let ResourceCycles = [26, 26]; }
 313 def M3WriteNEONZ   : SchedWriteRes<[M3UnitNMSC,
 314                                     M3UnitNMSC]>  { let Latency = 5;
 315                                                     let NumMicroOps = 2; }
 316 def M3WriteFADD2   : SchedWriteRes<[M3UnitFADD]>  { let Latency = 2; }
 317 def M3WriteFCVT2   : SchedWriteRes<[M3UnitFCVT]>  { let Latency = 2; }
 318 def M3WriteFCVT3   : SchedWriteRes<[M3UnitFCVT]>  { let Latency = 3; }
 319 def M3WriteFCVT3A  : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 3; }
 320 def M3WriteFCVT4A  : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 4; }
 321 def M3WriteFCVT4   : SchedWriteRes<[M3UnitFCVT]>  { let Latency = 4; }
 322 def M3WriteFDIV10  : SchedWriteRes<[M3UnitFDIV]>  { let Latency = 7;
 323                                                     let ResourceCycles = [8]; }
 324 def M3WriteFDIV12  : SchedWriteRes<[M3UnitFDIV]>  { let Latency = 12;
 325                                                     let ResourceCycles = [13]; }
 326 def M3WriteFMAC3   : SchedWriteRes<[M3UnitFMAC]>  { let Latency = 3; }
 327 def M3WriteFMAC4   : SchedWriteRes<[M3UnitFMAC]>  { let Latency = 4; }
 328 def M3WriteFMAC5   : SchedWriteRes<[M3UnitFMAC]>  { let Latency = 5; }
 329 def M3WriteFSQR17  : SchedWriteRes<[M3UnitFSQR]>  { let Latency = 18;
 330                                                     let ResourceCycles = [19]; }
 331 def M3WriteFSQR25  : SchedWriteRes<[M3UnitFSQR]>  { let Latency = 25;
 332                                                     let ResourceCycles = [26]; }
 333 def M3WriteNALU1   : SchedWriteRes<[M3UnitNALU]>  { let Latency = 1; }
 334 def M3WriteNCRY1A  : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 1; }
 335 def M3WriteNCRY3A  : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 3; }
 336 def M3WriteNCRY5A  : SchedWriteRes<[M3UnitNCRY]>  { let Latency = 5; }
 337 def M3WriteNMSC1   : SchedWriteRes<[M3UnitNMSC]>  { let Latency = 1; }
 338 def M3WriteNMSC2   : SchedWriteRes<[M3UnitNMSC]>  { let Latency = 2; }
 339 def M3WriteNMSC3   : SchedWriteRes<[M3UnitNMSC]>  { let Latency = 3; }
 340 def M3WriteNMUL3   : SchedWriteRes<[M3UnitNMUL]>  { let Latency = 3; }
 341 def M3WriteNSHF1   : SchedWriteRes<[M3UnitNSHF]>  { let Latency = 1; }
 342 def M3WriteNSHF3   : SchedWriteRes<[M3UnitNSHF]>  { let Latency = 3; }
 343 def M3WriteNSHT1   : SchedWriteRes<[M3UnitNSHT]>  { let Latency = 1; }
 344 def M3WriteNSHT2   : SchedWriteRes<[M3UnitNSHT]>  { let Latency = 2; }
 345 def M3WriteNSHT3   : SchedWriteRes<[M3UnitNSHT]>  { let Latency = 3; }
 346 def M3WriteVLDA    : SchedWriteRes<[M3UnitL,
 347                                     M3UnitL]>     { let Latency = 5;
 348                                                     let NumMicroOps = 2; }
 349 def M3WriteVLDB    : SchedWriteRes<[M3UnitL,
 350                                     M3UnitL,
 351                                     M3UnitL]>     { let Latency = 6;
 352                                                     let NumMicroOps = 3; }
 353 def M3WriteVLDC    : SchedWriteRes<[M3UnitL,
 354                                     M3UnitL,
 355                                     M3UnitL,
 356                                     M3UnitL]>     { let Latency = 6;
 357                                                     let NumMicroOps = 4; }
 358 def M3WriteVLDD    : SchedWriteRes<[M3UnitL,
 359                                     M3UnitNALU]>  { let Latency = 7;
 360                                                     let NumMicroOps = 2;
 361                                                     let ResourceCycles = [2, 1]; }
 362 def M3WriteVLDE    : SchedWriteRes<[M3UnitL,
 363                                     M3UnitNALU]>  { let Latency = 6;
 364                                                     let NumMicroOps = 2;
 365                                                     let ResourceCycles = [2, 1]; }
 366 def M3WriteVLDF    : SchedWriteRes<[M3UnitL,
 367                                     M3UnitL]>     { let Latency = 10;
 368                                                     let NumMicroOps = 2;
 369                                                     let ResourceCycles = [5, 5]; }
 370 def M3WriteVLDG    : SchedWriteRes<[M3UnitL,
 371                                     M3UnitNALU,
 372                                     M3UnitNALU]>  { let Latency = 7;
 373                                                     let NumMicroOps = 3;
 374                                                     let ResourceCycles = [2, 1, 1]; }
 375 def M3WriteVLDH    : SchedWriteRes<[M3UnitL,
 376                                     M3UnitNALU,
 377                                     M3UnitNALU]>  { let Latency = 6;
 378                                                     let NumMicroOps = 3;
 379                                                     let ResourceCycles = [2, 1, 1]; }
 380 def M3WriteVLDI    : SchedWriteRes<[M3UnitL,
 381                                     M3UnitL,
 382                                     M3UnitL]>     { let Latency = 12;
 383                                                     let NumMicroOps = 3;
 384                                                     let ResourceCycles = [6, 6, 6]; }
 385 def M3WriteVLDJ    : SchedWriteRes<[M3UnitL,
 386                                     M3UnitNALU,
 387                                     M3UnitNALU,
 388                                     M3UnitNALU]>  { let Latency = 7;
 389                                                     let NumMicroOps = 4;
 390                                                     let ResourceCycles = [2, 1, 1, 1]; }
 391 def M3WriteVLDK    : SchedWriteRes<[M3UnitL,
 392                                     M3UnitNALU,
 393                                     M3UnitNALU,
 394                                     M3UnitNALU,
 395                                     M3UnitNALU]>  { let Latency = 9;
 396                                                     let NumMicroOps = 5;
 397                                                     let ResourceCycles = [4, 1, 1, 1, 1]; }
 398 def M3WriteVLDL    : SchedWriteRes<[M3UnitL,
 399                                     M3UnitNALU,
 400                                     M3UnitNALU,
 401                                     M3UnitL,
 402                                     M3UnitNALU]>  { let Latency = 6;
 403                                                     let NumMicroOps = 5;
 404                                                     let ResourceCycles = [6, 1, 1, 6, 1]; }
 405 def M3WriteVLDM    : SchedWriteRes<[M3UnitL,
 406                                     M3UnitNALU,
 407                                     M3UnitNALU,
 408                                     M3UnitL,
 409                                     M3UnitNALU,
 410                                     M3UnitNALU]>  { let Latency = 7;
 411                                                     let NumMicroOps = 6;
 412                                                     let ResourceCycles = [6, 1, 1, 6, 1, 1]; }
 413 def M3WriteVLDN    : SchedWriteRes<[M3UnitL,
 414                                     M3UnitL,
 415                                     M3UnitL,
 416                                     M3UnitL]>     { let Latency = 14;
 417                                                     let NumMicroOps = 4;
 418                                                     let ResourceCycles = [6, 6, 6, 6]; }
 419 def M3WriteVSTA    : WriteSequence<[WriteVST], 2>;
 420 def M3WriteVSTB    : WriteSequence<[WriteVST], 3>;
 421 def M3WriteVSTC    : WriteSequence<[WriteVST], 4>;
 422 def M3WriteVSTD    : SchedWriteRes<[M3UnitS,
 423                                     M3UnitFST,
 424                                     M3UnitS,
 425                                     M3UnitFST]>   { let Latency = 7;
 426                                                     let NumMicroOps = 4;
 427                                                     let ResourceCycles = [1, 3, 1, 3]; }
 428 def M3WriteVSTE    : SchedWriteRes<[M3UnitS,
 429                                     M3UnitFST,
 430                                     M3UnitS,
 431                                     M3UnitFST,
 432                                     M3UnitS,
 433                                     M3UnitFST]>   { let Latency = 8;
 434                                                     let NumMicroOps = 6;
 435                                                     let ResourceCycles = [1, 3, 1, 3, 1, 3]; }
 436 def M3WriteVSTF    : SchedWriteRes<[M3UnitNALU,
 437                                     M3UnitFST,
 438                                     M3UnitFST,
 439                                     M3UnitS,
 440                                     M3UnitFST,
 441                                     M3UnitS,
 442                                     M3UnitFST]>   { let Latency = 15;
 443                                                     let NumMicroOps = 7;
 444                                                     let ResourceCycles = [1, 3, 3, 1, 3, 1, 3]; }
 445 def M3WriteVSTG    : SchedWriteRes<[M3UnitNALU,
 446                                     M3UnitFST,
 447                                     M3UnitFST,
 448                                     M3UnitS,
 449                                     M3UnitFST,
 450                                     M3UnitS,
 451                                     M3UnitFST,
 452                                     M3UnitS,
 453                                     M3UnitFST]>   { let Latency = 16;
 454                                                     let NumMicroOps = 9;
 455                                                     let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; }
 456 def M3WriteVSTH    : SchedWriteRes<[M3UnitNALU,
 457                                     M3UnitFST,
 458                                     M3UnitFST,
 459                                     M3UnitS,
 460                                     M3UnitFST]>   { let Latency = 14;
 461                                                     let NumMicroOps = 5;
 462                                                     let ResourceCycles = [1, 3, 3, 1, 3]; }
 463 def M3WriteVSTI    : SchedWriteRes<[M3UnitNALU,
 464                                     M3UnitFST,
 465                                     M3UnitFST,
 466                                     M3UnitS,
 467                                     M3UnitFST,
 468                                     M3UnitS,
 469                                     M3UnitFST,
 470                                     M3UnitS,
 471                                     M3UnitFST]>   { let Latency = 17;
 472                                                     let NumMicroOps = 9;
 473                                                     let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; }
 474
 475 // Special cases.
 476 def M3WriteAES     : SchedWriteRes<[M3UnitNCRY]>  { let Latency = 1; }
 477 def M3WriteCOPY    : SchedWriteVariant<[SchedVar<ExynosFPPred, [M3WriteNALU1]>,
 478                                         SchedVar<NoSchedPred,  [M3WriteZ0]>]>;
 479 def M3WriteMOVI    : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M3WriteZ0]>,
 480                                         SchedVar<NoSchedPred,       [M3WriteNALU1]>]>;
 481
 482 // Fast forwarding.
 483 def M3ReadAES      : SchedReadAdvance<1, [M3WriteAES]>;
 484 def M3ReadFMAC     : SchedReadAdvance<1, [M3WriteFMAC4,
 485                                           M3WriteFMAC5]>;
 486 def M3ReadNMUL     : SchedReadAdvance<1, [M3WriteNMUL3]>;
 487
 488 // Branch instructions
 489 def : InstRW<[M3WriteB1], (instrs Bcc)>;
 490 def : InstRW<[M3WriteA1], (instrs BL)>;
 491 def : InstRW<[M3WriteBX], (instrs BLR)>;
 492 def : InstRW<[M3WriteC1], (instregex "^CBN?Z[WX]")>;
 493 def : InstRW<[M3WriteAD], (instregex "^TBN?Z[WX]")>;
 494
 495 // Arithmetic and logical integer instructions.
 496 def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>;
 497 def : InstRW<[M3WriteAU], (instrs ORRWrs, ORRXrs)>;
 498 def : InstRW<[M3WriteAX], (instregex "^(ADD|SUB)S?[WX]rx(64)?$")>;
 499 def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>;
 500 def : InstRW<[M3WriteAV], (instrs ADDWri, ADDXri)>;
 501 def : InstRW<[M3WriteAW], (instrs ORRWri, ORRXri)>;
 502
 503 // Move instructions.
 504 def : InstRW<[M3WriteCOPY], (instrs COPY)>;
 505 def : InstRW<[M3WriteZ0],   (instrs ADR, ADRP)>;
 506 def : InstRW<[M3WriteZ0],   (instregex "^MOV[NZ][WX]i")>;
 507
 508 // Divide and multiply instructions.
 509
 510 // Miscellaneous instructions.
 511
 512 // Load instructions.
 513 def : InstRW<[M3WriteLD,
 514               WriteLDHi,
 515               WriteAdr],    (instregex "^LDP(SW|W|X)(post|pre)")>;
 516 def : InstRW<[M3WriteLB,
 517               ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
 518 def : InstRW<[M3WriteLX,
 519               ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
 520 def : InstRW<[M3WriteLB,
 521               ReadAdrBase], (instrs PRFMroW)>;
 522 def : InstRW<[M3WriteLX,
 523               ReadAdrBase], (instrs PRFMroX)>;
 524
 525 // Store instructions.
 526 def : InstRW<[M3WriteSB,
 527               ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>;
 528 def : InstRW<[WriteST,
 529               ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>;
 530
 531 // FP data instructions.
 532 def : InstRW<[M3WriteNSHF1],  (instregex "^FABS[DS]r")>;
 533 def : InstRW<[M3WriteFADD2],  (instregex "^F(ADD|SUB)[DS]rr")>;
 534 def : InstRW<[M3WriteFDIV10], (instrs FDIVSrr)>;
 535 def : InstRW<[M3WriteFDIV12], (instrs FDIVDrr)>;
 536 def : InstRW<[M3WriteNMSC1],  (instregex "^F(MAX|MIN).+rr")>;
 537 def : InstRW<[M3WriteFMAC3],  (instregex "^FN?MUL[DS]rr")>;
 538 def : InstRW<[M3WriteFMAC4,
 539               M3ReadFMAC],    (instregex "^FN?M(ADD|SUB)[DS]rrr")>;
 540 def : InstRW<[M3WriteNALU1],  (instregex "^FNEG[DS]r")>;
 541 def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT.+r")>;
 542 def : InstRW<[M3WriteNEONH],  (instregex "^FCSEL[DS]rrr")>;
 543 def : InstRW<[M3WriteFSQR17], (instrs FSQRTSr)>;
 544 def : InstRW<[M3WriteFSQR25], (instrs FSQRTDr)>;
 545
 546 // FP miscellaneous instructions.
 547 def : InstRW<[M3WriteFCVT3],  (instregex "^FCVT[DHS][DHS]r")>;
 548 def : InstRW<[M3WriteFCVT4A], (instregex "^[SU]CVTF[SU][XW][DHS]ri")>;
 549 def : InstRW<[M3WriteFCVT3A], (instregex "^FCVT[AMNPZ][SU]U[XW][DHS]r")>;
 550 def : InstRW<[M3WriteFCVT3A], (instregex "^FCVTZ[SU][dhs]")>;
 551 def : InstRW<[M3WriteNALU1],  (instregex "^FMOV[DS][ir]")>;
 552 def : InstRW<[M3WriteFCVT4],  (instregex "^[FU](RECP|RSQRT)Ev1")>;
 553 def : InstRW<[M3WriteNMSC1],  (instregex "^FRECPXv1")>;
 554 def : InstRW<[M3WriteFMAC4,
 555               M3ReadFMAC],    (instregex "^F(RECP|RSQRT)S(16|32|64)")>;
 556 def : InstRW<[M3WriteNALU1],  (instregex "^FMOV[WX][DS]r")>;
 557 def : InstRW<[M3WriteNALU1],  (instregex "^FMOV[DS][WX]r")>;
 558 def : InstRW<[M3WriteNEONI],  (instregex "^FMOV(DX|XD)Highr")>;
 559
 560 // FP load instructions.
 561 def : InstRW<[WriteVLD],    (instregex "^LDR[DSQ]l")>;
 562 def : InstRW<[WriteVLD],    (instregex "^LDUR[BDHSQ]i")>;
 563 def : InstRW<[WriteVLD,
 564               WriteAdr],    (instregex "^LDR[BDHSQ](post|pre)")>;
 565 def : InstRW<[WriteVLD],    (instregex "^LDR[BDHSQ]ui")>;
 566 def : InstRW<[M3WriteLE,
 567               ReadAdrBase], (instregex "^LDR[BDHS]roW")>;
 568 def : InstRW<[WriteVLD,
 569               ReadAdrBase], (instregex "^LDR[BDHS]roX")>;
 570 def : InstRW<[M3WriteLY,
 571               ReadAdrBase], (instregex "^LDRQro[WX]")>;
 572 def : InstRW<[WriteVLD,
 573               M3WriteLH],   (instregex "^LDN?P[DS]i")>;
 574 def : InstRW<[M3WriteLA,
 575               M3WriteLH],   (instregex "^LDN?PQi")>;
 576 def : InstRW<[M3WriteLB,
 577               M3WriteLH,
 578               WriteAdr],    (instregex "^LDP[DS](post|pre)")>;
 579 def : InstRW<[M3WriteLC,
 580               M3WriteLH,
 581               WriteAdr],    (instregex "^LDPQ(post|pre)")>;
 582
 583 // FP store instructions.
 584 def : InstRW<[WriteVST],    (instregex "^STUR[BDHSQ]i")>;
 585 def : InstRW<[WriteVST,
 586               WriteAdr],    (instregex "^STR[BDHSQ](post|pre)")>;
 587 def : InstRW<[WriteVST],    (instregex "^STR[BDHSQ]ui")>;
 588 def : InstRW<[M3WriteSA,
 589               ReadAdrBase], (instregex "^STR[BDHS]roW")>;
 590 def : InstRW<[M3WriteSA,
 591               ReadAdrBase], (instregex "^STRQroW")>;
 592 def : InstRW<[WriteVST,
 593               ReadAdrBase], (instregex "^STR[BDHS]roX")>;
 594 def : InstRW<[M3WriteSY,
 595               ReadAdrBase], (instregex "^STRQroX")>;
 596 def : InstRW<[WriteVST],    (instregex "^STN?P[DSQ]i")>;
 597 def : InstRW<[WriteVST,
 598               WriteAdr],    (instregex "^STP[DS](post|pre)")>;
 599 def : InstRW<[M3WriteSC,
 600               WriteAdr],    (instregex "^STPQ(post|pre)")>;
 601
 602 // ASIMD instructions.
 603 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]ABAL?v")>;
 604 def : InstRW<[M3WriteNMSC1], (instregex "^[SU]ABDL?v")>;
 605 def : InstRW<[M3WriteNMSC1], (instregex "^((SQ)?ABS|SQNEG)v")>;
 606 def : InstRW<[M3WriteNALU1], (instregex "^(ADD|NEG|SUB)v")>;
 607 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]?ADDL?Pv")>;
 608 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]H(ADD|SUB)v")>;
 609 def : InstRW<[M3WriteNMSC3], (instregex "^[SU](ADD|SUB)[LW]V?v")>;
 610 def : InstRW<[M3WriteNMSC3], (instregex "^R?(ADD|SUB)HN2?v")>;
 611 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]Q(ADD|SUB)v")>;
 612 def : InstRW<[M3WriteNMSC3], (instregex "^(SU|US)QADDv")>;
 613 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]RHADDv")>;
 614 def : InstRW<[M3WriteNMSC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>;
 615 def : InstRW<[M3WriteNALU1], (instregex "^CMTSTv")>;
 616 def : InstRW<[M3WriteNALU1], (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>;
 617 def : InstRW<[M3WriteNMSC1], (instregex "^[SU](MIN|MAX)v")>;
 618 def : InstRW<[M3WriteNMSC2], (instregex "^[SU](MIN|MAX)Pv")>;
 619 def : InstRW<[M3WriteNMSC3], (instregex "^[SU](MIN|MAX)Vv")>;
 620 def : InstRW<[M3WriteNMUL3], (instregex "^(MUL|SQR?DMULH)v")>;
 621 def : InstRW<[M3WriteNMUL3,
 622               M3ReadNMUL],   (instregex "^ML[AS]v")>;
 623 def : InstRW<[M3WriteNMUL3], (instregex "^[SU]ML[AS]Lv")>;
 624 def : InstRW<[M3WriteNMUL3], (instregex "^SQDML[AS]L")>;
 625 def : InstRW<[M3WriteNMUL3], (instregex "^(S|U|SQD)MULLv")>;
 626 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]ADALPv")>;
 627 def : InstRW<[M3WriteNSHT3], (instregex "^[SU]R?SRAv")>;
 628 def : InstRW<[M3WriteNSHT1], (instregex "^SHL[dv]")>;
 629 def : InstRW<[M3WriteNSHT1], (instregex "^[SU]SH[LR][dv]")>;
 630 def : InstRW<[M3WriteNSHT1], (instregex "^S[RS]I[dv]")>;
 631 def : InstRW<[M3WriteNSHT2], (instregex "^[SU]?SHLLv")>;
 632 def : InstRW<[M3WriteNSHT3], (instregex "^(([SU]Q)?R)?SHRU?N[bhsv]")>;
 633 def : InstRW<[M3WriteNSHT3], (instregex "^[SU]RSH[LR][dv]")>;
 634 def : InstRW<[M3WriteNSHT3], (instregex "^[SU]QR?SHLU?[bdhsv]")>;
 635
 636 // ASIMD FP instructions.
 637 def : InstRW<[M3WriteNSHF1],  (instregex "^FABSv")>;
 638 def : InstRW<[M3WriteFADD2],  (instregex "^F(ABD|ADD|SUB)v")>;
 639 def : InstRW<[M3WriteNEONA],  (instregex "^FADDP")>;
 640 def : InstRW<[M3WriteNMSC1],  (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>;
 641 def : InstRW<[M3WriteFCVT3],  (instregex "^FCVT(L|N|XN)v")>;
 642 def : InstRW<[M3WriteFCVT2],  (instregex "^FCVT[AMNPZ][SU]v")>;
 643 def : InstRW<[M3WriteFCVT2],  (instregex "^[SU]CVTFv")>;
 644 def : InstRW<[M3WriteFDIV10], (instrs FDIVv2f32)>;
 645 def : InstRW<[M3WriteNEONV],  (instrs FDIVv4f32)>;
 646 def : InstRW<[M3WriteNEONW],  (instrs FDIVv2f64)>;
 647 def : InstRW<[M3WriteNMSC1],  (instregex "^F(MAX|MIN)(NM)?v")>;
 648 def : InstRW<[M3WriteNMSC2],  (instregex "^F(MAX|MIN)(NM)?Pv")>;
 649 def : InstRW<[M3WriteNEONZ],  (instregex "^F(MAX|MIN)(NM)?Vv")>;
 650 def : InstRW<[M3WriteFMAC3],  (instregex "^FMULX?v.[fi]")>;
 651 def : InstRW<[M3WriteFMAC4,
 652               M3ReadFMAC],    (instregex "^FML[AS]v.f")>;
 653 def : InstRW<[M3WriteFMAC5,
 654               M3ReadFMAC],    (instregex "^FML[AS]v.i")>;
 655 def : InstRW<[M3WriteNALU1],  (instregex "^FNEGv")>;
 656 def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
 657 def : InstRW<[M3WriteFSQR17], (instrs FSQRTv2f32)>;
 658 def : InstRW<[M3WriteNEONX],  (instrs FSQRTv4f32)>;
 659 def : InstRW<[M3WriteNEONY],  (instrs FSQRTv2f64)>;
 660
 661 // ASIMD miscellaneous instructions.
 662 def : InstRW<[M3WriteNALU1], (instregex "^RBITv")>;
 663 def : InstRW<[M3WriteNALU1], (instregex "^(BIF|BIT|BSL)v")>;
 664 def : InstRW<[M3WriteNEONB], (instregex "^DUPv.+gpr")>;
 665 def : InstRW<[M3WriteNSHF1], (instregex "^DUPv.+lane")>;
 666 def : InstRW<[M3WriteNSHF1], (instregex "^EXTv")>;
 667 def : InstRW<[M3WriteNSHF1], (instregex "^[SU]?Q?XTU?Nv")>;
 668 def : InstRW<[M3WriteNSHF1], (instregex "^CPY")>;
 669 def : InstRW<[M3WriteNSHF1], (instregex "^INSv.+lane")>;
 670 def : InstRW<[M3WriteMOVI],  (instregex "^MOVI")>;
 671 def : InstRW<[M3WriteNALU1], (instregex "^FMOVv")>;
 672 def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev[248]")>;
 673 def : InstRW<[M3WriteFMAC4,
 674               M3ReadFMAC],   (instregex "^F(RECP|RSQRT)Sv")>;
 675 def : InstRW<[M3WriteNSHF1], (instregex "^REV(16|32|64)v")>;
 676 def : InstRW<[M3WriteNSHF1], (instregex "^TB[LX]v")>;
 677 def : InstRW<[M3WriteNEOND], (instregex "^[SU]MOVv")>;
 678 def : InstRW<[M3WriteNSHF3], (instregex "^INSv.+gpr")>;
 679 def : InstRW<[M3WriteNSHF1], (instregex "^(TRN|UZP|ZIP)[12]v")>;
 680
 681 // ASIMD load instructions.
 682 def : InstRW<[M3WriteL5],   (instregex "LD1Onev(8b|4h|2s|1d)$")>;
 683 def : InstRW<[M3WriteL5,
 684               M3WriteA1],   (instregex "LD1Onev(8b|4h|2s|1d)_POST")>;
 685 def : InstRW<[M3WriteL5],   (instregex "LD1Onev(16b|8h|4s|2d)$")>;
 686 def : InstRW<[M3WriteL5,
 687               M3WriteA1],   (instregex "LD1Onev(16b|8h|4s|2d)_POST")>;
 688
 689 def : InstRW<[M3WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>;
 690 def : InstRW<[M3WriteVLDA,
 691               M3WriteA1],   (instregex "LD1Twov(8b|4h|2s|1d)_POST")>;
 692 def : InstRW<[M3WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>;
 693 def : InstRW<[M3WriteVLDA,
 694               M3WriteA1],   (instregex "LD1Twov(16b|8h|4s|2d)_POST")>;
 695
 696 def : InstRW<[M3WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>;
 697 def : InstRW<[M3WriteVLDB,
 698               M3WriteA1],   (instregex "LD1Threev(8b|4h|2s|1d)_POST")>;
 699 def : InstRW<[M3WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>;
 700 def : InstRW<[M3WriteVLDB,
 701               M3WriteA1],   (instregex "LD1Threev(16b|8h|4s|2d)_POST")>;
 702
 703 def : InstRW<[M3WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>;
 704 def : InstRW<[M3WriteVLDC,
 705               M3WriteA1],   (instregex "LD1Fourv(8b|4h|2s|1d)_POST")>;
 706 def : InstRW<[M3WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>;
 707 def : InstRW<[M3WriteVLDC,
 708               M3WriteA1],   (instregex "LD1Fourv(16b|8h|4s|2d)_POST")>;
 709
 710 def : InstRW<[M3WriteVLDD], (instregex "LD1i(8|16|32)$")>;
 711 def : InstRW<[M3WriteVLDD,
 712               M3WriteA1],   (instregex "LD1i(8|16|32)_POST")>;
 713 def : InstRW<[M3WriteVLDE], (instregex "LD1i(64)$")>;
 714 def : InstRW<[M3WriteVLDE,
 715               M3WriteA1],   (instregex "LD1i(64)_POST")>;
 716
 717 def : InstRW<[M3WriteL5],   (instregex "LD1Rv(8b|4h|2s|1d)$")>;
 718 def : InstRW<[M3WriteL5,
 719               M3WriteA1],   (instregex "LD1Rv(8b|4h|2s|1d)_POST")>;
 720 def : InstRW<[M3WriteL5],   (instregex "LD1Rv(16b|8h|4s|2d)$")>;
 721 def : InstRW<[M3WriteL5,
 722               M3WriteA1],   (instregex "LD1Rv(16b|8h|4s|2d)_POST")>;
 723
 724 def : InstRW<[M3WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>;
 725 def : InstRW<[M3WriteVLDF,
 726               M3WriteA1],   (instregex "LD2Twov(8b|4h|2s)_POST")>;
 727 def : InstRW<[M3WriteVLDF], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
 728 def : InstRW<[M3WriteVLDF,
 729               M3WriteA1],   (instregex "LD2Twov(16b|8h|4s|2d)_POST")>;
 730
 731 def : InstRW<[M3WriteVLDG], (instregex "LD2i(8|16|32)$")>;
 732 def : InstRW<[M3WriteVLDG,
 733               M3WriteA1],   (instregex "LD2i(8|16|32)_POST")>;
 734 def : InstRW<[M3WriteVLDH], (instregex "LD2i(64)$")>;
 735 def : InstRW<[M3WriteVLDH,
 736               M3WriteA1],   (instregex "LD2i(64)_POST")>;
 737
 738 def : InstRW<[M3WriteVLDA], (instregex "LD2Rv(8b|4h|2s|1d)$")>;
 739 def : InstRW<[M3WriteVLDA,
 740               M3WriteA1],   (instregex "LD2Rv(8b|4h|2s|1d)_POST")>;
 741 def : InstRW<[M3WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>;
 742 def : InstRW<[M3WriteVLDA,
 743               M3WriteA1],   (instregex "LD2Rv(16b|8h|4s|2d)_POST")>;
 744
 745 def : InstRW<[M3WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>;
 746 def : InstRW<[M3WriteVLDI,
 747               M3WriteA1],   (instregex "LD3Threev(8b|4h|2s)_POST")>;
 748 def : InstRW<[M3WriteVLDI], (instregex "LD3Threev(16b|8h|4s|2d)$")>;
 749 def : InstRW<[M3WriteVLDI,
 750               M3WriteA1],   (instregex "LD3Threev(16b|8h|4s|2d)_POST")>;
 751
 752 def : InstRW<[M3WriteVLDJ], (instregex "LD3i(8|16|32)$")>;
 753 def : InstRW<[M3WriteVLDJ,
 754               M3WriteA1],   (instregex "LD3i(8|16|32)_POST")>;
 755 def : InstRW<[M3WriteVLDL], (instregex "LD3i(64)$")>;
 756 def : InstRW<[M3WriteVLDL,
 757               M3WriteA1],   (instregex "LD3i(64)_POST")>;
 758
 759 def : InstRW<[M3WriteVLDB], (instregex "LD3Rv(8b|4h|2s|1d)$")>;
 760 def : InstRW<[M3WriteVLDB,
 761               M3WriteA1],   (instregex "LD3Rv(8b|4h|2s|1d)_POST")>;
 762 def : InstRW<[M3WriteVLDB], (instregex "LD3Rv(16b|8h|4s|2d)$")>;
 763 def : InstRW<[M3WriteVLDB,
 764               M3WriteA1],   (instregex "LD3Rv(16b|8h|4s|2d)_POST")>;
 765
 766 def : InstRW<[M3WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>;
 767 def : InstRW<[M3WriteVLDN,
 768               M3WriteA1],   (instregex "LD4Fourv(8b|4h|2s)_POST")>;
 769 def : InstRW<[M3WriteVLDN], (instregex "LD4Fourv(16b|8h|4s|2d)$")>;
 770 def : InstRW<[M3WriteVLDN,
 771               M3WriteA1],   (instregex "LD4Fourv(16b|8h|4s|2d)_POST")>;
 772
 773 def : InstRW<[M3WriteVLDK], (instregex "LD4i(8|16|32)$")>;
 774 def : InstRW<[M3WriteVLDK,
 775               M3WriteA1],   (instregex "LD4i(8|16|32)_POST")>;
 776 def : InstRW<[M3WriteVLDM], (instregex "LD4i(64)$")>;
 777 def : InstRW<[M3WriteVLDM,
 778               M3WriteA1],   (instregex "LD4i(64)_POST")>;
 779
 780 def : InstRW<[M3WriteVLDC], (instregex "LD4Rv(8b|4h|2s|1d)$")>;
 781 def : InstRW<[M3WriteVLDC,
 782               M3WriteA1],   (instregex "LD4Rv(8b|4h|2s|1d)_POST")>;
 783 def : InstRW<[M3WriteVLDC], (instregex "LD4Rv(16b|8h|4s|2d)$")>;
 784 def : InstRW<[M3WriteVLDC,
 785               M3WriteA1],   (instregex "LD4Rv(16b|8h|4s|2d)_POST")>;
 786
 787 // ASIMD store instructions.
 788 def : InstRW<[WriteVST],    (instregex "ST1Onev(8b|4h|2s|1d)$")>;
 789 def : InstRW<[WriteVST,
 790               WriteAdr],    (instregex "ST1Onev(8b|4h|2s|1d)_POST")>;
 791 def : InstRW<[WriteVST],    (instregex "ST1Onev(16b|8h|4s|2d)$")>;
 792 def : InstRW<[WriteVST,
 793               WriteAdr],    (instregex "ST1Onev(16b|8h|4s|2d)_POST")>;
 794
 795 def : InstRW<[M3WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>;
 796 def : InstRW<[M3WriteVSTA,
 797               WriteAdr],    (instregex "ST1Twov(8b|4h|2s|1d)_POST")>;
 798 def : InstRW<[M3WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>;
 799 def : InstRW<[M3WriteVSTA,
 800               WriteAdr],    (instregex "ST1Twov(16b|8h|4s|2d)_POST")>;
 801
 802 def : InstRW<[M3WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>;
 803 def : InstRW<[M3WriteVSTB,
 804               WriteAdr],    (instregex "ST1Threev(8b|4h|2s|1d)_POST")>;
 805 def : InstRW<[M3WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>;
 806 def : InstRW<[M3WriteVSTB,
 807               WriteAdr],    (instregex "ST1Threev(16b|8h|4s|2d)_POST")>;
 808
 809 def : InstRW<[M3WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
 810 def : InstRW<[M3WriteVSTC,
 811               WriteAdr],    (instregex "ST1Fourv(8b|4h|2s|1d)_POST")>;
 812 def : InstRW<[M3WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
 813 def : InstRW<[M3WriteVSTC,
 814               WriteAdr],    (instregex "ST1Fourv(16b|8h|4s|2d)_POST")>;
 815
 816 def : InstRW<[M3WriteVSTD], (instregex "ST1i(8|16|32|64)$")>;
 817 def : InstRW<[M3WriteVSTD,
 818               WriteAdr],    (instregex "ST1i(8|16|32|64)_POST")>;
 819
 820 def : InstRW<[M3WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>;
 821 def : InstRW<[M3WriteVSTD,
 822               WriteAdr],    (instregex "ST2Twov(8b|4h|2s)_POST")>;
 823 def : InstRW<[M3WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
 824 def : InstRW<[M3WriteVSTE,
 825               WriteAdr],    (instregex "ST2Twov(16b|8h|4s|2d)_POST")>;
 826
 827 def : InstRW<[M3WriteVSTD], (instregex "ST2i(8|16|32)$")>;
 828 def : InstRW<[M3WriteVSTD,
 829               WriteAdr],    (instregex "ST2i(8|16|32)_POST")>;
 830 def : InstRW<[M3WriteVSTD], (instregex "ST2i(64)$")>;
 831 def : InstRW<[M3WriteVSTD,
 832               WriteAdr],    (instregex "ST2i(64)_POST")>;
 833
 834 def : InstRW<[M3WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>;
 835 def : InstRW<[M3WriteVSTF,
 836               WriteAdr],    (instregex "ST3Threev(8b|4h|2s)_POST")>;
 837 def : InstRW<[M3WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>;
 838 def : InstRW<[M3WriteVSTG,
 839               WriteAdr],    (instregex "ST3Threev(16b|8h|4s|2d)_POST")>;
 840
 841 def : InstRW<[M3WriteVSTH], (instregex "ST3i(8|16|32)$")>;
 842 def : InstRW<[M3WriteVSTH,
 843               WriteAdr],    (instregex "ST3i(8|16|32)_POST")>;
 844 def : InstRW<[M3WriteVSTF], (instregex "ST3i(64)$")>;
 845 def : InstRW<[M3WriteVSTF,
 846               WriteAdr],    (instregex "ST3i(64)_POST")>;
 847
 848 def : InstRW<[M3WriteVSTF], (instregex "ST4Fourv(8b|4h|2s)$")>;
 849 def : InstRW<[M3WriteVSTF,
 850               WriteAdr],    (instregex "ST4Fourv(8b|4h|2s)_POST")>;
 851 def : InstRW<[M3WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>;
 852 def : InstRW<[M3WriteVSTI,
 853               WriteAdr],    (instregex "ST4Fourv(16b|8h|4s|2d)_POST")>;
 854
 855 def : InstRW<[M3WriteVSTF], (instregex "ST4i(8|16|32|64)$")>;
 856 def : InstRW<[M3WriteVSTF,
 857               WriteAdr],    (instregex "ST4i(8|16|32|64)_POST")>;
 858
 859 // Cryptography instructions.
 860 def : InstRW<[M3WriteAES],    (instregex "^AES[DE]")>;
 861 def : InstRW<[M3WriteAES,
 862               M3ReadAES],     (instregex "^AESI?MC")>;
 863
 864 def : InstRW<[M3WriteNCRY3A], (instregex "^PMULL?v")>;
 865
 866 def : InstRW<[M3WriteNCRY1A], (instregex "^SHA1([CHMP]|SU[01])")>;
 867 def : InstRW<[M3WriteNCRY1A], (instregex "^SHA256SU0")>;
 868 def : InstRW<[M3WriteNCRY5A], (instregex "^SHA256(H2?|SU1)")>;
 869
 870 // CRC instructions.
 871 def : InstRW<[M3WriteC2], (instregex "^CRC32")>;
 872
 873 } // SchedModel = ExynosM3Model