llvm/lib/Target/RISCV/RISCVRegisterInfo.h

   1 //===-- RISCVRegisterInfo.h - RISCV Register Information Impl ---*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains the RISCV implementation of the TargetRegisterInfo class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
  14 #define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H
  15
  16 #include "llvm/CodeGen/TargetRegisterInfo.h"
  17
  18 #define GET_REGINFO_HEADER
  19 #include "RISCVGenRegisterInfo.inc"
  20
  21 namespace llvm {
  22
  23 struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
  24
  25   RISCVRegisterInfo(unsigned HwMode);
  26
  27   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
  28                                        CallingConv::ID) const override;
  29
  30   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
  31
  32   BitVector getReservedRegs(const MachineFunction &MF) const override;
  33   bool isAsmClobberable(const MachineFunction &MF,
  34                         unsigned PhysReg) const override;
  35
  36   bool isConstantPhysReg(unsigned PhysReg) const override;
  37
  38   const uint32_t *getNoPreservedMask() const override;
  39
  40   void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
  41                            unsigned FIOperandNum,
  42                            RegScavenger *RS = nullptr) const override;
  43
  44   Register getFrameRegister(const MachineFunction &MF) const override;
  45
  46   bool requiresRegisterScavenging(const MachineFunction &MF) const override {
  47     return true;
  48   }
  49
  50   bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
  51     return true;
  52   }
  53
  54   const TargetRegisterClass *
  55   getPointerRegClass(const MachineFunction &MF,
  56                      unsigned Kind = 0) const override {
  57     return &RISCV::GPRRegClass;
  58   }
  59 };
  60 }
  61
  62 #endif