llvm/lib/Target/RISCV/RISCVSubtarget.h

   1 //===-- RISCVSubtarget.h - Define Subtarget for the RISCV -------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file declares the RISCV specific subclass of TargetSubtargetInfo.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
  14 #define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
  15
  16 #include "RISCVFrameLowering.h"
  17 #include "RISCVISelLowering.h"
  18 #include "RISCVInstrInfo.h"
  19 #include "Utils/RISCVBaseInfo.h"
  20 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
  21 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
  22 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
  23 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
  24 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
  25 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  26 #include "llvm/IR/DataLayout.h"
  27 #include "llvm/Target/TargetMachine.h"
  28
  29 #define GET_SUBTARGETINFO_HEADER
  30 #include "RISCVGenSubtargetInfo.inc"
  31
  32 namespace llvm {
  33 class StringRef;
  34
  35 class RISCVSubtarget : public RISCVGenSubtargetInfo {
  36   virtual void anchor();
  37   bool HasStdExtM = false;
  38   bool HasStdExtA = false;
  39   bool HasStdExtF = false;
  40   bool HasStdExtD = false;
  41   bool HasStdExtC = false;
  42   bool HasRV64 = false;
  43   bool IsRV32E = false;
  44   bool EnableLinkerRelax = false;
  45   bool EnableRVCHintInstrs = false;
  46   unsigned XLen = 32;
  47   MVT XLenVT = MVT::i32;
  48   RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
  49   BitVector UserReservedRegister;
  50   RISCVFrameLowering FrameLowering;
  51   RISCVInstrInfo InstrInfo;
  52   RISCVRegisterInfo RegInfo;
  53   RISCVTargetLowering TLInfo;
  54   SelectionDAGTargetInfo TSInfo;
  55
  56   /// Initializes using the passed in CPU and feature strings so that we can
  57   /// use initializer lists for subtarget initialization.
  58   RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
  59                                                   StringRef CPU, StringRef FS,
  60                                                   StringRef ABIName);
  61
  62 public:
  63   // Initializes the data members to match that of the specified triple.
  64   RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
  65                  StringRef ABIName, const TargetMachine &TM);
  66
  67   // Parses features string setting specified subtarget options. The
  68   // definition of this function is auto-generated by tblgen.
  69   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
  70
  71   const RISCVFrameLowering *getFrameLowering() const override {
  72     return &FrameLowering;
  73   }
  74   const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; }
  75   const RISCVRegisterInfo *getRegisterInfo() const override {
  76     return &RegInfo;
  77   }
  78   const RISCVTargetLowering *getTargetLowering() const override {
  79     return &TLInfo;
  80   }
  81   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
  82     return &TSInfo;
  83   }
  84   bool enableMachineScheduler() const override { return true; }
  85   bool hasStdExtM() const { return HasStdExtM; }
  86   bool hasStdExtA() const { return HasStdExtA; }
  87   bool hasStdExtF() const { return HasStdExtF; }
  88   bool hasStdExtD() const { return HasStdExtD; }
  89   bool hasStdExtC() const { return HasStdExtC; }
  90   bool is64Bit() const { return HasRV64; }
  91   bool isRV32E() const { return IsRV32E; }
  92   bool enableLinkerRelax() const { return EnableLinkerRelax; }
  93   bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
  94   MVT getXLenVT() const { return XLenVT; }
  95   unsigned getXLen() const { return XLen; }
  96   RISCVABI::ABI getTargetABI() const { return TargetABI; }
  97   bool isRegisterReservedByUser(Register i) const {
  98     assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
  99     return UserReservedRegister[i];
 100   }
 101
 102 protected:
 103   // GlobalISel related APIs.
 104   std::unique_ptr<CallLowering> CallLoweringInfo;
 105   std::unique_ptr<InstructionSelector> InstSelector;
 106   std::unique_ptr<LegalizerInfo> Legalizer;
 107   std::unique_ptr<RegisterBankInfo> RegBankInfo;
 108
 109 public:
 110   const CallLowering *getCallLowering() const override;
 111   InstructionSelector *getInstructionSelector() const override;
 112   const LegalizerInfo *getLegalizerInfo() const override;
 113   const RegisterBankInfo *getRegBankInfo() const override;
 114 };
 115 } // End llvm namespace
 116
 117 #endif