lld/COFF/Chunks.cpp

   1 //===- Chunks.cpp ---------------------------------------------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 #include "Chunks.h"
  10 #include "COFFLinkerContext.h"
  11 #include "InputFiles.h"
  12 #include "SymbolTable.h"
  13 #include "Symbols.h"
  14 #include "Writer.h"
  15 #include "llvm/ADT/STLExtras.h"
  16 #include "llvm/ADT/StringExtras.h"
  17 #include "llvm/ADT/Twine.h"
  18 #include "llvm/BinaryFormat/COFF.h"
  19 #include "llvm/Object/COFF.h"
  20 #include "llvm/Support/Debug.h"
  21 #include "llvm/Support/Endian.h"
  22 #include "llvm/Support/raw_ostream.h"
  23 #include <algorithm>
  24 #include <iterator>
  25
  26 using namespace llvm;
  27 using namespace llvm::object;
  28 using namespace llvm::support::endian;
  29 using namespace llvm::COFF;
  30 using llvm::support::ulittle32_t;
  31
  32 namespace lld::coff {
  33
  34 SectionChunk::SectionChunk(ObjFile *f, const coff_section *h, Kind k)
  35     : Chunk(k), file(f), header(h), repl(this) {
  36   // Initialize relocs.
  37   if (file)
  38     setRelocs(file->getCOFFObj()->getRelocations(header));
  39
  40   // Initialize sectionName.
  41   StringRef sectionName;
  42   if (file) {
  43     if (Expected<StringRef> e = file->getCOFFObj()->getSectionName(header))
  44       sectionName = *e;
  45   }
  46   sectionNameData = sectionName.data();
  47   sectionNameSize = sectionName.size();
  48
  49   setAlignment(header->getAlignment());
  50
  51   hasData = !(header->Characteristics & IMAGE_SCN_CNT_UNINITIALIZED_DATA);
  52
  53   // If linker GC is disabled, every chunk starts out alive.  If linker GC is
  54   // enabled, treat non-comdat sections as roots. Generally optimized object
  55   // files will be built with -ffunction-sections or /Gy, so most things worth
  56   // stripping will be in a comdat.
  57   if (file)
  58     live = !file->ctx.config.doGC || !isCOMDAT();
  59   else
  60     live = true;
  61 }
  62
  63 // SectionChunk is one of the most frequently allocated classes, so it is
  64 // important to keep it as compact as possible. As of this writing, the number
  65 // below is the size of this class on x64 platforms.
  66 static_assert(sizeof(SectionChunk) <= 88, "SectionChunk grew unexpectedly");
  67
  68 static void add16(uint8_t *p, int16_t v) { write16le(p, read16le(p) + v); }
  69 static void add32(uint8_t *p, int32_t v) { write32le(p, read32le(p) + v); }
  70 static void add64(uint8_t *p, int64_t v) { write64le(p, read64le(p) + v); }
  71 static void or16(uint8_t *p, uint16_t v) { write16le(p, read16le(p) | v); }
  72 static void or32(uint8_t *p, uint32_t v) { write32le(p, read32le(p) | v); }
  73
  74 // Verify that given sections are appropriate targets for SECREL
  75 // relocations. This check is relaxed because unfortunately debug
  76 // sections have section-relative relocations against absolute symbols.
  77 static bool checkSecRel(const SectionChunk *sec, OutputSection *os) {
  78   if (os)
  79     return true;
  80   if (sec->isCodeView())
  81     return false;
  82   error("SECREL relocation cannot be applied to absolute symbols");
  83   return false;
  84 }
  85
  86 static void applySecRel(const SectionChunk *sec, uint8_t *off,
  87                         OutputSection *os, uint64_t s) {
  88   if (!checkSecRel(sec, os))
  89     return;
  90   uint64_t secRel = s - os->getRVA();
  91   if (secRel > UINT32_MAX) {
  92     error("overflow in SECREL relocation in section: " + sec->getSectionName());
  93     return;
  94   }
  95   add32(off, secRel);
  96 }
  97
  98 static void applySecIdx(uint8_t *off, OutputSection *os,
  99                         unsigned numOutputSections) {
 100   // numOutputSections is the largest valid section index. Make sure that
 101   // it fits in 16 bits.
 102   assert(numOutputSections <= 0xffff && "size of outputSections is too big");
 103
 104   // Absolute symbol doesn't have section index, but section index relocation
 105   // against absolute symbol should be resolved to one plus the last output
 106   // section index. This is required for compatibility with MSVC.
 107   if (os)
 108     add16(off, os->sectionIndex);
 109   else
 110     add16(off, numOutputSections + 1);
 111 }
 112
 113 void SectionChunk::applyRelX64(uint8_t *off, uint16_t type, OutputSection *os,
 114                                uint64_t s, uint64_t p,
 115                                uint64_t imageBase) const {
 116   switch (type) {
 117   case IMAGE_REL_AMD64_ADDR32:
 118     add32(off, s + imageBase);
 119     break;
 120   case IMAGE_REL_AMD64_ADDR64:
 121     add64(off, s + imageBase);
 122     break;
 123   case IMAGE_REL_AMD64_ADDR32NB: add32(off, s); break;
 124   case IMAGE_REL_AMD64_REL32:    add32(off, s - p - 4); break;
 125   case IMAGE_REL_AMD64_REL32_1:  add32(off, s - p - 5); break;
 126   case IMAGE_REL_AMD64_REL32_2:  add32(off, s - p - 6); break;
 127   case IMAGE_REL_AMD64_REL32_3:  add32(off, s - p - 7); break;
 128   case IMAGE_REL_AMD64_REL32_4:  add32(off, s - p - 8); break;
 129   case IMAGE_REL_AMD64_REL32_5:  add32(off, s - p - 9); break;
 130   case IMAGE_REL_AMD64_SECTION:
 131     applySecIdx(off, os, file->ctx.outputSections.size());
 132     break;
 133   case IMAGE_REL_AMD64_SECREL:   applySecRel(this, off, os, s); break;
 134   default:
 135     error("unsupported relocation type 0x" + Twine::utohexstr(type) + " in " +
 136           toString(file));
 137   }
 138 }
 139
 140 void SectionChunk::applyRelX86(uint8_t *off, uint16_t type, OutputSection *os,
 141                                uint64_t s, uint64_t p,
 142                                uint64_t imageBase) const {
 143   switch (type) {
 144   case IMAGE_REL_I386_ABSOLUTE: break;
 145   case IMAGE_REL_I386_DIR32:
 146     add32(off, s + imageBase);
 147     break;
 148   case IMAGE_REL_I386_DIR32NB:  add32(off, s); break;
 149   case IMAGE_REL_I386_REL32:    add32(off, s - p - 4); break;
 150   case IMAGE_REL_I386_SECTION:
 151     applySecIdx(off, os, file->ctx.outputSections.size());
 152     break;
 153   case IMAGE_REL_I386_SECREL:   applySecRel(this, off, os, s); break;
 154   default:
 155     error("unsupported relocation type 0x" + Twine::utohexstr(type) + " in " +
 156           toString(file));
 157   }
 158 }
 159
 160 static void applyMOV(uint8_t *off, uint16_t v) {
 161   write16le(off, (read16le(off) & 0xfbf0) | ((v & 0x800) >> 1) | ((v >> 12) & 0xf));
 162   write16le(off + 2, (read16le(off + 2) & 0x8f00) | ((v & 0x700) << 4) | (v & 0xff));
 163 }
 164
 165 static uint16_t readMOV(uint8_t *off, bool movt) {
 166   uint16_t op1 = read16le(off);
 167   if ((op1 & 0xfbf0) != (movt ? 0xf2c0 : 0xf240))
 168     error("unexpected instruction in " + Twine(movt ? "MOVT" : "MOVW") +
 169           " instruction in MOV32T relocation");
 170   uint16_t op2 = read16le(off + 2);
 171   if ((op2 & 0x8000) != 0)
 172     error("unexpected instruction in " + Twine(movt ? "MOVT" : "MOVW") +
 173           " instruction in MOV32T relocation");
 174   return (op2 & 0x00ff) | ((op2 >> 4) & 0x0700) | ((op1 << 1) & 0x0800) |
 175          ((op1 & 0x000f) << 12);
 176 }
 177
 178 void applyMOV32T(uint8_t *off, uint32_t v) {
 179   uint16_t immW = readMOV(off, false);    // read MOVW operand
 180   uint16_t immT = readMOV(off + 4, true); // read MOVT operand
 181   uint32_t imm = immW | (immT << 16);
 182   v += imm;                         // add the immediate offset
 183   applyMOV(off, v);           // set MOVW operand
 184   applyMOV(off + 4, v >> 16); // set MOVT operand
 185 }
 186
 187 static void applyBranch20T(uint8_t *off, int32_t v) {
 188   if (!isInt<21>(v))
 189     error("relocation out of range");
 190   uint32_t s = v < 0 ? 1 : 0;
 191   uint32_t j1 = (v >> 19) & 1;
 192   uint32_t j2 = (v >> 18) & 1;
 193   or16(off, (s << 10) | ((v >> 12) & 0x3f));
 194   or16(off + 2, (j1 << 13) | (j2 << 11) | ((v >> 1) & 0x7ff));
 195 }
 196
 197 void applyBranch24T(uint8_t *off, int32_t v) {
 198   if (!isInt<25>(v))
 199     error("relocation out of range");
 200   uint32_t s = v < 0 ? 1 : 0;
 201   uint32_t j1 = ((~v >> 23) & 1) ^ s;
 202   uint32_t j2 = ((~v >> 22) & 1) ^ s;
 203   or16(off, (s << 10) | ((v >> 12) & 0x3ff));
 204   // Clear out the J1 and J2 bits which may be set.
 205   write16le(off + 2, (read16le(off + 2) & 0xd000) | (j1 << 13) | (j2 << 11) | ((v >> 1) & 0x7ff));
 206 }
 207
 208 void SectionChunk::applyRelARM(uint8_t *off, uint16_t type, OutputSection *os,
 209                                uint64_t s, uint64_t p,
 210                                uint64_t imageBase) const {
 211   // Pointer to thumb code must have the LSB set.
 212   uint64_t sx = s;
 213   if (os && (os->header.Characteristics & IMAGE_SCN_MEM_EXECUTE))
 214     sx |= 1;
 215   switch (type) {
 216   case IMAGE_REL_ARM_ADDR32:
 217     add32(off, sx + imageBase);
 218     break;
 219   case IMAGE_REL_ARM_ADDR32NB:  add32(off, sx); break;
 220   case IMAGE_REL_ARM_MOV32T:
 221     applyMOV32T(off, sx + imageBase);
 222     break;
 223   case IMAGE_REL_ARM_BRANCH20T: applyBranch20T(off, sx - p - 4); break;
 224   case IMAGE_REL_ARM_BRANCH24T: applyBranch24T(off, sx - p - 4); break;
 225   case IMAGE_REL_ARM_BLX23T:    applyBranch24T(off, sx - p - 4); break;
 226   case IMAGE_REL_ARM_SECTION:
 227     applySecIdx(off, os, file->ctx.outputSections.size());
 228     break;
 229   case IMAGE_REL_ARM_SECREL:    applySecRel(this, off, os, s); break;
 230   case IMAGE_REL_ARM_REL32:     add32(off, sx - p - 4); break;
 231   default:
 232     error("unsupported relocation type 0x" + Twine::utohexstr(type) + " in " +
 233           toString(file));
 234   }
 235 }
 236
 237 // Interpret the existing immediate value as a byte offset to the
 238 // target symbol, then update the instruction with the immediate as
 239 // the page offset from the current instruction to the target.
 240 void applyArm64Addr(uint8_t *off, uint64_t s, uint64_t p, int shift) {
 241   uint32_t orig = read32le(off);
 242   int64_t imm =
 243       SignExtend64<21>(((orig >> 29) & 0x3) | ((orig >> 3) & 0x1FFFFC));
 244   s += imm;
 245   imm = (s >> shift) - (p >> shift);
 246   uint32_t immLo = (imm & 0x3) << 29;
 247   uint32_t immHi = (imm & 0x1FFFFC) << 3;
 248   uint64_t mask = (0x3 << 29) | (0x1FFFFC << 3);
 249   write32le(off, (orig & ~mask) | immLo | immHi);
 250 }
 251
 252 // Update the immediate field in a AARCH64 ldr, str, and add instruction.
 253 // Optionally limit the range of the written immediate by one or more bits
 254 // (rangeLimit).
 255 void applyArm64Imm(uint8_t *off, uint64_t imm, uint32_t rangeLimit) {
 256   uint32_t orig = read32le(off);
 257   imm += (orig >> 10) & 0xFFF;
 258   orig &= ~(0xFFF << 10);
 259   write32le(off, orig | ((imm & (0xFFF >> rangeLimit)) << 10));
 260 }
 261
 262 // Add the 12 bit page offset to the existing immediate.
 263 // Ldr/str instructions store the opcode immediate scaled
 264 // by the load/store size (giving a larger range for larger
 265 // loads/stores). The immediate is always (both before and after
 266 // fixing up the relocation) stored scaled similarly.
 267 // Even if larger loads/stores have a larger range, limit the
 268 // effective offset to 12 bit, since it is intended to be a
 269 // page offset.
 270 static void applyArm64Ldr(uint8_t *off, uint64_t imm) {
 271   uint32_t orig = read32le(off);
 272   uint32_t size = orig >> 30;
 273   // 0x04000000 indicates SIMD/FP registers
 274   // 0x00800000 indicates 128 bit
 275   if ((orig & 0x4800000) == 0x4800000)
 276     size += 4;
 277   if ((imm & ((1 << size) - 1)) != 0)
 278     error("misaligned ldr/str offset");
 279   applyArm64Imm(off, imm >> size, size);
 280 }
 281
 282 static void applySecRelLow12A(const SectionChunk *sec, uint8_t *off,
 283                               OutputSection *os, uint64_t s) {
 284   if (checkSecRel(sec, os))
 285     applyArm64Imm(off, (s - os->getRVA()) & 0xfff, 0);
 286 }
 287
 288 static void applySecRelHigh12A(const SectionChunk *sec, uint8_t *off,
 289                                OutputSection *os, uint64_t s) {
 290   if (!checkSecRel(sec, os))
 291     return;
 292   uint64_t secRel = (s - os->getRVA()) >> 12;
 293   if (0xfff < secRel) {
 294     error("overflow in SECREL_HIGH12A relocation in section: " +
 295           sec->getSectionName());
 296     return;
 297   }
 298   applyArm64Imm(off, secRel & 0xfff, 0);
 299 }
 300
 301 static void applySecRelLdr(const SectionChunk *sec, uint8_t *off,
 302                            OutputSection *os, uint64_t s) {
 303   if (checkSecRel(sec, os))
 304     applyArm64Ldr(off, (s - os->getRVA()) & 0xfff);
 305 }
 306
 307 void applyArm64Branch26(uint8_t *off, int64_t v) {
 308   if (!isInt<28>(v))
 309     error("relocation out of range");
 310   or32(off, (v & 0x0FFFFFFC) >> 2);
 311 }
 312
 313 static void applyArm64Branch19(uint8_t *off, int64_t v) {
 314   if (!isInt<21>(v))
 315     error("relocation out of range");
 316   or32(off, (v & 0x001FFFFC) << 3);
 317 }
 318
 319 static void applyArm64Branch14(uint8_t *off, int64_t v) {
 320   if (!isInt<16>(v))
 321     error("relocation out of range");
 322   or32(off, (v & 0x0000FFFC) << 3);
 323 }
 324
 325 void SectionChunk::applyRelARM64(uint8_t *off, uint16_t type, OutputSection *os,
 326                                  uint64_t s, uint64_t p,
 327                                  uint64_t imageBase) const {
 328   switch (type) {
 329   case IMAGE_REL_ARM64_PAGEBASE_REL21: applyArm64Addr(off, s, p, 12); break;
 330   case IMAGE_REL_ARM64_REL21:          applyArm64Addr(off, s, p, 0); break;
 331   case IMAGE_REL_ARM64_PAGEOFFSET_12A: applyArm64Imm(off, s & 0xfff, 0); break;
 332   case IMAGE_REL_ARM64_PAGEOFFSET_12L: applyArm64Ldr(off, s & 0xfff); break;
 333   case IMAGE_REL_ARM64_BRANCH26:       applyArm64Branch26(off, s - p); break;
 334   case IMAGE_REL_ARM64_BRANCH19:       applyArm64Branch19(off, s - p); break;
 335   case IMAGE_REL_ARM64_BRANCH14:       applyArm64Branch14(off, s - p); break;
 336   case IMAGE_REL_ARM64_ADDR32:
 337     add32(off, s + imageBase);
 338     break;
 339   case IMAGE_REL_ARM64_ADDR32NB:       add32(off, s); break;
 340   case IMAGE_REL_ARM64_ADDR64:
 341     add64(off, s + imageBase);
 342     break;
 343   case IMAGE_REL_ARM64_SECREL:         applySecRel(this, off, os, s); break;
 344   case IMAGE_REL_ARM64_SECREL_LOW12A:  applySecRelLow12A(this, off, os, s); break;
 345   case IMAGE_REL_ARM64_SECREL_HIGH12A: applySecRelHigh12A(this, off, os, s); break;
 346   case IMAGE_REL_ARM64_SECREL_LOW12L:  applySecRelLdr(this, off, os, s); break;
 347   case IMAGE_REL_ARM64_SECTION:
 348     applySecIdx(off, os, file->ctx.outputSections.size());
 349     break;
 350   case IMAGE_REL_ARM64_REL32:          add32(off, s - p - 4); break;
 351   default:
 352     error("unsupported relocation type 0x" + Twine::utohexstr(type) + " in " +
 353           toString(file));
 354   }
 355 }
 356
 357 static void maybeReportRelocationToDiscarded(const SectionChunk *fromChunk,
 358                                              Defined *sym,
 359                                              const coff_relocation &rel,
 360                                              bool isMinGW) {
 361   // Don't report these errors when the relocation comes from a debug info
 362   // section or in mingw mode. MinGW mode object files (built by GCC) can
 363   // have leftover sections with relocations against discarded comdat
 364   // sections. Such sections are left as is, with relocations untouched.
 365   if (fromChunk->isCodeView() || fromChunk->isDWARF() || isMinGW)
 366     return;
 367
 368   // Get the name of the symbol. If it's null, it was discarded early, so we
 369   // have to go back to the object file.
 370   ObjFile *file = fromChunk->file;
 371   StringRef name;
 372   if (sym) {
 373     name = sym->getName();
 374   } else {
 375     COFFSymbolRef coffSym =
 376         check(file->getCOFFObj()->getSymbol(rel.SymbolTableIndex));
 377     name = check(file->getCOFFObj()->getSymbolName(coffSym));
 378   }
 379
 380   std::vector<std::string> symbolLocations =
 381       getSymbolLocations(file, rel.SymbolTableIndex);
 382
 383   std::string out;
 384   llvm::raw_string_ostream os(out);
 385   os << "relocation against symbol in discarded section: " + name;
 386   for (const std::string &s : symbolLocations)
 387     os << s;
 388   error(out);
 389 }
 390
 391 void SectionChunk::writeTo(uint8_t *buf) const {
 392   if (!hasData)
 393     return;
 394   // Copy section contents from source object file to output file.
 395   ArrayRef<uint8_t> a = getContents();
 396   if (!a.empty())
 397     memcpy(buf, a.data(), a.size());
 398
 399   // Apply relocations.
 400   size_t inputSize = getSize();
 401   for (const coff_relocation &rel : getRelocs()) {
 402     // Check for an invalid relocation offset. This check isn't perfect, because
 403     // we don't have the relocation size, which is only known after checking the
 404     // machine and relocation type. As a result, a relocation may overwrite the
 405     // beginning of the following input section.
 406     if (rel.VirtualAddress >= inputSize) {
 407       error("relocation points beyond the end of its parent section");
 408       continue;
 409     }
 410
 411     applyRelocation(buf + rel.VirtualAddress, rel);
 412   }
 413
 414   // Write the offset to EC entry thunk preceding section contents. The low bit
 415   // is always set, so it's effectively an offset from the last byte of the
 416   // offset.
 417   if (Defined *entryThunk = getEntryThunk())
 418     write32le(buf - sizeof(uint32_t), entryThunk->getRVA() - rva + 1);
 419 }
 420
 421 void SectionChunk::applyRelocation(uint8_t *off,
 422                                    const coff_relocation &rel) const {
 423   auto *sym = dyn_cast_or_null<Defined>(file->getSymbol(rel.SymbolTableIndex));
 424
 425   // Get the output section of the symbol for this relocation.  The output
 426   // section is needed to compute SECREL and SECTION relocations used in debug
 427   // info.
 428   Chunk *c = sym ? sym->getChunk() : nullptr;
 429   OutputSection *os = c ? file->ctx.getOutputSection(c) : nullptr;
 430
 431   // Skip the relocation if it refers to a discarded section, and diagnose it
 432   // as an error if appropriate. If a symbol was discarded early, it may be
 433   // null. If it was discarded late, the output section will be null, unless
 434   // it was an absolute or synthetic symbol.
 435   if (!sym ||
 436       (!os && !isa<DefinedAbsolute>(sym) && !isa<DefinedSynthetic>(sym))) {
 437     maybeReportRelocationToDiscarded(this, sym, rel, file->ctx.config.mingw);
 438     return;
 439   }
 440
 441   uint64_t s = sym->getRVA();
 442
 443   // Compute the RVA of the relocation for relative relocations.
 444   uint64_t p = rva + rel.VirtualAddress;
 445   uint64_t imageBase = file->ctx.config.imageBase;
 446   switch (getArch()) {
 447   case Triple::x86_64:
 448     applyRelX64(off, rel.Type, os, s, p, imageBase);
 449     break;
 450   case Triple::x86:
 451     applyRelX86(off, rel.Type, os, s, p, imageBase);
 452     break;
 453   case Triple::thumb:
 454     applyRelARM(off, rel.Type, os, s, p, imageBase);
 455     break;
 456   case Triple::aarch64:
 457     applyRelARM64(off, rel.Type, os, s, p, imageBase);
 458     break;
 459   default:
 460     llvm_unreachable("unknown machine type");
 461   }
 462 }
 463
 464 // Defend against unsorted relocations. This may be overly conservative.
 465 void SectionChunk::sortRelocations() {
 466   auto cmpByVa = [](const coff_relocation &l, const coff_relocation &r) {
 467     return l.VirtualAddress < r.VirtualAddress;
 468   };
 469   if (llvm::is_sorted(getRelocs(), cmpByVa))
 470     return;
 471   warn("some relocations in " + file->getName() + " are not sorted");
 472   MutableArrayRef<coff_relocation> newRelocs(
 473       bAlloc().Allocate<coff_relocation>(relocsSize), relocsSize);
 474   memcpy(newRelocs.data(), relocsData, relocsSize * sizeof(coff_relocation));
 475   llvm::sort(newRelocs, cmpByVa);
 476   setRelocs(newRelocs);
 477 }
 478
 479 // Similar to writeTo, but suitable for relocating a subsection of the overall
 480 // section.
 481 void SectionChunk::writeAndRelocateSubsection(ArrayRef<uint8_t> sec,
 482                                               ArrayRef<uint8_t> subsec,
 483                                               uint32_t &nextRelocIndex,
 484                                               uint8_t *buf) const {
 485   assert(!subsec.empty() && !sec.empty());
 486   assert(sec.begin() <= subsec.begin() && subsec.end() <= sec.end() &&
 487          "subsection is not part of this section");
 488   size_t vaBegin = std::distance(sec.begin(), subsec.begin());
 489   size_t vaEnd = std::distance(sec.begin(), subsec.end());
 490   memcpy(buf, subsec.data(), subsec.size());
 491   for (; nextRelocIndex < relocsSize; ++nextRelocIndex) {
 492     const coff_relocation &rel = relocsData[nextRelocIndex];
 493     // Only apply relocations that apply to this subsection. These checks
 494     // assume that all subsections completely contain their relocations.
 495     // Relocations must not straddle the beginning or end of a subsection.
 496     if (rel.VirtualAddress < vaBegin)
 497       continue;
 498     if (rel.VirtualAddress + 1 >= vaEnd)
 499       break;
 500     applyRelocation(&buf[rel.VirtualAddress - vaBegin], rel);
 501   }
 502 }
 503
 504 void SectionChunk::addAssociative(SectionChunk *child) {
 505   // Insert the child section into the list of associated children. Keep the
 506   // list ordered by section name so that ICF does not depend on section order.
 507   assert(child->assocChildren == nullptr &&
 508          "associated sections cannot have their own associated children");
 509   SectionChunk *prev = this;
 510   SectionChunk *next = assocChildren;
 511   for (; next != nullptr; prev = next, next = next->assocChildren) {
 512     if (next->getSectionName() <= child->getSectionName())
 513       break;
 514   }
 515
 516   // Insert child between prev and next.
 517   assert(prev->assocChildren == next);
 518   prev->assocChildren = child;
 519   child->assocChildren = next;
 520 }
 521
 522 static uint8_t getBaserelType(const coff_relocation &rel,
 523                               Triple::ArchType arch) {
 524   switch (arch) {
 525   case Triple::x86_64:
 526     if (rel.Type == IMAGE_REL_AMD64_ADDR64)
 527       return IMAGE_REL_BASED_DIR64;
 528     if (rel.Type == IMAGE_REL_AMD64_ADDR32)
 529       return IMAGE_REL_BASED_HIGHLOW;
 530     return IMAGE_REL_BASED_ABSOLUTE;
 531   case Triple::x86:
 532     if (rel.Type == IMAGE_REL_I386_DIR32)
 533       return IMAGE_REL_BASED_HIGHLOW;
 534     return IMAGE_REL_BASED_ABSOLUTE;
 535   case Triple::thumb:
 536     if (rel.Type == IMAGE_REL_ARM_ADDR32)
 537       return IMAGE_REL_BASED_HIGHLOW;
 538     if (rel.Type == IMAGE_REL_ARM_MOV32T)
 539       return IMAGE_REL_BASED_ARM_MOV32T;
 540     return IMAGE_REL_BASED_ABSOLUTE;
 541   case Triple::aarch64:
 542     if (rel.Type == IMAGE_REL_ARM64_ADDR64)
 543       return IMAGE_REL_BASED_DIR64;
 544     return IMAGE_REL_BASED_ABSOLUTE;
 545   default:
 546     llvm_unreachable("unknown machine type");
 547   }
 548 }
 549
 550 // Windows-specific.
 551 // Collect all locations that contain absolute addresses, which need to be
 552 // fixed by the loader if load-time relocation is needed.
 553 // Only called when base relocation is enabled.
 554 void SectionChunk::getBaserels(std::vector<Baserel> *res) {
 555   for (const coff_relocation &rel : getRelocs()) {
 556     uint8_t ty = getBaserelType(rel, getArch());
 557     if (ty == IMAGE_REL_BASED_ABSOLUTE)
 558       continue;
 559     Symbol *target = file->getSymbol(rel.SymbolTableIndex);
 560     if (!target || isa<DefinedAbsolute>(target))
 561       continue;
 562     res->emplace_back(rva + rel.VirtualAddress, ty);
 563   }
 564 }
 565
 566 // MinGW specific.
 567 // Check whether a static relocation of type Type can be deferred and
 568 // handled at runtime as a pseudo relocation (for references to a module
 569 // local variable, which turned out to actually need to be imported from
 570 // another DLL) This returns the size the relocation is supposed to update,
 571 // in bits, or 0 if the relocation cannot be handled as a runtime pseudo
 572 // relocation.
 573 static int getRuntimePseudoRelocSize(uint16_t type, Triple::ArchType arch) {
 574   // Relocations that either contain an absolute address, or a plain
 575   // relative offset, since the runtime pseudo reloc implementation
 576   // adds 8/16/32/64 bit values to a memory address.
 577   //
 578   // Given a pseudo relocation entry,
 579   //
 580   // typedef struct {
 581   //   DWORD sym;
 582   //   DWORD target;
 583   //   DWORD flags;
 584   // } runtime_pseudo_reloc_item_v2;
 585   //
 586   // the runtime relocation performs this adjustment:
 587   //     *(base + .target) += *(base + .sym) - (base + .sym)
 588   //
 589   // This works for both absolute addresses (IMAGE_REL_*_ADDR32/64,
 590   // IMAGE_REL_I386_DIR32, where the memory location initially contains
 591   // the address of the IAT slot, and for relative addresses (IMAGE_REL*_REL32),
 592   // where the memory location originally contains the relative offset to the
 593   // IAT slot.
 594   //
 595   // This requires the target address to be writable, either directly out of
 596   // the image, or temporarily changed at runtime with VirtualProtect.
 597   // Since this only operates on direct address values, it doesn't work for
 598   // ARM/ARM64 relocations, other than the plain ADDR32/ADDR64 relocations.
 599   switch (arch) {
 600   case Triple::x86_64:
 601     switch (type) {
 602     case IMAGE_REL_AMD64_ADDR64:
 603       return 64;
 604     case IMAGE_REL_AMD64_ADDR32:
 605     case IMAGE_REL_AMD64_REL32:
 606     case IMAGE_REL_AMD64_REL32_1:
 607     case IMAGE_REL_AMD64_REL32_2:
 608     case IMAGE_REL_AMD64_REL32_3:
 609     case IMAGE_REL_AMD64_REL32_4:
 610     case IMAGE_REL_AMD64_REL32_5:
 611       return 32;
 612     default:
 613       return 0;
 614     }
 615   case Triple::x86:
 616     switch (type) {
 617     case IMAGE_REL_I386_DIR32:
 618     case IMAGE_REL_I386_REL32:
 619       return 32;
 620     default:
 621       return 0;
 622     }
 623   case Triple::thumb:
 624     switch (type) {
 625     case IMAGE_REL_ARM_ADDR32:
 626       return 32;
 627     default:
 628       return 0;
 629     }
 630   case Triple::aarch64:
 631     switch (type) {
 632     case IMAGE_REL_ARM64_ADDR64:
 633       return 64;
 634     case IMAGE_REL_ARM64_ADDR32:
 635       return 32;
 636     default:
 637       return 0;
 638     }
 639   default:
 640     llvm_unreachable("unknown machine type");
 641   }
 642 }
 643
 644 // MinGW specific.
 645 // Append information to the provided vector about all relocations that
 646 // need to be handled at runtime as runtime pseudo relocations (references
 647 // to a module local variable, which turned out to actually need to be
 648 // imported from another DLL).
 649 void SectionChunk::getRuntimePseudoRelocs(
 650     std::vector<RuntimePseudoReloc> &res) {
 651   for (const coff_relocation &rel : getRelocs()) {
 652     auto *target =
 653         dyn_cast_or_null<Defined>(file->getSymbol(rel.SymbolTableIndex));
 654     if (!target || !target->isRuntimePseudoReloc)
 655       continue;
 656     // If the target doesn't have a chunk allocated, it may be a
 657     // DefinedImportData symbol which ended up unnecessary after GC.
 658     // Normally we wouldn't eliminate section chunks that are referenced, but
 659     // references within DWARF sections don't count for keeping section chunks
 660     // alive. Thus such dangling references in DWARF sections are expected.
 661     if (!target->getChunk())
 662       continue;
 663     int sizeInBits = getRuntimePseudoRelocSize(rel.Type, getArch());
 664     if (sizeInBits == 0) {
 665       error("unable to automatically import from " + target->getName() +
 666             " with relocation type " +
 667             file->getCOFFObj()->getRelocationTypeName(rel.Type) + " in " +
 668             toString(file));
 669       continue;
 670     }
 671     int addressSizeInBits = file->ctx.config.is64() ? 64 : 32;
 672     if (sizeInBits < addressSizeInBits) {
 673       warn("runtime pseudo relocation in " + toString(file) + " against " +
 674            "symbol " + target->getName() + " is too narrow (only " +
 675            Twine(sizeInBits) + " bits wide); this can fail at runtime " +
 676            "depending on memory layout");
 677     }
 678     // sizeInBits is used to initialize the Flags field; currently no
 679     // other flags are defined.
 680     res.emplace_back(target, this, rel.VirtualAddress, sizeInBits);
 681   }
 682 }
 683
 684 bool SectionChunk::isCOMDAT() const {
 685   return header->Characteristics & IMAGE_SCN_LNK_COMDAT;
 686 }
 687
 688 void SectionChunk::printDiscardedMessage() const {
 689   // Removed by dead-stripping. If it's removed by ICF, ICF already
 690   // printed out the name, so don't repeat that here.
 691   if (sym && this == repl)
 692     log("Discarded " + sym->getName());
 693 }
 694
 695 StringRef SectionChunk::getDebugName() const {
 696   if (sym)
 697     return sym->getName();
 698   return "";
 699 }
 700
 701 ArrayRef<uint8_t> SectionChunk::getContents() const {
 702   ArrayRef<uint8_t> a;
 703   cantFail(file->getCOFFObj()->getSectionContents(header, a));
 704   return a;
 705 }
 706
 707 ArrayRef<uint8_t> SectionChunk::consumeDebugMagic() {
 708   assert(isCodeView());
 709   return consumeDebugMagic(getContents(), getSectionName());
 710 }
 711
 712 ArrayRef<uint8_t> SectionChunk::consumeDebugMagic(ArrayRef<uint8_t> data,
 713                                                   StringRef sectionName) {
 714   if (data.empty())
 715     return {};
 716
 717   // First 4 bytes are section magic.
 718   if (data.size() < 4)
 719     fatal("the section is too short: " + sectionName);
 720
 721   if (!sectionName.starts_with(".debug$"))
 722     fatal("invalid section: " + sectionName);
 723
 724   uint32_t magic = support::endian::read32le(data.data());
 725   uint32_t expectedMagic = sectionName == ".debug$H"
 726                                ? DEBUG_HASHES_SECTION_MAGIC
 727                                : DEBUG_SECTION_MAGIC;
 728   if (magic != expectedMagic) {
 729     warn("ignoring section " + sectionName + " with unrecognized magic 0x" +
 730          utohexstr(magic));
 731     return {};
 732   }
 733   return data.slice(4);
 734 }
 735
 736 SectionChunk *SectionChunk::findByName(ArrayRef<SectionChunk *> sections,
 737                                        StringRef name) {
 738   for (SectionChunk *c : sections)
 739     if (c->getSectionName() == name)
 740       return c;
 741   return nullptr;
 742 }
 743
 744 void SectionChunk::replace(SectionChunk *other) {
 745   p2Align = std::max(p2Align, other->p2Align);
 746   other->repl = repl;
 747   other->live = false;
 748 }
 749
 750 uint32_t SectionChunk::getSectionNumber() const {
 751   DataRefImpl r;
 752   r.p = reinterpret_cast<uintptr_t>(header);
 753   SectionRef s(r, file->getCOFFObj());
 754   return s.getIndex() + 1;
 755 }
 756
 757 CommonChunk::CommonChunk(const COFFSymbolRef s) : sym(s) {
 758   // The value of a common symbol is its size. Align all common symbols smaller
 759   // than 32 bytes naturally, i.e. round the size up to the next power of two.
 760   // This is what MSVC link.exe does.
 761   setAlignment(std::min(32U, uint32_t(PowerOf2Ceil(sym.getValue()))));
 762   hasData = false;
 763 }
 764
 765 uint32_t CommonChunk::getOutputCharacteristics() const {
 766   return IMAGE_SCN_CNT_UNINITIALIZED_DATA | IMAGE_SCN_MEM_READ |
 767          IMAGE_SCN_MEM_WRITE;
 768 }
 769
 770 void StringChunk::writeTo(uint8_t *buf) const {
 771   memcpy(buf, str.data(), str.size());
 772   buf[str.size()] = '\0';
 773 }
 774
 775 ImportThunkChunk::ImportThunkChunk(COFFLinkerContext &ctx, Defined *s)
 776     : NonSectionCodeChunk(ImportThunkKind), live(!ctx.config.doGC),
 777       impSymbol(s), ctx(ctx) {}
 778
 779 ImportThunkChunkX64::ImportThunkChunkX64(COFFLinkerContext &ctx, Defined *s)
 780     : ImportThunkChunk(ctx, s) {
 781   // Intel Optimization Manual says that all branch targets
 782   // should be 16-byte aligned. MSVC linker does this too.
 783   setAlignment(16);
 784 }
 785
 786 void ImportThunkChunkX64::writeTo(uint8_t *buf) const {
 787   memcpy(buf, importThunkX86, sizeof(importThunkX86));
 788   // The first two bytes is a JMP instruction. Fill its operand.
 789   write32le(buf + 2, impSymbol->getRVA() - rva - getSize());
 790 }
 791
 792 void ImportThunkChunkX86::getBaserels(std::vector<Baserel> *res) {
 793   res->emplace_back(getRVA() + 2, ctx.config.machine);
 794 }
 795
 796 void ImportThunkChunkX86::writeTo(uint8_t *buf) const {
 797   memcpy(buf, importThunkX86, sizeof(importThunkX86));
 798   // The first two bytes is a JMP instruction. Fill its operand.
 799   write32le(buf + 2, impSymbol->getRVA() + ctx.config.imageBase);
 800 }
 801
 802 void ImportThunkChunkARM::getBaserels(std::vector<Baserel> *res) {
 803   res->emplace_back(getRVA(), IMAGE_REL_BASED_ARM_MOV32T);
 804 }
 805
 806 void ImportThunkChunkARM::writeTo(uint8_t *buf) const {
 807   memcpy(buf, importThunkARM, sizeof(importThunkARM));
 808   // Fix mov.w and mov.t operands.
 809   applyMOV32T(buf, impSymbol->getRVA() + ctx.config.imageBase);
 810 }
 811
 812 void ImportThunkChunkARM64::writeTo(uint8_t *buf) const {
 813   int64_t off = impSymbol->getRVA() & 0xfff;
 814   memcpy(buf, importThunkARM64, sizeof(importThunkARM64));
 815   applyArm64Addr(buf, impSymbol->getRVA(), rva, 12);
 816   applyArm64Ldr(buf + 4, off);
 817 }
 818
 819 // A Thumb2, PIC, non-interworking range extension thunk.
 820 const uint8_t armThunk[] = {
 821     0x40, 0xf2, 0x00, 0x0c, // P:  movw ip,:lower16:S - (P + (L1-P) + 4)
 822     0xc0, 0xf2, 0x00, 0x0c, //     movt ip,:upper16:S - (P + (L1-P) + 4)
 823     0xe7, 0x44,             // L1: add  pc, ip
 824 };
 825
 826 size_t RangeExtensionThunkARM::getSize() const {
 827   assert(ctx.config.machine == ARMNT);
 828   (void)&ctx;
 829   return sizeof(armThunk);
 830 }
 831
 832 void RangeExtensionThunkARM::writeTo(uint8_t *buf) const {
 833   assert(ctx.config.machine == ARMNT);
 834   uint64_t offset = target->getRVA() - rva - 12;
 835   memcpy(buf, armThunk, sizeof(armThunk));
 836   applyMOV32T(buf, uint32_t(offset));
 837 }
 838
 839 // A position independent ARM64 adrp+add thunk, with a maximum range of
 840 // +/- 4 GB, which is enough for any PE-COFF.
 841 const uint8_t arm64Thunk[] = {
 842     0x10, 0x00, 0x00, 0x90, // adrp x16, Dest
 843     0x10, 0x02, 0x00, 0x91, // add  x16, x16, :lo12:Dest
 844     0x00, 0x02, 0x1f, 0xd6, // br   x16
 845 };
 846
 847 size_t RangeExtensionThunkARM64::getSize() const { return sizeof(arm64Thunk); }
 848
 849 void RangeExtensionThunkARM64::writeTo(uint8_t *buf) const {
 850   memcpy(buf, arm64Thunk, sizeof(arm64Thunk));
 851   applyArm64Addr(buf + 0, target->getRVA(), rva, 12);
 852   applyArm64Imm(buf + 4, target->getRVA() & 0xfff, 0);
 853 }
 854
 855 LocalImportChunk::LocalImportChunk(COFFLinkerContext &c, Defined *s)
 856     : sym(s), ctx(c) {
 857   setAlignment(ctx.config.wordsize);
 858 }
 859
 860 void LocalImportChunk::getBaserels(std::vector<Baserel> *res) {
 861   res->emplace_back(getRVA(), ctx.config.machine);
 862 }
 863
 864 size_t LocalImportChunk::getSize() const { return ctx.config.wordsize; }
 865
 866 void LocalImportChunk::writeTo(uint8_t *buf) const {
 867   if (ctx.config.is64()) {
 868     write64le(buf, sym->getRVA() + ctx.config.imageBase);
 869   } else {
 870     write32le(buf, sym->getRVA() + ctx.config.imageBase);
 871   }
 872 }
 873
 874 void RVATableChunk::writeTo(uint8_t *buf) const {
 875   ulittle32_t *begin = reinterpret_cast<ulittle32_t *>(buf);
 876   size_t cnt = 0;
 877   for (const ChunkAndOffset &co : syms)
 878     begin[cnt++] = co.inputChunk->getRVA() + co.offset;
 879   llvm::sort(begin, begin + cnt);
 880   assert(std::unique(begin, begin + cnt) == begin + cnt &&
 881          "RVA tables should be de-duplicated");
 882 }
 883
 884 void RVAFlagTableChunk::writeTo(uint8_t *buf) const {
 885   struct RVAFlag {
 886     ulittle32_t rva;
 887     uint8_t flag;
 888   };
 889   auto flags =
 890       MutableArrayRef(reinterpret_cast<RVAFlag *>(buf), syms.size());
 891   for (auto t : zip(syms, flags)) {
 892     const auto &sym = std::get<0>(t);
 893     auto &flag = std::get<1>(t);
 894     flag.rva = sym.inputChunk->getRVA() + sym.offset;
 895     flag.flag = 0;
 896   }
 897   llvm::sort(flags,
 898              [](const RVAFlag &a, const RVAFlag &b) { return a.rva < b.rva; });
 899   assert(llvm::unique(flags, [](const RVAFlag &a,
 900                                 const RVAFlag &b) { return a.rva == b.rva; }) ==
 901              flags.end() &&
 902          "RVA tables should be de-duplicated");
 903 }
 904
 905 size_t ECCodeMapChunk::getSize() const {
 906   return map.size() * sizeof(chpe_range_entry);
 907 }
 908
 909 void ECCodeMapChunk::writeTo(uint8_t *buf) const {
 910   auto table = reinterpret_cast<chpe_range_entry *>(buf);
 911   for (uint32_t i = 0; i < map.size(); i++) {
 912     const ECCodeMapEntry &entry = map[i];
 913     uint32_t start = entry.first->getRVA();
 914     table[i].StartOffset = start | entry.type;
 915     table[i].Length = entry.last->getRVA() + entry.last->getSize() - start;
 916   }
 917 }
 918
 919 // MinGW specific, for the "automatic import of variables from DLLs" feature.
 920 size_t PseudoRelocTableChunk::getSize() const {
 921   if (relocs.empty())
 922     return 0;
 923   return 12 + 12 * relocs.size();
 924 }
 925
 926 // MinGW specific.
 927 void PseudoRelocTableChunk::writeTo(uint8_t *buf) const {
 928   if (relocs.empty())
 929     return;
 930
 931   ulittle32_t *table = reinterpret_cast<ulittle32_t *>(buf);
 932   // This is the list header, to signal the runtime pseudo relocation v2
 933   // format.
 934   table[0] = 0;
 935   table[1] = 0;
 936   table[2] = 1;
 937
 938   size_t idx = 3;
 939   for (const RuntimePseudoReloc &rpr : relocs) {
 940     table[idx + 0] = rpr.sym->getRVA();
 941     table[idx + 1] = rpr.target->getRVA() + rpr.targetOffset;
 942     table[idx + 2] = rpr.flags;
 943     idx += 3;
 944   }
 945 }
 946
 947 // Windows-specific. This class represents a block in .reloc section.
 948 // The format is described here.
 949 //
 950 // On Windows, each DLL is linked against a fixed base address and
 951 // usually loaded to that address. However, if there's already another
 952 // DLL that overlaps, the loader has to relocate it. To do that, DLLs
 953 // contain .reloc sections which contain offsets that need to be fixed
 954 // up at runtime. If the loader finds that a DLL cannot be loaded to its
 955 // desired base address, it loads it to somewhere else, and add <actual
 956 // base address> - <desired base address> to each offset that is
 957 // specified by the .reloc section. In ELF terms, .reloc sections
 958 // contain relative relocations in REL format (as opposed to RELA.)
 959 //
 960 // This already significantly reduces the size of relocations compared
 961 // to ELF .rel.dyn, but Windows does more to reduce it (probably because
 962 // it was invented for PCs in the late '80s or early '90s.)  Offsets in
 963 // .reloc are grouped by page where the page size is 12 bits, and
 964 // offsets sharing the same page address are stored consecutively to
 965 // represent them with less space. This is very similar to the page
 966 // table which is grouped by (multiple stages of) pages.
 967 //
 968 // For example, let's say we have 0x00030, 0x00500, 0x00700, 0x00A00,
 969 // 0x20004, and 0x20008 in a .reloc section for x64. The uppermost 4
 970 // bits have a type IMAGE_REL_BASED_DIR64 or 0xA. In the section, they
 971 // are represented like this:
 972 //
 973 //   0x00000  -- page address (4 bytes)
 974 //   16       -- size of this block (4 bytes)
 975 //     0xA030 -- entries (2 bytes each)
 976 //     0xA500
 977 //     0xA700
 978 //     0xAA00
 979 //   0x20000  -- page address (4 bytes)
 980 //   12       -- size of this block (4 bytes)
 981 //     0xA004 -- entries (2 bytes each)
 982 //     0xA008
 983 //
 984 // Usually we have a lot of relocations for each page, so the number of
 985 // bytes for one .reloc entry is close to 2 bytes on average.
 986 BaserelChunk::BaserelChunk(uint32_t page, Baserel *begin, Baserel *end) {
 987   // Block header consists of 4 byte page RVA and 4 byte block size.
 988   // Each entry is 2 byte. Last entry may be padding.
 989   data.resize(alignTo((end - begin) * 2 + 8, 4));
 990   uint8_t *p = data.data();
 991   write32le(p, page);
 992   write32le(p + 4, data.size());
 993   p += 8;
 994   for (Baserel *i = begin; i != end; ++i) {
 995     write16le(p, (i->type << 12) | (i->rva - page));
 996     p += 2;
 997   }
 998 }
 999
1000 void BaserelChunk::writeTo(uint8_t *buf) const {
1001   memcpy(buf, data.data(), data.size());
1002 }
1003
1004 uint8_t Baserel::getDefaultType(llvm::COFF::MachineTypes machine) {
1005   return is64Bit(machine) ? IMAGE_REL_BASED_DIR64 : IMAGE_REL_BASED_HIGHLOW;
1006 }
1007
1008 MergeChunk::MergeChunk(uint32_t alignment)
1009     : builder(StringTableBuilder::RAW, llvm::Align(alignment)) {
1010   setAlignment(alignment);
1011 }
1012
1013 void MergeChunk::addSection(COFFLinkerContext &ctx, SectionChunk *c) {
1014   assert(isPowerOf2_32(c->getAlignment()));
1015   uint8_t p2Align = llvm::Log2_32(c->getAlignment());
1016   assert(p2Align < std::size(ctx.mergeChunkInstances));
1017   auto *&mc = ctx.mergeChunkInstances[p2Align];
1018   if (!mc)
1019     mc = make<MergeChunk>(c->getAlignment());
1020   mc->sections.push_back(c);
1021 }
1022
1023 void MergeChunk::finalizeContents() {
1024   assert(!finalized && "should only finalize once");
1025   for (SectionChunk *c : sections)
1026     if (c->live)
1027       builder.add(toStringRef(c->getContents()));
1028   builder.finalize();
1029   finalized = true;
1030 }
1031
1032 void MergeChunk::assignSubsectionRVAs() {
1033   for (SectionChunk *c : sections) {
1034     if (!c->live)
1035       continue;
1036     size_t off = builder.getOffset(toStringRef(c->getContents()));
1037     c->setRVA(rva + off);
1038   }
1039 }
1040
1041 uint32_t MergeChunk::getOutputCharacteristics() const {
1042   return IMAGE_SCN_MEM_READ | IMAGE_SCN_CNT_INITIALIZED_DATA;
1043 }
1044
1045 size_t MergeChunk::getSize() const {
1046   return builder.getSize();
1047 }
1048
1049 void MergeChunk::writeTo(uint8_t *buf) const {
1050   builder.write(buf);
1051 }
1052
1053 // MinGW specific.
1054 size_t AbsolutePointerChunk::getSize() const { return ctx.config.wordsize; }
1055
1056 void AbsolutePointerChunk::writeTo(uint8_t *buf) const {
1057   if (ctx.config.is64()) {
1058     write64le(buf, value);
1059   } else {
1060     write32le(buf, value);
1061   }
1062 }
1063
1064 void ECExportThunkChunk::writeTo(uint8_t *buf) const {
1065   memcpy(buf, ECExportThunkCode, sizeof(ECExportThunkCode));
1066   write32le(buf + 10, target->getRVA() - rva - 14);
1067 }
1068
1069 size_t CHPECodeRangesChunk::getSize() const {
1070   return exportThunks.size() * sizeof(chpe_code_range_entry);
1071 }
1072
1073 void CHPECodeRangesChunk::writeTo(uint8_t *buf) const {
1074   auto ranges = reinterpret_cast<chpe_code_range_entry *>(buf);
1075
1076   for (uint32_t i = 0; i < exportThunks.size(); i++) {
1077     Chunk *thunk = exportThunks[i].first;
1078     uint32_t start = thunk->getRVA();
1079     ranges[i].StartRva = start;
1080     ranges[i].EndRva = start + thunk->getSize();
1081     ranges[i].EntryPoint = start;
1082   }
1083 }
1084
1085 size_t CHPERedirectionChunk::getSize() const {
1086   // Add an extra +1 for a terminator entry.
1087   return (exportThunks.size() + 1) * sizeof(chpe_redirection_entry);
1088 }
1089
1090 void CHPERedirectionChunk::writeTo(uint8_t *buf) const {
1091   auto entries = reinterpret_cast<chpe_redirection_entry *>(buf);
1092
1093   for (uint32_t i = 0; i < exportThunks.size(); i++) {
1094     entries[i].Source = exportThunks[i].first->getRVA();
1095     entries[i].Destination = exportThunks[i].second->getRVA();
1096   }
1097 }
1098
1099 ImportThunkChunkARM64EC::ImportThunkChunkARM64EC(ImportFile *file)
1100     : ImportThunkChunk(file->ctx, file->impSym), file(file) {}
1101
1102 size_t ImportThunkChunkARM64EC::getSize() const {
1103   if (!extended)
1104     return sizeof(importThunkARM64EC);
1105   // The last instruction is replaced with an inline range extension thunk.
1106   return sizeof(importThunkARM64EC) + sizeof(arm64Thunk) - sizeof(uint32_t);
1107 }
1108
1109 void ImportThunkChunkARM64EC::writeTo(uint8_t *buf) const {
1110   memcpy(buf, importThunkARM64EC, sizeof(importThunkARM64EC));
1111   applyArm64Addr(buf, file->impSym->getRVA(), rva, 12);
1112   applyArm64Ldr(buf + 4, file->impSym->getRVA() & 0xfff);
1113
1114   // The exit thunk may be missing. This can happen if the application only
1115   // references a function by its address (in which case the thunk is never
1116   // actually used, but is still required to fill the auxiliary IAT), or in
1117   // cases of hand-written assembly calling an imported ARM64EC function (where
1118   // the exit thunk is ignored by __icall_helper_arm64ec). In such cases, MSVC
1119   // link.exe uses 0 as the RVA.
1120   uint32_t exitThunkRVA = exitThunk ? exitThunk->getRVA() : 0;
1121   applyArm64Addr(buf + 8, exitThunkRVA, rva + 8, 12);
1122   applyArm64Imm(buf + 12, exitThunkRVA & 0xfff, 0);
1123
1124   Defined *helper = cast<Defined>(file->ctx.config.arm64ECIcallHelper);
1125   if (extended) {
1126     // Replace last instruction with an inline range extension thunk.
1127     memcpy(buf + 16, arm64Thunk, sizeof(arm64Thunk));
1128     applyArm64Addr(buf + 16, helper->getRVA(), rva + 16, 12);
1129     applyArm64Imm(buf + 20, helper->getRVA() & 0xfff, 0);
1130   } else {
1131     applyArm64Branch26(buf + 16, helper->getRVA() - rva - 16);
1132   }
1133 }
1134
1135 bool ImportThunkChunkARM64EC::verifyRanges() {
1136   if (extended)
1137     return true;
1138   auto helper = cast<Defined>(file->ctx.config.arm64ECIcallHelper);
1139   return isInt<28>(helper->getRVA() - rva - 16);
1140 }
1141
1142 uint32_t ImportThunkChunkARM64EC::extendRanges() {
1143   if (extended || verifyRanges())
1144     return 0;
1145   extended = true;
1146   // The last instruction is replaced with an inline range extension thunk.
1147   return sizeof(arm64Thunk) - sizeof(uint32_t);
1148 }
1149
1150 } // namespace lld::coff