clang/lib/Headers/raointintrin.h

   1 /*===----------------------- raointintrin.h - RAOINT ------------------------===
   2  *
   3  * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4  * See https://llvm.org/LICENSE.txt for license information.
   5  * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6  *
   7  *===-----------------------------------------------------------------------===
   8  */
   9
  10 #ifndef __X86GPRINTRIN_H
  11 #error "Never use <raointintrin.h> directly; include <x86gprintrin.h> instead."
  12 #endif // __X86GPRINTRIN_H
  13
  14 #ifndef __RAOINTINTRIN_H
  15 #define __RAOINTINTRIN_H
  16
  17 #define __DEFAULT_FN_ATTRS                                                     \
  18   __attribute__((__always_inline__, __nodebug__, __target__("raoint")))
  19
  20 /// Atomically add a 32-bit value at memory operand \a __A and a 32-bit \a __B,
  21 ///    and store the result to the same memory location.
  22 ///
  23 ///    This intrinsic should be used for contention or weak ordering. It may
  24 ///    result in bad performance for hot data used by single thread only.
  25 ///
  26 /// \headerfile <x86intrin.h>
  27 ///
  28 /// This intrinsic corresponds to the \c AADD instruction.
  29 ///
  30 /// \param __A
  31 ///    A pointer to a 32-bit memory location.
  32 /// \param __B
  33 ///    A 32-bit integer value.
  34 ///
  35 /// \code{.operation}
  36 /// MEM[__A+31:__A] := MEM[__A+31:__A] + __B[31:0]
  37 /// \endcode
  38 static __inline__ void __DEFAULT_FN_ATTRS _aadd_i32(int *__A, int __B) {
  39   __builtin_ia32_aadd32((int *)__A, __B);
  40 }
  41
  42 /// Atomically and a 32-bit value at memory operand \a __A and a 32-bit \a __B,
  43 ///    and store the result to the same memory location.
  44 ///
  45 ///    This intrinsic should be used for contention or weak ordering. It may
  46 ///    result in bad performance for hot data used by single thread only.
  47 ///
  48 /// \headerfile <x86intrin.h>
  49 ///
  50 /// This intrinsic corresponds to the \c AAND instruction.
  51 ///
  52 /// \param __A
  53 ///    A pointer to a 32-bit memory location.
  54 /// \param __B
  55 ///    A 32-bit integer value.
  56 ///
  57 /// \code{.operation}
  58 /// MEM[__A+31:__A] := MEM[__A+31:__A] AND __B[31:0]
  59 /// \endcode
  60 static __inline__ void __DEFAULT_FN_ATTRS _aand_i32(int *__A, int __B) {
  61   __builtin_ia32_aand32((int *)__A, __B);
  62 }
  63
  64 /// Atomically or a 32-bit value at memory operand \a __A and a 32-bit \a __B,
  65 ///    and store the result to the same memory location.
  66 ///
  67 ///    This intrinsic should be used for contention or weak ordering. It may
  68 ///    result in bad performance for hot data used by single thread only.
  69 ///
  70 /// \headerfile <x86intrin.h>
  71 ///
  72 /// This intrinsic corresponds to the \c AOR instruction.
  73 ///
  74 /// \param __A
  75 ///    A pointer to a 32-bit memory location.
  76 /// \param __B
  77 ///    A 32-bit integer value.
  78 ///
  79 /// \code{.operation}
  80 /// MEM[__A+31:__A] := MEM[__A+31:__A] OR __B[31:0]
  81 /// \endcode
  82 static __inline__ void __DEFAULT_FN_ATTRS _aor_i32(int *__A, int __B) {
  83   __builtin_ia32_aor32((int *)__A, __B);
  84 }
  85
  86 /// Atomically xor a 32-bit value at memory operand \a __A and a 32-bit \a __B,
  87 ///    and store the result to the same memory location.
  88 ///
  89 ///    This intrinsic should be used for contention or weak ordering. It may
  90 ///    result in bad performance for hot data used by single thread only.
  91 ///
  92 /// \headerfile <x86intrin.h>
  93 ///
  94 /// This intrinsic corresponds to the \c AXOR instruction.
  95 ///
  96 /// \param __A
  97 ///    A pointer to a 32-bit memory location.
  98 /// \param __B
  99 ///    A 32-bit integer value.
 100 ///
 101 /// \code{.operation}
 102 /// MEM[__A+31:__A] := MEM[__A+31:__A] XOR __B[31:0]
 103 /// \endcode
 104 static __inline__ void __DEFAULT_FN_ATTRS _axor_i32(int *__A, int __B) {
 105   __builtin_ia32_axor32((int *)__A, __B);
 106 }
 107
 108 #ifdef __x86_64__
 109 /// Atomically add a 64-bit value at memory operand \a __A and a 64-bit \a __B,
 110 ///    and store the result to the same memory location.
 111 ///
 112 ///    This intrinsic should be used for contention or weak ordering. It may
 113 ///    result in bad performance for hot data used by single thread only.
 114 ///
 115 /// \headerfile <x86intrin.h>
 116 ///
 117 /// This intrinsic corresponds to the \c AADD instruction.
 118 ///
 119 /// \param __A
 120 ///    A pointer to a 64-bit memory location.
 121 /// \param __B
 122 ///    A 64-bit integer value.
 123 ///
 124 /// \code{.operation}
 125 /// MEM[__A+63:__A] := MEM[__A+63:__A] + __B[63:0]
 126 /// \endcode
 127 static __inline__ void __DEFAULT_FN_ATTRS _aadd_i64(long long *__A,
 128                                                     long long __B) {
 129   __builtin_ia32_aadd64((long long *)__A, __B);
 130 }
 131
 132 /// Atomically and a 64-bit value at memory operand \a __A and a 64-bit \a __B,
 133 ///    and store the result to the same memory location.
 134 ///
 135 ///    This intrinsic should be used for contention or weak ordering. It may
 136 ///    result in bad performance for hot data used by single thread only.
 137 ///
 138 /// \headerfile <x86intrin.h>
 139 ///
 140 /// This intrinsic corresponds to the \c AAND instruction.
 141 ///
 142 /// \param __A
 143 ///    A pointer to a 64-bit memory location.
 144 /// \param __B
 145 ///    A 64-bit integer value.
 146 ///
 147 /// \code{.operation}
 148 /// MEM[__A+63:__A] := MEM[__A+63:__A] AND __B[63:0]
 149 /// \endcode
 150 static __inline__ void __DEFAULT_FN_ATTRS _aand_i64(long long *__A,
 151                                                     long long __B) {
 152   __builtin_ia32_aand64((long long *)__A, __B);
 153 }
 154
 155 /// Atomically or a 64-bit value at memory operand \a __A and a 64-bit \a __B,
 156 ///    and store the result to the same memory location.
 157 ///
 158 ///    This intrinsic should be used for contention or weak ordering. It may
 159 ///    result in bad performance for hot data used by single thread only.
 160 ///
 161 /// \headerfile <x86intrin.h>
 162 ///
 163 /// This intrinsic corresponds to the \c AOR instruction.
 164 ///
 165 /// \param __A
 166 ///    A pointer to a 64-bit memory location.
 167 /// \param __B
 168 ///    A 64-bit integer value.
 169 ///
 170 /// \code{.operation}
 171 /// MEM[__A+63:__A] := MEM[__A+63:__A] OR __B[63:0]
 172 /// \endcode
 173 static __inline__ void __DEFAULT_FN_ATTRS _aor_i64(long long *__A,
 174                                                    long long __B) {
 175   __builtin_ia32_aor64((long long *)__A, __B);
 176 }
 177
 178 /// Atomically xor a 64-bit value at memory operand \a __A and a 64-bit \a __B,
 179 ///    and store the result to the same memory location.
 180 ///
 181 ///    This intrinsic should be used for contention or weak ordering. It may
 182 ///    result in bad performance for hot data used by single thread only.
 183 ///
 184 /// \headerfile <x86intrin.h>
 185 ///
 186 /// This intrinsic corresponds to the \c AXOR instruction.
 187 ///
 188 /// \param __A
 189 ///    A pointer to a 64-bit memory location.
 190 /// \param __B
 191 ///    A 64-bit integer value.
 192 ///
 193 /// \code{.operation}
 194 /// MEM[__A+63:__A] := MEM[__A+63:__A] XOR __B[63:0]
 195 /// \endcode
 196 static __inline__ void __DEFAULT_FN_ATTRS _axor_i64(long long *__A,
 197                                                     long long __B) {
 198   __builtin_ia32_axor64((long long *)__A, __B);
 199 }
 200 #endif // __x86_64__
 201
 202 #undef __DEFAULT_FN_ATTRS
 203 #endif // __RAOINTINTRIN_H