[flang][cuda] Update CompilerGeneratedNames pass to work on gpu module (#120660)
[llvm-project.git] / clang / test / CodeGen / AArch64 / mixed-target-attributes.c
blob1ccb0c6177c8c5d4732f934f11b5bff462a1233f
1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals --include-generated-funcs --global-value-regex ".*"
2 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -v9.5a -emit-llvm -o - %s | FileCheck %s
3 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -fmv -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK-NOFMV
5 // The following is guarded because in NOFMV we get an error for redefining the default.
6 #ifdef __HAVE_FUNCTION_MULTI_VERSIONING
7 int explicit_default(void) { return 0; }
8 __attribute__((target_version("jscvt"))) int explicit_default(void) { return 1; }
9 __attribute__((target_clones("dotprod", "lse"))) int explicit_default(void) { return 2; }
10 __attribute__((target_version("rdma"))) int explicit_default(void) { return 3; }
12 int foo(void) { return explicit_default(); }
13 #endif
15 __attribute__((target_version("jscvt"))) int implicit_default(void) { return 1; }
16 __attribute__((target_clones("dotprod", "lse"))) int implicit_default(void) { return 2; }
17 __attribute__((target_version("rdma"))) int implicit_default(void) { return 3; }
19 int bar(void) { return implicit_default(); }
21 // These shouldn't generate anything.
22 int unused_version_declarations(void);
23 __attribute__((target_clones("dotprod", "lse"))) int unused_version_declarations(void);
24 __attribute__((target_version("jscvt"))) int unused_version_declarations(void);
26 // These should generate the default (mangled) version and the resolver.
27 int default_def_with_version_decls(void) { return 0; }
28 __attribute__((target_clones("dotprod", "lse"))) int default_def_with_version_decls(void);
29 __attribute__((target_version("jscvt"))) int default_def_with_version_decls(void);
31 //.
32 // CHECK: @__aarch64_cpu_features = external dso_local global { i64 }
33 // CHECK: @explicit_default = weak_odr ifunc i32 (), ptr @explicit_default.resolver
34 // CHECK: @implicit_default = weak_odr ifunc i32 (), ptr @implicit_default.resolver
35 // CHECK: @default_def_with_version_decls = weak_odr ifunc i32 (), ptr @default_def_with_version_decls.resolver
36 //.
37 // CHECK: Function Attrs: noinline nounwind optnone
38 // CHECK-LABEL: define {{[^@]+}}@explicit_default.default
39 // CHECK-SAME: () #[[ATTR0:[0-9]+]] {
40 // CHECK-NEXT: entry:
41 // CHECK-NEXT: ret i32 0
44 // CHECK: Function Attrs: noinline nounwind optnone
45 // CHECK-LABEL: define {{[^@]+}}@explicit_default._Mjscvt
46 // CHECK-SAME: () #[[ATTR1:[0-9]+]] {
47 // CHECK-NEXT: entry:
48 // CHECK-NEXT: ret i32 1
51 // CHECK: Function Attrs: noinline nounwind optnone
52 // CHECK-LABEL: define {{[^@]+}}@explicit_default._Mdotprod
53 // CHECK-SAME: () #[[ATTR2:[0-9]+]] {
54 // CHECK-NEXT: entry:
55 // CHECK-NEXT: ret i32 2
58 // CHECK: Function Attrs: noinline nounwind optnone
59 // CHECK-LABEL: define {{[^@]+}}@explicit_default._Mlse
60 // CHECK-SAME: () #[[ATTR3:[0-9]+]] {
61 // CHECK-NEXT: entry:
62 // CHECK-NEXT: ret i32 2
65 // CHECK-LABEL: define {{[^@]+}}@explicit_default.resolver() comdat {
66 // CHECK-NEXT: resolver_entry:
67 // CHECK-NEXT: call void @__init_cpu_features_resolver()
68 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
69 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1048832
70 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1048832
71 // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
72 // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
73 // CHECK: resolver_return:
74 // CHECK-NEXT: ret ptr @explicit_default._Mjscvt
75 // CHECK: resolver_else:
76 // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
77 // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 832
78 // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 832
79 // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
80 // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
81 // CHECK: resolver_return1:
82 // CHECK-NEXT: ret ptr @explicit_default._Mrdm
83 // CHECK: resolver_else2:
84 // CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
85 // CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 784
86 // CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 784
87 // CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]
88 // CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
89 // CHECK: resolver_return3:
90 // CHECK-NEXT: ret ptr @explicit_default._Mdotprod
91 // CHECK: resolver_else4:
92 // CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
93 // CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 128
94 // CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 128
95 // CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]]
96 // CHECK-NEXT: br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]]
97 // CHECK: resolver_return5:
98 // CHECK-NEXT: ret ptr @explicit_default._Mlse
99 // CHECK: resolver_else6:
100 // CHECK-NEXT: ret ptr @explicit_default.default
103 // CHECK: Function Attrs: noinline nounwind optnone
104 // CHECK-LABEL: define {{[^@]+}}@explicit_default._Mrdm
105 // CHECK-SAME: () #[[ATTR4:[0-9]+]] {
106 // CHECK-NEXT: entry:
107 // CHECK-NEXT: ret i32 3
110 // CHECK: Function Attrs: noinline nounwind optnone
111 // CHECK-LABEL: define {{[^@]+}}@foo
112 // CHECK-SAME: () #[[ATTR0]] {
113 // CHECK-NEXT: entry:
114 // CHECK-NEXT: [[CALL:%.*]] = call i32 @explicit_default()
115 // CHECK-NEXT: ret i32 [[CALL]]
118 // CHECK: Function Attrs: noinline nounwind optnone
119 // CHECK-LABEL: define {{[^@]+}}@implicit_default._Mjscvt
120 // CHECK-SAME: () #[[ATTR1]] {
121 // CHECK-NEXT: entry:
122 // CHECK-NEXT: ret i32 1
125 // CHECK: Function Attrs: noinline nounwind optnone
126 // CHECK-LABEL: define {{[^@]+}}@implicit_default._Mdotprod
127 // CHECK-SAME: () #[[ATTR2]] {
128 // CHECK-NEXT: entry:
129 // CHECK-NEXT: ret i32 2
132 // CHECK: Function Attrs: noinline nounwind optnone
133 // CHECK-LABEL: define {{[^@]+}}@implicit_default._Mlse
134 // CHECK-SAME: () #[[ATTR3]] {
135 // CHECK-NEXT: entry:
136 // CHECK-NEXT: ret i32 2
139 // CHECK-LABEL: define {{[^@]+}}@implicit_default.resolver() comdat {
140 // CHECK-NEXT: resolver_entry:
141 // CHECK-NEXT: call void @__init_cpu_features_resolver()
142 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
143 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1048832
144 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1048832
145 // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
146 // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
147 // CHECK: resolver_return:
148 // CHECK-NEXT: ret ptr @implicit_default._Mjscvt
149 // CHECK: resolver_else:
150 // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
151 // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 832
152 // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 832
153 // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
154 // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
155 // CHECK: resolver_return1:
156 // CHECK-NEXT: ret ptr @implicit_default._Mrdm
157 // CHECK: resolver_else2:
158 // CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
159 // CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 784
160 // CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 784
161 // CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]
162 // CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
163 // CHECK: resolver_return3:
164 // CHECK-NEXT: ret ptr @implicit_default._Mdotprod
165 // CHECK: resolver_else4:
166 // CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
167 // CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 128
168 // CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 128
169 // CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]]
170 // CHECK-NEXT: br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]]
171 // CHECK: resolver_return5:
172 // CHECK-NEXT: ret ptr @implicit_default._Mlse
173 // CHECK: resolver_else6:
174 // CHECK-NEXT: ret ptr @implicit_default.default
177 // CHECK: Function Attrs: noinline nounwind optnone
178 // CHECK-LABEL: define {{[^@]+}}@implicit_default._Mrdm
179 // CHECK-SAME: () #[[ATTR4]] {
180 // CHECK-NEXT: entry:
181 // CHECK-NEXT: ret i32 3
184 // CHECK: Function Attrs: noinline nounwind optnone
185 // CHECK-LABEL: define {{[^@]+}}@bar
186 // CHECK-SAME: () #[[ATTR0]] {
187 // CHECK-NEXT: entry:
188 // CHECK-NEXT: [[CALL:%.*]] = call i32 @implicit_default()
189 // CHECK-NEXT: ret i32 [[CALL]]
192 // CHECK: Function Attrs: noinline nounwind optnone
193 // CHECK-LABEL: define {{[^@]+}}@default_def_with_version_decls.default
194 // CHECK-SAME: () #[[ATTR0]] {
195 // CHECK-NEXT: entry:
196 // CHECK-NEXT: ret i32 0
199 // CHECK: Function Attrs: noinline nounwind optnone
200 // CHECK-LABEL: define {{[^@]+}}@implicit_default.default
201 // CHECK-SAME: () #[[ATTR6:[0-9]+]] {
202 // CHECK-NEXT: entry:
203 // CHECK-NEXT: ret i32 2
206 // CHECK-LABEL: define {{[^@]+}}@default_def_with_version_decls.resolver() comdat {
207 // CHECK-NEXT: resolver_entry:
208 // CHECK-NEXT: call void @__init_cpu_features_resolver()
209 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
210 // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1048832
211 // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1048832
212 // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
213 // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
214 // CHECK: resolver_return:
215 // CHECK-NEXT: ret ptr @default_def_with_version_decls._Mjscvt
216 // CHECK: resolver_else:
217 // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
218 // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 784
219 // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 784
220 // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
221 // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
222 // CHECK: resolver_return1:
223 // CHECK-NEXT: ret ptr @default_def_with_version_decls._Mdotprod
224 // CHECK: resolver_else2:
225 // CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
226 // CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 128
227 // CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 128
228 // CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]
229 // CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
230 // CHECK: resolver_return3:
231 // CHECK-NEXT: ret ptr @default_def_with_version_decls._Mlse
232 // CHECK: resolver_else4:
233 // CHECK-NEXT: ret ptr @default_def_with_version_decls.default
236 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
237 // CHECK-NOFMV-LABEL: define {{[^@]+}}@implicit_default
238 // CHECK-NOFMV-SAME: () #[[ATTR0:[0-9]+]] {
239 // CHECK-NOFMV-NEXT: entry:
240 // CHECK-NOFMV-NEXT: ret i32 2
243 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
244 // CHECK-NOFMV-LABEL: define {{[^@]+}}@bar
245 // CHECK-NOFMV-SAME: () #[[ATTR0]] {
246 // CHECK-NOFMV-NEXT: entry:
247 // CHECK-NOFMV-NEXT: [[CALL:%.*]] = call i32 @implicit_default()
248 // CHECK-NOFMV-NEXT: ret i32 [[CALL]]
251 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
252 // CHECK-NOFMV-LABEL: define {{[^@]+}}@default_def_with_version_decls
253 // CHECK-NOFMV-SAME: () #[[ATTR0]] {
254 // CHECK-NOFMV-NEXT: entry:
255 // CHECK-NOFMV-NEXT: ret i32 0
258 // CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
259 // CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
261 // CHECK-NOFMV: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
262 // CHECK-NOFMV: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}