clang/test/CodeGen/AArch64/poly64.c

   1 // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
   2 // RUN:  -ffp-contract=fast -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg \
   3 // RUN:  | FileCheck %s
   4
   5 // REQUIRES: aarch64-registered-target || arm-registered-target
   6
   7 #include <arm_neon.h>
   8
   9 // CHECK-LABEL: define{{.*}} <1 x i64> @test_vceq_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
  10 // CHECK:   [[CMP_I:%.*]] = icmp eq <1 x i64> %a, %b
  11 // CHECK:   [[SEXT_I:%.*]] = sext <1 x i1> [[CMP_I]] to <1 x i64>
  12 // CHECK:   ret <1 x i64> [[SEXT_I]]
  13 uint64x1_t test_vceq_p64(poly64x1_t a, poly64x1_t b) {
  14   return vceq_p64(a, b);
  15 }
  16
  17 // CHECK-LABEL: define{{.*}} <2 x i64> @test_vceqq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
  18 // CHECK:   [[CMP_I:%.*]] = icmp eq <2 x i64> %a, %b
  19 // CHECK:   [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i64>
  20 // CHECK:   ret <2 x i64> [[SEXT_I]]
  21 uint64x2_t test_vceqq_p64(poly64x2_t a, poly64x2_t b) {
  22   return vceqq_p64(a, b);
  23 }
  24
  25 // CHECK-LABEL: define{{.*}} <1 x i64> @test_vtst_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
  26 // CHECK:   [[TMP4:%.*]] = and <1 x i64> %a, %b
  27 // CHECK:   [[TMP5:%.*]] = icmp ne <1 x i64> [[TMP4]], zeroinitializer
  28 // CHECK:   [[VTST_I:%.*]] = sext <1 x i1> [[TMP5]] to <1 x i64>
  29 // CHECK:   ret <1 x i64> [[VTST_I]]
  30 uint64x1_t test_vtst_p64(poly64x1_t a, poly64x1_t b) {
  31   return vtst_p64(a, b);
  32 }
  33
  34 // CHECK-LABEL: define{{.*}} <2 x i64> @test_vtstq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
  35 // CHECK:   [[TMP4:%.*]] = and <2 x i64> %a, %b
  36 // CHECK:   [[TMP5:%.*]] = icmp ne <2 x i64> [[TMP4]], zeroinitializer
  37 // CHECK:   [[VTST_I:%.*]] = sext <2 x i1> [[TMP5]] to <2 x i64>
  38 // CHECK:   ret <2 x i64> [[VTST_I]]
  39 uint64x2_t test_vtstq_p64(poly64x2_t a, poly64x2_t b) {
  40   return vtstq_p64(a, b);
  41 }
  42
  43 // CHECK-LABEL: define{{.*}} <1 x i64> @test_vbsl_p64(<1 x i64> noundef %a, <1 x i64> noundef %b, <1 x i64> noundef %c) #0 {
  44 // CHECK:   [[VBSL3_I:%.*]] = and <1 x i64> %a, %b
  45 // CHECK:   [[TMP3:%.*]] = xor <1 x i64> %a, splat (i64 -1)
  46 // CHECK:   [[VBSL4_I:%.*]] = and <1 x i64> [[TMP3]], %c
  47 // CHECK:   [[VBSL5_I:%.*]] = or <1 x i64> [[VBSL3_I]], [[VBSL4_I]]
  48 // CHECK:   ret <1 x i64> [[VBSL5_I]]
  49 poly64x1_t test_vbsl_p64(poly64x1_t a, poly64x1_t b, poly64x1_t c) {
  50   return vbsl_p64(a, b, c);
  51 }
  52
  53 // CHECK-LABEL: define{{.*}} <2 x i64> @test_vbslq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b, <2 x i64> noundef %c) #0 {
  54 // CHECK:   [[VBSL3_I:%.*]] = and <2 x i64> %a, %b
  55 // CHECK:   [[TMP3:%.*]] = xor <2 x i64> %a, splat (i64 -1)
  56 // CHECK:   [[VBSL4_I:%.*]] = and <2 x i64> [[TMP3]], %c
  57 // CHECK:   [[VBSL5_I:%.*]] = or <2 x i64> [[VBSL3_I]], [[VBSL4_I]]
  58 // CHECK:   ret <2 x i64> [[VBSL5_I]]
  59 poly64x2_t test_vbslq_p64(poly64x2_t a, poly64x2_t b, poly64x2_t c) {
  60   return vbslq_p64(a, b, c);
  61 }
  62
  63 // CHECK-LABEL: define{{.*}} i64 @test_vget_lane_p64(<1 x i64> noundef %v) #0 {
  64 // CHECK:   [[VGET_LANE:%.*]] = extractelement <1 x i64> %v, i32 0
  65 // CHECK:   ret i64 [[VGET_LANE]]
  66 poly64_t test_vget_lane_p64(poly64x1_t v) {
  67   return vget_lane_p64(v, 0);
  68 }
  69
  70 // CHECK-LABEL: define{{.*}} i64 @test_vgetq_lane_p64(<2 x i64> noundef %v) #0 {
  71 // CHECK:   [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %v, i32 1
  72 // CHECK:   ret i64 [[VGETQ_LANE]]
  73 poly64_t test_vgetq_lane_p64(poly64x2_t v) {
  74   return vgetq_lane_p64(v, 1);
  75 }
  76
  77 // CHECK-LABEL: define{{.*}} <1 x i64> @test_vset_lane_p64(i64 noundef %a, <1 x i64> noundef %v) #0 {
  78 // CHECK:   [[VSET_LANE:%.*]] = insertelement <1 x i64> %v, i64 %a, i32 0
  79 // CHECK:   ret <1 x i64> [[VSET_LANE]]
  80 poly64x1_t test_vset_lane_p64(poly64_t a, poly64x1_t v) {
  81   return vset_lane_p64(a, v, 0);
  82 }
  83
  84 // CHECK-LABEL: define{{.*}} <2 x i64> @test_vsetq_lane_p64(i64 noundef %a, <2 x i64> noundef %v) #0 {
  85 // CHECK:   [[VSET_LANE:%.*]] = insertelement <2 x i64> %v, i64 %a, i32 1
  86 // CHECK:   ret <2 x i64> [[VSET_LANE]]
  87 poly64x2_t test_vsetq_lane_p64(poly64_t a, poly64x2_t v) {
  88   return vsetq_lane_p64(a, v, 1);
  89 }
  90
  91 // CHECK-LABEL: define{{.*}} <1 x i64> @test_vcopy_lane_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
  92 // CHECK:   [[VGET_LANE:%.*]] = extractelement <1 x i64> %b, i32 0
  93 // CHECK:   [[VSET_LANE:%.*]] = insertelement <1 x i64> %a, i64 [[VGET_LANE]], i32 0
  94 // CHECK:   ret <1 x i64> [[VSET_LANE]]
  95 poly64x1_t test_vcopy_lane_p64(poly64x1_t a, poly64x1_t b) {
  96   return vcopy_lane_p64(a, 0, b, 0);
  97
  98 }
  99
 100 // CHECK-LABEL: define{{.*}} <2 x i64> @test_vcopyq_lane_p64(<2 x i64> noundef %a, <1 x i64> noundef %b) #0 {
 101 // CHECK:   [[VGET_LANE:%.*]] = extractelement <1 x i64> %b, i32 0
 102 // CHECK:   [[VSET_LANE:%.*]] = insertelement <2 x i64> %a, i64 [[VGET_LANE]], i32 1
 103 // CHECK:   ret <2 x i64> [[VSET_LANE]]
 104 poly64x2_t test_vcopyq_lane_p64(poly64x2_t a, poly64x1_t b) {
 105   return vcopyq_lane_p64(a, 1, b, 0);
 106 }
 107
 108 // CHECK-LABEL: define{{.*}} <2 x i64> @test_vcopyq_laneq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
 109 // CHECK:   [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %b, i32 1
 110 // CHECK:   [[VSET_LANE:%.*]] = insertelement <2 x i64> %a, i64 [[VGETQ_LANE]], i32 1
 111 // CHECK:   ret <2 x i64> [[VSET_LANE]]
 112 poly64x2_t test_vcopyq_laneq_p64(poly64x2_t a, poly64x2_t b) {
 113   return vcopyq_laneq_p64(a, 1, b, 1);
 114 }
 115
 116 // CHECK-LABEL: define{{.*}} <1 x i64> @test_vcreate_p64(i64 noundef %a) #0 {
 117 // CHECK:   [[TMP0:%.*]] = bitcast i64 %a to <1 x i64>
 118 // CHECK:   ret <1 x i64> [[TMP0]]
 119 poly64x1_t test_vcreate_p64(uint64_t a) {
 120   return vcreate_p64(a);
 121 }
 122
 123 // CHECK-LABEL: define{{.*}} <1 x i64> @test_vdup_n_p64(i64 noundef %a) #0 {
 124 // CHECK:   [[VECINIT_I:%.*]] = insertelement <1 x i64> poison, i64 %a, i32 0
 125 // CHECK:   ret <1 x i64> [[VECINIT_I]]
 126 poly64x1_t test_vdup_n_p64(poly64_t a) {
 127   return vdup_n_p64(a);
 128 }
 129 // CHECK-LABEL: define{{.*}} <2 x i64> @test_vdupq_n_p64(i64 noundef %a) #0 {
 130 // CHECK:   [[VECINIT_I:%.*]] = insertelement <2 x i64> poison, i64 %a, i32 0
 131 // CHECK:   [[VECINIT1_I:%.*]] = insertelement <2 x i64> [[VECINIT_I]], i64 %a, i32 1
 132 // CHECK:   ret <2 x i64> [[VECINIT1_I]]
 133 poly64x2_t test_vdupq_n_p64(poly64_t a) {
 134   return vdupq_n_p64(a);
 135 }
 136
 137 // CHECK-LABEL: define{{.*}} <1 x i64> @test_vmov_n_p64(i64 noundef %a) #0 {
 138 // CHECK:   [[VECINIT_I:%.*]] = insertelement <1 x i64> poison, i64 %a, i32 0
 139 // CHECK:   ret <1 x i64> [[VECINIT_I]]
 140 poly64x1_t test_vmov_n_p64(poly64_t a) {
 141   return vmov_n_p64(a);
 142 }
 143
 144 // CHECK-LABEL: define{{.*}} <2 x i64> @test_vmovq_n_p64(i64 noundef %a) #0 {
 145 // CHECK:   [[VECINIT_I:%.*]] = insertelement <2 x i64> poison, i64 %a, i32 0
 146 // CHECK:   [[VECINIT1_I:%.*]] = insertelement <2 x i64> [[VECINIT_I]], i64 %a, i32 1
 147 // CHECK:   ret <2 x i64> [[VECINIT1_I]]
 148 poly64x2_t test_vmovq_n_p64(poly64_t a) {
 149   return vmovq_n_p64(a);
 150 }
 151
 152 // CHECK-LABEL: define{{.*}} <1 x i64> @test_vdup_lane_p64(<1 x i64> noundef %vec) #0 {
 153 // CHECK:    [[TMP0:%.*]] = bitcast <1 x i64> [[VEC:%.*]] to <8 x i8>
 154 // CHECK:    [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
 155 // CHECK:    [[LANE:%.*]] = shufflevector <1 x i64> [[TMP1]], <1 x i64> [[TMP1]], <1 x i32> zeroinitializer
 156 // CHECK:    ret <1 x i64> [[LANE]]
 157 poly64x1_t test_vdup_lane_p64(poly64x1_t vec) {
 158   return vdup_lane_p64(vec, 0);
 159 }
 160
 161 // CHECK-LABEL: define{{.*}} <2 x i64> @test_vdupq_lane_p64(<1 x i64> noundef %vec) #0 {
 162 // CHECK:    [[TMP0:%.*]] = bitcast <1 x i64> [[VEC:%.*]] to <8 x i8>
 163 // CHECK:    [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
 164 // CHECK:    [[LANE:%.*]] = shufflevector <1 x i64> [[TMP1]], <1 x i64> [[TMP1]], <2 x i32> zeroinitializer
 165 // CHECK:    ret <2 x i64> [[LANE]]
 166 poly64x2_t test_vdupq_lane_p64(poly64x1_t vec) {
 167   return vdupq_lane_p64(vec, 0);
 168 }
 169
 170 // CHECK-LABEL: define{{.*}} <2 x i64> @test_vdupq_laneq_p64(<2 x i64> noundef %vec) #0 {
 171 // CHECK:    [[TMP0:%.*]] = bitcast <2 x i64> [[VEC:%.*]] to <16 x i8>
 172 // CHECK:    [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
 173 // CHECK:    [[LANE:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> [[TMP1]], <2 x i32> <i32 1, i32 1>
 174 // CHECK:    ret <2 x i64> [[LANE]]
 175 poly64x2_t test_vdupq_laneq_p64(poly64x2_t vec) {
 176   return vdupq_laneq_p64(vec, 1);
 177 }
 178
 179 // CHECK-LABEL: define{{.*}} <2 x i64> @test_vcombine_p64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 {
 180 // CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <1 x i64> %low, <1 x i64> %high, <2 x i32> <i32 0, i32 1>
 181 // CHECK:   ret <2 x i64> [[SHUFFLE_I]]
 182 poly64x2_t test_vcombine_p64(poly64x1_t low, poly64x1_t high) {
 183   return vcombine_p64(low, high);
 184 }
 185
 186 // CHECK-LABEL: define{{.*}} <1 x i64> @test_vld1_p64(ptr noundef %ptr) #0 {
 187 // CHECK:   [[TMP2:%.*]] = load <1 x i64>, ptr %ptr
 188 // CHECK:   ret <1 x i64> [[TMP2]]
 189 poly64x1_t test_vld1_p64(poly64_t const * ptr) {
 190   return vld1_p64(ptr);
 191 }
 192
 193 // CHECK-LABEL: define{{.*}} <2 x i64> @test_vld1q_p64(ptr noundef %ptr) #0 {
 194 // CHECK:   [[TMP2:%.*]] = load <2 x i64>, ptr %ptr
 195 // CHECK:   ret <2 x i64> [[TMP2]]
 196 poly64x2_t test_vld1q_p64(poly64_t const * ptr) {
 197   return vld1q_p64(ptr);
 198 }
 199
 200 // CHECK-LABEL: define{{.*}} void @test_vst1_p64(ptr noundef %ptr, <1 x i64> noundef %val) #0 {
 201 // CHECK:   [[TMP1:%.*]] = bitcast <1 x i64> %val to <8 x i8>
 202 // CHECK:   [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
 203 // CHECK:   store <1 x i64> [[TMP3]], ptr %ptr
 204 // CHECK:   ret void
 205 void test_vst1_p64(poly64_t * ptr, poly64x1_t val) {
 206   return vst1_p64(ptr, val);
 207 }
 208
 209 // CHECK-LABEL: define{{.*}} void @test_vst1q_p64(ptr noundef %ptr, <2 x i64> noundef %val) #0 {
 210 // CHECK:   [[TMP1:%.*]] = bitcast <2 x i64> %val to <16 x i8>
 211 // CHECK:   [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
 212 // CHECK:   store <2 x i64> [[TMP3]], ptr %ptr
 213 // CHECK:   ret void
 214 void test_vst1q_p64(poly64_t * ptr, poly64x2_t val) {
 215   return vst1q_p64(ptr, val);
 216 }
 217
 218 // CHECK-LABEL: define{{.*}} %struct.poly64x1x2_t @test_vld2_p64(ptr noundef %ptr) #0 {
 219 // CHECK:   [[RETVAL:%.*]] = alloca %struct.poly64x1x2_t, align 8
 220 // CHECK:   [[__RET:%.*]] = alloca %struct.poly64x1x2_t, align 8
 221 // CHECK:   [[VLD2:%.*]] = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2.v1i64.p0(ptr %ptr)
 222 // CHECK:   store { <1 x i64>, <1 x i64> } [[VLD2]], ptr [[__RET]]
 223 // CHECK:   call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i64 16, i1 false)
 224 // CHECK:   [[TMP6:%.*]] = load %struct.poly64x1x2_t, ptr [[RETVAL]], align 8
 225 // CHECK:   ret %struct.poly64x1x2_t [[TMP6]]
 226 poly64x1x2_t test_vld2_p64(poly64_t const * ptr) {
 227   return vld2_p64(ptr);
 228 }
 229
 230 // CHECK-LABEL: define{{.*}} %struct.poly64x2x2_t @test_vld2q_p64(ptr noundef %ptr) #0 {
 231 // CHECK:   [[RETVAL:%.*]] = alloca %struct.poly64x2x2_t, align 16
 232 // CHECK:   [[__RET:%.*]] = alloca %struct.poly64x2x2_t, align 16
 233 // CHECK:   [[VLD2:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2.v2i64.p0(ptr %ptr)
 234 // CHECK:   store { <2 x i64>, <2 x i64> } [[VLD2]], ptr [[__RET]]
 235 // CHECK:   call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[RETVAL]], ptr align 16 [[__RET]], i64 32, i1 false)
 236 // CHECK:   [[TMP6:%.*]] = load %struct.poly64x2x2_t, ptr [[RETVAL]], align 16
 237 // CHECK:   ret %struct.poly64x2x2_t [[TMP6]]
 238 poly64x2x2_t test_vld2q_p64(poly64_t const * ptr) {
 239   return vld2q_p64(ptr);
 240 }
 241
 242 // CHECK-LABEL: define{{.*}} %struct.poly64x1x3_t @test_vld3_p64(ptr noundef %ptr) #0 {
 243 // CHECK:   [[RETVAL:%.*]] = alloca %struct.poly64x1x3_t, align 8
 244 // CHECK:   [[__RET:%.*]] = alloca %struct.poly64x1x3_t, align 8
 245 // CHECK:   [[VLD3:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld3.v1i64.p0(ptr %ptr)
 246 // CHECK:   store { <1 x i64>, <1 x i64>, <1 x i64> } [[VLD3]], ptr [[__RET]]
 247 // CHECK:   call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i64 24, i1 false)
 248 // CHECK:   [[TMP6:%.*]] = load %struct.poly64x1x3_t, ptr [[RETVAL]], align 8
 249 // CHECK:   ret %struct.poly64x1x3_t [[TMP6]]
 250 poly64x1x3_t test_vld3_p64(poly64_t const * ptr) {
 251   return vld3_p64(ptr);
 252 }
 253
 254 // CHECK-LABEL: define{{.*}} %struct.poly64x2x3_t @test_vld3q_p64(ptr noundef %ptr) #0 {
 255 // CHECK:   [[RETVAL:%.*]] = alloca %struct.poly64x2x3_t, align 16
 256 // CHECK:   [[__RET:%.*]] = alloca %struct.poly64x2x3_t, align 16
 257 // CHECK:   [[VLD3:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld3.v2i64.p0(ptr %ptr)
 258 // CHECK:   store { <2 x i64>, <2 x i64>, <2 x i64> } [[VLD3]], ptr [[__RET]]
 259 // CHECK:   call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[RETVAL]], ptr align 16 [[__RET]], i64 48, i1 false)
 260 // CHECK:   [[TMP6:%.*]] = load %struct.poly64x2x3_t, ptr [[RETVAL]], align 16
 261 // CHECK:   ret %struct.poly64x2x3_t [[TMP6]]
 262 poly64x2x3_t test_vld3q_p64(poly64_t const * ptr) {
 263   return vld3q_p64(ptr);
 264 }
 265
 266 // CHECK-LABEL: define{{.*}} %struct.poly64x1x4_t @test_vld4_p64(ptr noundef %ptr) #0 {
 267 // CHECK:   [[RETVAL:%.*]] = alloca %struct.poly64x1x4_t, align 8
 268 // CHECK:   [[__RET:%.*]] = alloca %struct.poly64x1x4_t, align 8
 269 // CHECK:   [[VLD4:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld4.v1i64.p0(ptr %ptr)
 270 // CHECK:   store { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD4]], ptr [[__RET]]
 271 // CHECK:   call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i64 32, i1 false)
 272 // CHECK:   [[TMP6:%.*]] = load %struct.poly64x1x4_t, ptr [[RETVAL]], align 8
 273 // CHECK:   ret %struct.poly64x1x4_t [[TMP6]]
 274 poly64x1x4_t test_vld4_p64(poly64_t const * ptr) {
 275   return vld4_p64(ptr);
 276 }
 277
 278 // CHECK-LABEL: define{{.*}} %struct.poly64x2x4_t @test_vld4q_p64(ptr noundef %ptr) #0 {
 279 // CHECK:   [[RETVAL:%.*]] = alloca %struct.poly64x2x4_t, align 16
 280 // CHECK:   [[__RET:%.*]] = alloca %struct.poly64x2x4_t, align 16
 281 // CHECK:   [[VLD4:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4.v2i64.p0(ptr %ptr)
 282 // CHECK:   store { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[VLD4]], ptr [[__RET]]
 283 // CHECK:   call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[RETVAL]], ptr align 16 [[__RET]], i64 64, i1 false)
 284 // CHECK:   [[TMP6:%.*]] = load %struct.poly64x2x4_t, ptr [[RETVAL]], align 16
 285 // CHECK:   ret %struct.poly64x2x4_t [[TMP6]]
 286 poly64x2x4_t test_vld4q_p64(poly64_t const * ptr) {
 287   return vld4q_p64(ptr);
 288 }
 289
 290 // CHECK-LABEL: define{{.*}} void @test_vst2_p64(ptr noundef %ptr, [2 x <1 x i64>] alignstack(8) %val.coerce) #0 {
 291 // CHECK:   [[VAL:%.*]] = alloca %struct.poly64x1x2_t, align 8
 292 // CHECK:   [[__S1:%.*]] = alloca %struct.poly64x1x2_t, align 8
 293 // CHECK:   [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw %struct.poly64x1x2_t, ptr [[VAL]], i32 0, i32 0
 294 // CHECK:   store [2 x <1 x i64>] [[VAL]].coerce, ptr [[COERCE_DIVE]], align 8
 295 // CHECK:   call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[__S1]], ptr align 8 [[VAL]], i64 16, i1 false)
 296 // CHECK:   [[VAL1:%.*]] = getelementptr inbounds nuw %struct.poly64x1x2_t, ptr [[__S1]], i32 0, i32 0
 297 // CHECK:   [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x <1 x i64>], ptr [[VAL1]], i64 0, i64 0
 298 // CHECK:   [[TMP3:%.*]] = load <1 x i64>, ptr [[ARRAYIDX]], align 8
 299 // CHECK:   [[TMP4:%.*]] = bitcast <1 x i64> [[TMP3]] to <8 x i8>
 300 // CHECK:   [[VAL2:%.*]] = getelementptr inbounds nuw %struct.poly64x1x2_t, ptr [[__S1]], i32 0, i32 0
 301 // CHECK:   [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x <1 x i64>], ptr [[VAL2]], i64 0, i64 1
 302 // CHECK:   [[TMP5:%.*]] = load <1 x i64>, ptr [[ARRAYIDX3]], align 8
 303 // CHECK:   [[TMP6:%.*]] = bitcast <1 x i64> [[TMP5]] to <8 x i8>
 304 // CHECK:   [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <1 x i64>
 305 // CHECK:   [[TMP8:%.*]] = bitcast <8 x i8> [[TMP6]] to <1 x i64>
 306 // CHECK:   call void @llvm.aarch64.neon.st2.v1i64.p0(<1 x i64> [[TMP7]], <1 x i64> [[TMP8]], ptr %ptr)
 307 // CHECK:   ret void
 308 void test_vst2_p64(poly64_t * ptr, poly64x1x2_t val) {
 309   return vst2_p64(ptr, val);
 310 }
 311
 312 // CHECK-LABEL: define{{.*}} void @test_vst2q_p64(ptr noundef %ptr, [2 x <2 x i64>] alignstack(16) %val.coerce) #0 {
 313 // CHECK:   [[VAL:%.*]] = alloca %struct.poly64x2x2_t, align 16
 314 // CHECK:   [[__S1:%.*]] = alloca %struct.poly64x2x2_t, align 16
 315 // CHECK:   [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw %struct.poly64x2x2_t, ptr [[VAL]], i32 0, i32 0
 316 // CHECK:   store [2 x <2 x i64>] [[VAL]].coerce, ptr [[COERCE_DIVE]], align 16
 317 // CHECK:   call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[__S1]], ptr align 16 [[VAL]], i64 32, i1 false)
 318 // CHECK:   [[VAL1:%.*]] = getelementptr inbounds nuw %struct.poly64x2x2_t, ptr [[__S1]], i32 0, i32 0
 319 // CHECK:   [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x <2 x i64>], ptr [[VAL1]], i64 0, i64 0
 320 // CHECK:   [[TMP3:%.*]] = load <2 x i64>, ptr [[ARRAYIDX]], align 16
 321 // CHECK:   [[TMP4:%.*]] = bitcast <2 x i64> [[TMP3]] to <16 x i8>
 322 // CHECK:   [[VAL2:%.*]] = getelementptr inbounds nuw %struct.poly64x2x2_t, ptr [[__S1]], i32 0, i32 0
 323 // CHECK:   [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x <2 x i64>], ptr [[VAL2]], i64 0, i64 1
 324 // CHECK:   [[TMP5:%.*]] = load <2 x i64>, ptr [[ARRAYIDX3]], align 16
 325 // CHECK:   [[TMP6:%.*]] = bitcast <2 x i64> [[TMP5]] to <16 x i8>
 326 // CHECK:   [[TMP7:%.*]] = bitcast <16 x i8> [[TMP4]] to <2 x i64>
 327 // CHECK:   [[TMP8:%.*]] = bitcast <16 x i8> [[TMP6]] to <2 x i64>
 328 // CHECK:   call void @llvm.aarch64.neon.st2.v2i64.p0(<2 x i64> [[TMP7]], <2 x i64> [[TMP8]], ptr %ptr)
 329 // CHECK:   ret void
 330 void test_vst2q_p64(poly64_t * ptr, poly64x2x2_t val) {
 331   return vst2q_p64(ptr, val);
 332 }
 333
 334 // CHECK-LABEL: define{{.*}} void @test_vst3_p64(ptr noundef %ptr, [3 x <1 x i64>] alignstack(8) %val.coerce) #0 {
 335 // CHECK:   [[VAL:%.*]] = alloca %struct.poly64x1x3_t, align 8
 336 // CHECK:   [[__S1:%.*]] = alloca %struct.poly64x1x3_t, align 8
 337 // CHECK:   [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw %struct.poly64x1x3_t, ptr [[VAL]], i32 0, i32 0
 338 // CHECK:   store [3 x <1 x i64>] [[VAL]].coerce, ptr [[COERCE_DIVE]], align 8
 339 // CHECK:   call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[__S1]], ptr align 8 [[VAL]], i64 24, i1 false)
 340 // CHECK:   [[VAL1:%.*]] = getelementptr inbounds nuw %struct.poly64x1x3_t, ptr [[__S1]], i32 0, i32 0
 341 // CHECK:   [[ARRAYIDX:%.*]] = getelementptr inbounds [3 x <1 x i64>], ptr [[VAL1]], i64 0, i64 0
 342 // CHECK:   [[TMP3:%.*]] = load <1 x i64>, ptr [[ARRAYIDX]], align 8
 343 // CHECK:   [[TMP4:%.*]] = bitcast <1 x i64> [[TMP3]] to <8 x i8>
 344 // CHECK:   [[VAL2:%.*]] = getelementptr inbounds nuw %struct.poly64x1x3_t, ptr [[__S1]], i32 0, i32 0
 345 // CHECK:   [[ARRAYIDX3:%.*]] = getelementptr inbounds [3 x <1 x i64>], ptr [[VAL2]], i64 0, i64 1
 346 // CHECK:   [[TMP5:%.*]] = load <1 x i64>, ptr [[ARRAYIDX3]], align 8
 347 // CHECK:   [[TMP6:%.*]] = bitcast <1 x i64> [[TMP5]] to <8 x i8>
 348 // CHECK:   [[VAL4:%.*]] = getelementptr inbounds nuw %struct.poly64x1x3_t, ptr [[__S1]], i32 0, i32 0
 349 // CHECK:   [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x <1 x i64>], ptr [[VAL4]], i64 0, i64 2
 350 // CHECK:   [[TMP7:%.*]] = load <1 x i64>, ptr [[ARRAYIDX5]], align 8
 351 // CHECK:   [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <8 x i8>
 352 // CHECK:   [[TMP9:%.*]] = bitcast <8 x i8> [[TMP4]] to <1 x i64>
 353 // CHECK:   [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <1 x i64>
 354 // CHECK:   [[TMP11:%.*]] = bitcast <8 x i8> [[TMP8]] to <1 x i64>
 355 // CHECK:   call void @llvm.aarch64.neon.st3.v1i64.p0(<1 x i64> [[TMP9]], <1 x i64> [[TMP10]], <1 x i64> [[TMP11]], ptr %ptr)
 356 // CHECK:   ret void
 357 void test_vst3_p64(poly64_t * ptr, poly64x1x3_t val) {
 358   return vst3_p64(ptr, val);
 359 }
 360
 361 // CHECK-LABEL: define{{.*}} void @test_vst3q_p64(ptr noundef %ptr, [3 x <2 x i64>] alignstack(16) %val.coerce) #0 {
 362 // CHECK:   [[VAL:%.*]] = alloca %struct.poly64x2x3_t, align 16
 363 // CHECK:   [[__S1:%.*]] = alloca %struct.poly64x2x3_t, align 16
 364 // CHECK:   [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw %struct.poly64x2x3_t, ptr [[VAL]], i32 0, i32 0
 365 // CHECK:   store [3 x <2 x i64>] [[VAL]].coerce, ptr [[COERCE_DIVE]], align 16
 366 // CHECK:   call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[__S1]], ptr align 16 [[VAL]], i64 48, i1 false)
 367 // CHECK:   [[VAL1:%.*]] = getelementptr inbounds nuw %struct.poly64x2x3_t, ptr [[__S1]], i32 0, i32 0
 368 // CHECK:   [[ARRAYIDX:%.*]] = getelementptr inbounds [3 x <2 x i64>], ptr [[VAL1]], i64 0, i64 0
 369 // CHECK:   [[TMP3:%.*]] = load <2 x i64>, ptr [[ARRAYIDX]], align 16
 370 // CHECK:   [[TMP4:%.*]] = bitcast <2 x i64> [[TMP3]] to <16 x i8>
 371 // CHECK:   [[VAL2:%.*]] = getelementptr inbounds nuw %struct.poly64x2x3_t, ptr [[__S1]], i32 0, i32 0
 372 // CHECK:   [[ARRAYIDX3:%.*]] = getelementptr inbounds [3 x <2 x i64>], ptr [[VAL2]], i64 0, i64 1
 373 // CHECK:   [[TMP5:%.*]] = load <2 x i64>, ptr [[ARRAYIDX3]], align 16
 374 // CHECK:   [[TMP6:%.*]] = bitcast <2 x i64> [[TMP5]] to <16 x i8>
 375 // CHECK:   [[VAL4:%.*]] = getelementptr inbounds nuw %struct.poly64x2x3_t, ptr [[__S1]], i32 0, i32 0
 376 // CHECK:   [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x <2 x i64>], ptr [[VAL4]], i64 0, i64 2
 377 // CHECK:   [[TMP7:%.*]] = load <2 x i64>, ptr [[ARRAYIDX5]], align 16
 378 // CHECK:   [[TMP8:%.*]] = bitcast <2 x i64> [[TMP7]] to <16 x i8>
 379 // CHECK:   [[TMP9:%.*]] = bitcast <16 x i8> [[TMP4]] to <2 x i64>
 380 // CHECK:   [[TMP10:%.*]] = bitcast <16 x i8> [[TMP6]] to <2 x i64>
 381 // CHECK:   [[TMP11:%.*]] = bitcast <16 x i8> [[TMP8]] to <2 x i64>
 382 // CHECK:   call void @llvm.aarch64.neon.st3.v2i64.p0(<2 x i64> [[TMP9]], <2 x i64> [[TMP10]], <2 x i64> [[TMP11]], ptr %ptr)
 383 // CHECK:   ret void
 384 void test_vst3q_p64(poly64_t * ptr, poly64x2x3_t val) {
 385   return vst3q_p64(ptr, val);
 386 }
 387
 388 // CHECK-LABEL: define{{.*}} void @test_vst4_p64(ptr noundef %ptr, [4 x <1 x i64>] alignstack(8) %val.coerce) #0 {
 389 // CHECK:   [[VAL:%.*]] = alloca %struct.poly64x1x4_t, align 8
 390 // CHECK:   [[__S1:%.*]] = alloca %struct.poly64x1x4_t, align 8
 391 // CHECK:   [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw %struct.poly64x1x4_t, ptr [[VAL]], i32 0, i32 0
 392 // CHECK:   store [4 x <1 x i64>] [[VAL]].coerce, ptr [[COERCE_DIVE]], align 8
 393 // CHECK:   call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[__S1]], ptr align 8 [[VAL]], i64 32, i1 false)
 394 // CHECK:   [[VAL1:%.*]] = getelementptr inbounds nuw %struct.poly64x1x4_t, ptr [[__S1]], i32 0, i32 0
 395 // CHECK:   [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x <1 x i64>], ptr [[VAL1]], i64 0, i64 0
 396 // CHECK:   [[TMP3:%.*]] = load <1 x i64>, ptr [[ARRAYIDX]], align 8
 397 // CHECK:   [[TMP4:%.*]] = bitcast <1 x i64> [[TMP3]] to <8 x i8>
 398 // CHECK:   [[VAL2:%.*]] = getelementptr inbounds nuw %struct.poly64x1x4_t, ptr [[__S1]], i32 0, i32 0
 399 // CHECK:   [[ARRAYIDX3:%.*]] = getelementptr inbounds [4 x <1 x i64>], ptr [[VAL2]], i64 0, i64 1
 400 // CHECK:   [[TMP5:%.*]] = load <1 x i64>, ptr [[ARRAYIDX3]], align 8
 401 // CHECK:   [[TMP6:%.*]] = bitcast <1 x i64> [[TMP5]] to <8 x i8>
 402 // CHECK:   [[VAL4:%.*]] = getelementptr inbounds nuw %struct.poly64x1x4_t, ptr [[__S1]], i32 0, i32 0
 403 // CHECK:   [[ARRAYIDX5:%.*]] = getelementptr inbounds [4 x <1 x i64>], ptr [[VAL4]], i64 0, i64 2
 404 // CHECK:   [[TMP7:%.*]] = load <1 x i64>, ptr [[ARRAYIDX5]], align 8
 405 // CHECK:   [[TMP8:%.*]] = bitcast <1 x i64> [[TMP7]] to <8 x i8>
 406 // CHECK:   [[VAL6:%.*]] = getelementptr inbounds nuw %struct.poly64x1x4_t, ptr [[__S1]], i32 0, i32 0
 407 // CHECK:   [[ARRAYIDX7:%.*]] = getelementptr inbounds [4 x <1 x i64>], ptr [[VAL6]], i64 0, i64 3
 408 // CHECK:   [[TMP9:%.*]] = load <1 x i64>, ptr [[ARRAYIDX7]], align 8
 409 // CHECK:   [[TMP10:%.*]] = bitcast <1 x i64> [[TMP9]] to <8 x i8>
 410 // CHECK:   [[TMP11:%.*]] = bitcast <8 x i8> [[TMP4]] to <1 x i64>
 411 // CHECK:   [[TMP12:%.*]] = bitcast <8 x i8> [[TMP6]] to <1 x i64>
 412 // CHECK:   [[TMP13:%.*]] = bitcast <8 x i8> [[TMP8]] to <1 x i64>
 413 // CHECK:   [[TMP14:%.*]] = bitcast <8 x i8> [[TMP10]] to <1 x i64>
 414 // CHECK:   call void @llvm.aarch64.neon.st4.v1i64.p0(<1 x i64> [[TMP11]], <1 x i64> [[TMP12]], <1 x i64> [[TMP13]], <1 x i64> [[TMP14]], ptr %ptr)
 415 // CHECK:   ret void
 416 void test_vst4_p64(poly64_t * ptr, poly64x1x4_t val) {
 417   return vst4_p64(ptr, val);
 418 }
 419
 420 // CHECK-LABEL: define{{.*}} void @test_vst4q_p64(ptr noundef %ptr, [4 x <2 x i64>] alignstack(16) %val.coerce) #0 {
 421 // CHECK:   [[VAL:%.*]] = alloca %struct.poly64x2x4_t, align 16
 422 // CHECK:   [[__S1:%.*]] = alloca %struct.poly64x2x4_t, align 16
 423 // CHECK:   [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw %struct.poly64x2x4_t, ptr [[VAL]], i32 0, i32 0
 424 // CHECK:   store [4 x <2 x i64>] [[VAL]].coerce, ptr [[COERCE_DIVE]], align 16
 425 // CHECK:   call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[__S1]], ptr align 16 [[VAL]], i64 64, i1 false)
 426 // CHECK:   [[VAL1:%.*]] = getelementptr inbounds nuw %struct.poly64x2x4_t, ptr [[__S1]], i32 0, i32 0
 427 // CHECK:   [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x <2 x i64>], ptr [[VAL1]], i64 0, i64 0
 428 // CHECK:   [[TMP3:%.*]] = load <2 x i64>, ptr [[ARRAYIDX]], align 16
 429 // CHECK:   [[TMP4:%.*]] = bitcast <2 x i64> [[TMP3]] to <16 x i8>
 430 // CHECK:   [[VAL2:%.*]] = getelementptr inbounds nuw %struct.poly64x2x4_t, ptr [[__S1]], i32 0, i32 0
 431 // CHECK:   [[ARRAYIDX3:%.*]] = getelementptr inbounds [4 x <2 x i64>], ptr [[VAL2]], i64 0, i64 1
 432 // CHECK:   [[TMP5:%.*]] = load <2 x i64>, ptr [[ARRAYIDX3]], align 16
 433 // CHECK:   [[TMP6:%.*]] = bitcast <2 x i64> [[TMP5]] to <16 x i8>
 434 // CHECK:   [[VAL4:%.*]] = getelementptr inbounds nuw %struct.poly64x2x4_t, ptr [[__S1]], i32 0, i32 0
 435 // CHECK:   [[ARRAYIDX5:%.*]] = getelementptr inbounds [4 x <2 x i64>], ptr [[VAL4]], i64 0, i64 2
 436 // CHECK:   [[TMP7:%.*]] = load <2 x i64>, ptr [[ARRAYIDX5]], align 16
 437 // CHECK:   [[TMP8:%.*]] = bitcast <2 x i64> [[TMP7]] to <16 x i8>
 438 // CHECK:   [[VAL6:%.*]] = getelementptr inbounds nuw %struct.poly64x2x4_t, ptr [[__S1]], i32 0, i32 0
 439 // CHECK:   [[ARRAYIDX7:%.*]] = getelementptr inbounds [4 x <2 x i64>], ptr [[VAL6]], i64 0, i64 3
 440 // CHECK:   [[TMP9:%.*]] = load <2 x i64>, ptr [[ARRAYIDX7]], align 16
 441 // CHECK:   [[TMP10:%.*]] = bitcast <2 x i64> [[TMP9]] to <16 x i8>
 442 // CHECK:   [[TMP11:%.*]] = bitcast <16 x i8> [[TMP4]] to <2 x i64>
 443 // CHECK:   [[TMP12:%.*]] = bitcast <16 x i8> [[TMP6]] to <2 x i64>
 444 // CHECK:   [[TMP13:%.*]] = bitcast <16 x i8> [[TMP8]] to <2 x i64>
 445 // CHECK:   [[TMP14:%.*]] = bitcast <16 x i8> [[TMP10]] to <2 x i64>
 446 // CHECK:   call void @llvm.aarch64.neon.st4.v2i64.p0(<2 x i64> [[TMP11]], <2 x i64> [[TMP12]], <2 x i64> [[TMP13]], <2 x i64> [[TMP14]], ptr %ptr)
 447 // CHECK:   ret void
 448 void test_vst4q_p64(poly64_t * ptr, poly64x2x4_t val) {
 449   return vst4q_p64(ptr, val);
 450 }
 451
 452 // CHECK-LABEL: define{{.*}} <1 x i64> @test_vext_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
 453 // CHECK:   [[TMP0:%.*]] = bitcast <1 x i64> %a to <8 x i8>
 454 // CHECK:   [[TMP1:%.*]] = bitcast <1 x i64> %b to <8 x i8>
 455 // CHECK:   [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
 456 // CHECK:   [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
 457 // CHECK:   [[VEXT:%.*]] = shufflevector <1 x i64> [[TMP2]], <1 x i64> [[TMP3]], <1 x i32> zeroinitializer
 458 // CHECK:   ret <1 x i64> [[VEXT]]
 459 poly64x1_t test_vext_p64(poly64x1_t a, poly64x1_t b) {
 460   return vext_u64(a, b, 0);
 461
 462 }
 463
 464 // CHECK-LABEL: define{{.*}} <2 x i64> @test_vextq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
 465 // CHECK:   [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8>
 466 // CHECK:   [[TMP1:%.*]] = bitcast <2 x i64> %b to <16 x i8>
 467 // CHECK:   [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
 468 // CHECK:   [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
 469 // CHECK:   [[VEXT:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> [[TMP3]], <2 x i32> <i32 1, i32 2>
 470 // CHECK:   ret <2 x i64> [[VEXT]]
 471 poly64x2_t test_vextq_p64(poly64x2_t a, poly64x2_t b) {
 472   return vextq_p64(a, b, 1);
 473 }
 474
 475 // CHECK-LABEL: define{{.*}} <2 x i64> @test_vzip1q_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
 476 // CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 2>
 477 // CHECK:   ret <2 x i64> [[SHUFFLE_I]]
 478 poly64x2_t test_vzip1q_p64(poly64x2_t a, poly64x2_t b) {
 479   return vzip1q_p64(a, b);
 480 }
 481
 482 // CHECK-LABEL: define{{.*}} <2 x i64> @test_vzip2q_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
 483 // CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3>
 484 // CHECK:   ret <2 x i64> [[SHUFFLE_I]]
 485 poly64x2_t test_vzip2q_p64(poly64x2_t a, poly64x2_t b) {
 486   return vzip2q_u64(a, b);
 487 }
 488
 489 // CHECK-LABEL: define{{.*}} <2 x i64> @test_vuzp1q_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
 490 // CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 2>
 491 // CHECK:   ret <2 x i64> [[SHUFFLE_I]]
 492 poly64x2_t test_vuzp1q_p64(poly64x2_t a, poly64x2_t b) {
 493   return vuzp1q_p64(a, b);
 494 }
 495
 496 // CHECK-LABEL: define{{.*}} <2 x i64> @test_vuzp2q_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
 497 // CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3>
 498 // CHECK:   ret <2 x i64> [[SHUFFLE_I]]
 499 poly64x2_t test_vuzp2q_p64(poly64x2_t a, poly64x2_t b) {
 500   return vuzp2q_u64(a, b);
 501 }
 502
 503 // CHECK-LABEL: define{{.*}} <2 x i64> @test_vtrn1q_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
 504 // CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 2>
 505 // CHECK:   ret <2 x i64> [[SHUFFLE_I]]
 506 poly64x2_t test_vtrn1q_p64(poly64x2_t a, poly64x2_t b) {
 507   return vtrn1q_p64(a, b);
 508 }
 509
 510 // CHECK-LABEL: define{{.*}} <2 x i64> @test_vtrn2q_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
 511 // CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3>
 512 // CHECK:   ret <2 x i64> [[SHUFFLE_I]]
 513 poly64x2_t test_vtrn2q_p64(poly64x2_t a, poly64x2_t b) {
 514   return vtrn2q_u64(a, b);
 515 }
 516
 517 // CHECK-LABEL: define{{.*}} <1 x i64> @test_vsri_n_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
 518 // CHECK:   [[TMP0:%.*]] = bitcast <1 x i64> %a to <8 x i8>
 519 // CHECK:   [[TMP1:%.*]] = bitcast <1 x i64> %b to <8 x i8>
 520 // CHECK:   [[VSRI_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
 521 // CHECK:   [[VSRI_N1:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
 522 // CHECK:   [[VSRI_N2:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsri.v1i64(<1 x i64> [[VSRI_N]], <1 x i64> [[VSRI_N1]], i32 33)
 523 // CHECK:   ret <1 x i64> [[VSRI_N2]]
 524 poly64x1_t test_vsri_n_p64(poly64x1_t a, poly64x1_t b) {
 525   return vsri_n_p64(a, b, 33);
 526 }
 527
 528 // CHECK-LABEL: define{{.*}} <2 x i64> @test_vsriq_n_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
 529 // CHECK:   [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8>
 530 // CHECK:   [[TMP1:%.*]] = bitcast <2 x i64> %b to <16 x i8>
 531 // CHECK:   [[VSRI_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
 532 // CHECK:   [[VSRI_N1:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
 533 // CHECK:   [[VSRI_N2:%.*]] = call <2 x i64> @llvm.aarch64.neon.vsri.v2i64(<2 x i64> [[VSRI_N]], <2 x i64> [[VSRI_N1]], i32 64)
 534 // CHECK:   ret <2 x i64> [[VSRI_N2]]
 535 poly64x2_t test_vsriq_n_p64(poly64x2_t a, poly64x2_t b) {
 536   return vsriq_n_p64(a, b, 64);
 537 }