clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_read.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3
   2 // REQUIRES: aarch64-registered-target
   3 // RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
   4 // RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
   5 // RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64 -target-feature +sme -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
   6 // RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64 -target-feature +sme -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
   7 // RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -S -O1 -Werror -o /dev/null %s
   8
   9 #include <arm_sme.h>
  10
  11 #ifdef SME_OVERLOADED_FORMS
  12 #define SME_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A3
  13 #else
  14 #define SME_ACLE_FUNC(A1,A2,A3) A1##A2##A3
  15 #endif
  16
  17 // CHECK-C-LABEL: define dso_local <vscale x 16 x i8> @test_svread_hor_za8_s8(
  18 // CHECK-C-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
  19 // CHECK-C-NEXT:  entry:
  20 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.read.horiz.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 0, i32 [[SLICE_BASE]])
  21 // CHECK-C-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  22 //
  23 // CHECK-CXX-LABEL: define dso_local <vscale x 16 x i8> @_Z22test_svread_hor_za8_s8u10__SVInt8_tu10__SVBool_tj(
  24 // CHECK-CXX-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
  25 // CHECK-CXX-NEXT:  entry:
  26 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.read.horiz.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 0, i32 [[SLICE_BASE]])
  27 // CHECK-CXX-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  28 //
  29 svint8_t test_svread_hor_za8_s8(svint8_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
  30     return SME_ACLE_FUNC(svread_hor_za8, _s8, _m)(zd, pg, 0, slice_base);
  31 }
  32
  33 // CHECK-C-LABEL: define dso_local <vscale x 16 x i8> @test_svread_hor_za8_s8_1(
  34 // CHECK-C-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
  35 // CHECK-C-NEXT:  entry:
  36 // CHECK-C-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 15
  37 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.read.horiz.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 0, i32 [[ADD]])
  38 // CHECK-C-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  39 //
  40 // CHECK-CXX-LABEL: define dso_local <vscale x 16 x i8> @_Z24test_svread_hor_za8_s8_1u10__SVInt8_tu10__SVBool_tj(
  41 // CHECK-CXX-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
  42 // CHECK-CXX-NEXT:  entry:
  43 // CHECK-CXX-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 15
  44 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.read.horiz.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 0, i32 [[ADD]])
  45 // CHECK-CXX-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  46 //
  47 svint8_t test_svread_hor_za8_s8_1(svint8_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
  48     uint32_t slice = slice_base + 15;
  49     return SME_ACLE_FUNC(svread_hor_za8, _s8, _m)(zd, pg, 0, slice);
  50 }
  51
  52 // CHECK-C-LABEL: define dso_local <vscale x 8 x i16> @test_svread_hor_za16_s16(
  53 // CHECK-C-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
  54 // CHECK-C-NEXT:  entry:
  55 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
  56 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.read.horiz.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
  57 // CHECK-C-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
  58 //
  59 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x i16> @_Z24test_svread_hor_za16_s16u11__SVInt16_tu10__SVBool_tj(
  60 // CHECK-CXX-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
  61 // CHECK-CXX-NEXT:  entry:
  62 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
  63 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.read.horiz.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
  64 // CHECK-CXX-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
  65 //
  66 svint16_t test_svread_hor_za16_s16(svint16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
  67      return SME_ACLE_FUNC(svread_hor_za16, _s16, _m)(zd, pg, 0, slice_base);
  68 }
  69
  70 // CHECK-C-LABEL: define dso_local <vscale x 8 x i16> @test_svread_hor_za16_s16_1(
  71 // CHECK-C-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
  72 // CHECK-C-NEXT:  entry:
  73 // CHECK-C-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 7
  74 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
  75 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.read.horiz.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 1, i32 [[ADD]])
  76 // CHECK-C-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
  77 //
  78 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x i16> @_Z26test_svread_hor_za16_s16_1u11__SVInt16_tu10__SVBool_tj(
  79 // CHECK-CXX-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
  80 // CHECK-CXX-NEXT:  entry:
  81 // CHECK-CXX-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 7
  82 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
  83 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.read.horiz.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 1, i32 [[ADD]])
  84 // CHECK-CXX-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
  85 //
  86 svint16_t test_svread_hor_za16_s16_1(svint16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
  87      uint32_t slice = slice_base + 7;
  88      return SME_ACLE_FUNC(svread_hor_za16, _s16, _m)(zd, pg, 1, slice);
  89 }
  90
  91 // CHECK-C-LABEL: define dso_local <vscale x 4 x i32> @test_svread_hor_za32_s32(
  92 // CHECK-C-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
  93 // CHECK-C-NEXT:  entry:
  94 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
  95 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.read.horiz.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
  96 // CHECK-C-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
  97 //
  98 // CHECK-CXX-LABEL: define dso_local <vscale x 4 x i32> @_Z24test_svread_hor_za32_s32u11__SVInt32_tu10__SVBool_tj(
  99 // CHECK-CXX-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 100 // CHECK-CXX-NEXT:  entry:
 101 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 102 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.read.horiz.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 103 // CHECK-CXX-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 104 //
 105 svint32_t test_svread_hor_za32_s32(svint32_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 106     return SME_ACLE_FUNC(svread_hor_za32, _s32, _m)(zd, pg, 0, slice_base);
 107 }
 108
 109 // CHECK-C-LABEL: define dso_local <vscale x 4 x i32> @test_svread_hor_za32_s32_1(
 110 // CHECK-C-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 111 // CHECK-C-NEXT:  entry:
 112 // CHECK-C-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 3
 113 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 114 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.read.horiz.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 3, i32 [[ADD]])
 115 // CHECK-C-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 116 //
 117 // CHECK-CXX-LABEL: define dso_local <vscale x 4 x i32> @_Z26test_svread_hor_za32_s32_1u11__SVInt32_tu10__SVBool_tj(
 118 // CHECK-CXX-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 119 // CHECK-CXX-NEXT:  entry:
 120 // CHECK-CXX-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 3
 121 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 122 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.read.horiz.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 3, i32 [[ADD]])
 123 // CHECK-CXX-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 124 //
 125 svint32_t test_svread_hor_za32_s32_1(svint32_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 126     uint32_t slice = slice_base + 3;
 127     return SME_ACLE_FUNC(svread_hor_za32, _s32, _m)(zd, pg, 3, slice);
 128 }
 129
 130 // CHECK-C-LABEL: define dso_local <vscale x 2 x i64> @test_svread_hor_za64_s64(
 131 // CHECK-C-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 132 // CHECK-C-NEXT:  entry:
 133 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
 134 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.read.horiz.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 135 // CHECK-C-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 136 //
 137 // CHECK-CXX-LABEL: define dso_local <vscale x 2 x i64> @_Z24test_svread_hor_za64_s64u11__SVInt64_tu10__SVBool_tj(
 138 // CHECK-CXX-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 139 // CHECK-CXX-NEXT:  entry:
 140 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
 141 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.read.horiz.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 142 // CHECK-CXX-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 143 //
 144 svint64_t test_svread_hor_za64_s64(svint64_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 145     return SME_ACLE_FUNC(svread_hor_za64, _s64, _m)(zd, pg, 0, slice_base);
 146 }
 147
 148 // CHECK-C-LABEL: define dso_local <vscale x 2 x i64> @test_svread_hor_za64_s64_1(
 149 // CHECK-C-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 150 // CHECK-C-NEXT:  entry:
 151 // CHECK-C-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 1
 152 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
 153 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.read.horiz.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 7, i32 [[ADD]])
 154 // CHECK-C-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 155 //
 156 // CHECK-CXX-LABEL: define dso_local <vscale x 2 x i64> @_Z26test_svread_hor_za64_s64_1u11__SVInt64_tu10__SVBool_tj(
 157 // CHECK-CXX-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 158 // CHECK-CXX-NEXT:  entry:
 159 // CHECK-CXX-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 1
 160 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
 161 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.read.horiz.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 7, i32 [[ADD]])
 162 // CHECK-CXX-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 163 //
 164 svint64_t test_svread_hor_za64_s64_1(svint64_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 165     uint32_t slice = slice_base + 1;
 166     return SME_ACLE_FUNC(svread_hor_za64, _s64, _m)(zd, pg, 7, slice);
 167 }
 168
 169 // CHECK-C-LABEL: define dso_local <vscale x 16 x i8> @test_svread_hor_za8_u8(
 170 // CHECK-C-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 171 // CHECK-C-NEXT:  entry:
 172 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.read.horiz.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 0, i32 [[SLICE_BASE]])
 173 // CHECK-C-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 174 //
 175 // CHECK-CXX-LABEL: define dso_local <vscale x 16 x i8> @_Z22test_svread_hor_za8_u8u11__SVUint8_tu10__SVBool_tj(
 176 // CHECK-CXX-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 177 // CHECK-CXX-NEXT:  entry:
 178 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.read.horiz.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 0, i32 [[SLICE_BASE]])
 179 // CHECK-CXX-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 180 //
 181 svuint8_t test_svread_hor_za8_u8(svuint8_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 182     return SME_ACLE_FUNC(svread_hor_za8, _u8, _m)(zd, pg, 0, slice_base);
 183 }
 184
 185 // CHECK-C-LABEL: define dso_local <vscale x 16 x i8> @test_svread_hor_za8_u8_1(
 186 // CHECK-C-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 187 // CHECK-C-NEXT:  entry:
 188 // CHECK-C-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 15
 189 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.read.horiz.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 0, i32 [[ADD]])
 190 // CHECK-C-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 191 //
 192 // CHECK-CXX-LABEL: define dso_local <vscale x 16 x i8> @_Z24test_svread_hor_za8_u8_1u11__SVUint8_tu10__SVBool_tj(
 193 // CHECK-CXX-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 194 // CHECK-CXX-NEXT:  entry:
 195 // CHECK-CXX-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 15
 196 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.read.horiz.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 0, i32 [[ADD]])
 197 // CHECK-CXX-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 198 //
 199 svuint8_t test_svread_hor_za8_u8_1(svuint8_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 200     uint32_t slice = slice_base + 15;
 201     return SME_ACLE_FUNC(svread_hor_za8, _u8, _m)(zd, pg, 0, slice);
 202 }
 203
 204 // CHECK-C-LABEL: define dso_local <vscale x 8 x i16> @test_svread_hor_za16_u16(
 205 // CHECK-C-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 206 // CHECK-C-NEXT:  entry:
 207 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 208 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.read.horiz.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 209 // CHECK-C-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 210 //
 211 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x i16> @_Z24test_svread_hor_za16_u16u12__SVUint16_tu10__SVBool_tj(
 212 // CHECK-CXX-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 213 // CHECK-CXX-NEXT:  entry:
 214 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 215 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.read.horiz.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 216 // CHECK-CXX-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 217 //
 218 svuint16_t test_svread_hor_za16_u16(svuint16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 219     return SME_ACLE_FUNC(svread_hor_za16, _u16, _m)(zd, pg, 0, slice_base);
 220 }
 221
 222 // CHECK-C-LABEL: define dso_local <vscale x 8 x i16> @test_svread_hor_za16_u16_1(
 223 // CHECK-C-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 224 // CHECK-C-NEXT:  entry:
 225 // CHECK-C-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 7
 226 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 227 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.read.horiz.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 1, i32 [[ADD]])
 228 // CHECK-C-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 229 //
 230 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x i16> @_Z26test_svread_hor_za16_u16_1u12__SVUint16_tu10__SVBool_tj(
 231 // CHECK-CXX-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 232 // CHECK-CXX-NEXT:  entry:
 233 // CHECK-CXX-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 7
 234 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 235 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.read.horiz.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 1, i32 [[ADD]])
 236 // CHECK-CXX-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 237 //
 238 svuint16_t test_svread_hor_za16_u16_1(svuint16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 239     uint32_t slice = slice_base + 7;
 240     return SME_ACLE_FUNC(svread_hor_za16, _u16, _m)(zd, pg, 1, slice);
 241 }
 242
 243 // CHECK-C-LABEL: define dso_local <vscale x 4 x i32> @test_svread_hor_za32_u32(
 244 // CHECK-C-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 245 // CHECK-C-NEXT:  entry:
 246 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 247 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.read.horiz.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 248 // CHECK-C-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 249 //
 250 // CHECK-CXX-LABEL: define dso_local <vscale x 4 x i32> @_Z24test_svread_hor_za32_u32u12__SVUint32_tu10__SVBool_tj(
 251 // CHECK-CXX-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 252 // CHECK-CXX-NEXT:  entry:
 253 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 254 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.read.horiz.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 255 // CHECK-CXX-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 256 //
 257 svuint32_t test_svread_hor_za32_u32(svuint32_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 258     return SME_ACLE_FUNC(svread_hor_za32, _u32, _m)(zd, pg, 0, slice_base);
 259 }
 260
 261 // CHECK-C-LABEL: define dso_local <vscale x 4 x i32> @test_svread_hor_za32_u32_1(
 262 // CHECK-C-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 263 // CHECK-C-NEXT:  entry:
 264 // CHECK-C-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 3
 265 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 266 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.read.horiz.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 3, i32 [[ADD]])
 267 // CHECK-C-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 268 //
 269 // CHECK-CXX-LABEL: define dso_local <vscale x 4 x i32> @_Z26test_svread_hor_za32_u32_1u12__SVUint32_tu10__SVBool_tj(
 270 // CHECK-CXX-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 271 // CHECK-CXX-NEXT:  entry:
 272 // CHECK-CXX-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 3
 273 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 274 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.read.horiz.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 3, i32 [[ADD]])
 275 // CHECK-CXX-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 276 //
 277 svuint32_t test_svread_hor_za32_u32_1(svuint32_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 278     uint32_t slice = slice_base + 3;
 279     return SME_ACLE_FUNC(svread_hor_za32, _u32, _m)(zd, pg, 3, slice);
 280 }
 281
 282 // CHECK-C-LABEL: define dso_local <vscale x 2 x i64> @test_svread_hor_za64_u64(
 283 // CHECK-C-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 284 // CHECK-C-NEXT:  entry:
 285 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
 286 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.read.horiz.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 287 // CHECK-C-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 288 //
 289 // CHECK-CXX-LABEL: define dso_local <vscale x 2 x i64> @_Z24test_svread_hor_za64_u64u12__SVUint64_tu10__SVBool_tj(
 290 // CHECK-CXX-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 291 // CHECK-CXX-NEXT:  entry:
 292 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
 293 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.read.horiz.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 294 // CHECK-CXX-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 295 //
 296 svuint64_t test_svread_hor_za64_u64(svuint64_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 297     return SME_ACLE_FUNC(svread_hor_za64, _u64, _m)(zd, pg, 0, slice_base);
 298 }
 299
 300 // CHECK-C-LABEL: define dso_local <vscale x 2 x i64> @test_svread_hor_za64_u64_1(
 301 // CHECK-C-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 302 // CHECK-C-NEXT:  entry:
 303 // CHECK-C-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 1
 304 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
 305 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.read.horiz.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 7, i32 [[ADD]])
 306 // CHECK-C-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 307 //
 308 // CHECK-CXX-LABEL: define dso_local <vscale x 2 x i64> @_Z26test_svread_hor_za64_u64_1u12__SVUint64_tu10__SVBool_tj(
 309 // CHECK-CXX-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 310 // CHECK-CXX-NEXT:  entry:
 311 // CHECK-CXX-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 1
 312 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
 313 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.read.horiz.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 7, i32 [[ADD]])
 314 // CHECK-CXX-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 315 //
 316 svuint64_t test_svread_hor_za64_u64_1(svuint64_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 317     uint32_t slice = slice_base + 1;
 318     return SME_ACLE_FUNC(svread_hor_za64, _u64, _m)(zd, pg, 7, slice);
 319 }
 320
 321 // CHECK-C-LABEL: define dso_local <vscale x 8 x half> @test_svread_hor_za16_f16(
 322 // CHECK-C-SAME: <vscale x 8 x half> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 323 // CHECK-C-NEXT:  entry:
 324 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 325 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sme.read.horiz.nxv8f16(<vscale x 8 x half> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 326 // CHECK-C-NEXT:    ret <vscale x 8 x half> [[TMP1]]
 327 //
 328 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x half> @_Z24test_svread_hor_za16_f16u13__SVFloat16_tu10__SVBool_tj(
 329 // CHECK-CXX-SAME: <vscale x 8 x half> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 330 // CHECK-CXX-NEXT:  entry:
 331 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 332 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sme.read.horiz.nxv8f16(<vscale x 8 x half> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 333 // CHECK-CXX-NEXT:    ret <vscale x 8 x half> [[TMP1]]
 334 //
 335 svfloat16_t test_svread_hor_za16_f16(svfloat16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 336     return SME_ACLE_FUNC(svread_hor_za16, _f16, _m)(zd, pg, 0, slice_base);
 337 }
 338
 339 // CHECK-C-LABEL: define dso_local <vscale x 8 x half> @test_svread_hor_za16_f16_1(
 340 // CHECK-C-SAME: <vscale x 8 x half> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 341 // CHECK-C-NEXT:  entry:
 342 // CHECK-C-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 7
 343 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 344 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sme.read.horiz.nxv8f16(<vscale x 8 x half> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 1, i32 [[ADD]])
 345 // CHECK-C-NEXT:    ret <vscale x 8 x half> [[TMP1]]
 346 //
 347 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x half> @_Z26test_svread_hor_za16_f16_1u13__SVFloat16_tu10__SVBool_tj(
 348 // CHECK-CXX-SAME: <vscale x 8 x half> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 349 // CHECK-CXX-NEXT:  entry:
 350 // CHECK-CXX-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 7
 351 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 352 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sme.read.horiz.nxv8f16(<vscale x 8 x half> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 1, i32 [[ADD]])
 353 // CHECK-CXX-NEXT:    ret <vscale x 8 x half> [[TMP1]]
 354 //
 355 svfloat16_t test_svread_hor_za16_f16_1(svfloat16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 356     uint32_t slice = slice_base + 7;
 357     return SME_ACLE_FUNC(svread_hor_za16, _f16, _m)(zd, pg, 1, slice);
 358 }
 359
 360 // CHECK-C-LABEL: define dso_local <vscale x 8 x bfloat> @test_svread_hor_za16_bf16(
 361 // CHECK-C-SAME: <vscale x 8 x bfloat> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 362 // CHECK-C-NEXT:  entry:
 363 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 364 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sme.read.horiz.nxv8bf16(<vscale x 8 x bfloat> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 365 // CHECK-C-NEXT:    ret <vscale x 8 x bfloat> [[TMP1]]
 366 //
 367 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x bfloat> @_Z25test_svread_hor_za16_bf16u14__SVBfloat16_tu10__SVBool_tj(
 368 // CHECK-CXX-SAME: <vscale x 8 x bfloat> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 369 // CHECK-CXX-NEXT:  entry:
 370 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 371 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sme.read.horiz.nxv8bf16(<vscale x 8 x bfloat> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 372 // CHECK-CXX-NEXT:    ret <vscale x 8 x bfloat> [[TMP1]]
 373 //
 374 svbfloat16_t test_svread_hor_za16_bf16(svbfloat16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 375     return SME_ACLE_FUNC(svread_hor_za16, _bf16, _m)(zd, pg, 0, slice_base);
 376 }
 377
 378 // CHECK-C-LABEL: define dso_local <vscale x 8 x bfloat> @test_svread_hor_za16_bf16_1(
 379 // CHECK-C-SAME: <vscale x 8 x bfloat> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 380 // CHECK-C-NEXT:  entry:
 381 // CHECK-C-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 7
 382 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 383 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sme.read.horiz.nxv8bf16(<vscale x 8 x bfloat> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 1, i32 [[ADD]])
 384 // CHECK-C-NEXT:    ret <vscale x 8 x bfloat> [[TMP1]]
 385 //
 386 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x bfloat> @_Z27test_svread_hor_za16_bf16_1u14__SVBfloat16_tu10__SVBool_tj(
 387 // CHECK-CXX-SAME: <vscale x 8 x bfloat> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 388 // CHECK-CXX-NEXT:  entry:
 389 // CHECK-CXX-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 7
 390 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 391 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sme.read.horiz.nxv8bf16(<vscale x 8 x bfloat> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 1, i32 [[ADD]])
 392 // CHECK-CXX-NEXT:    ret <vscale x 8 x bfloat> [[TMP1]]
 393 //
 394 svbfloat16_t test_svread_hor_za16_bf16_1(svbfloat16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 395     uint32_t slice = slice_base + 7;
 396     return SME_ACLE_FUNC(svread_hor_za16, _bf16, _m)(zd, pg, 1, slice);
 397 }
 398
 399 // CHECK-C-LABEL: define dso_local <vscale x 4 x float> @test_svread_hor_za32_f32(
 400 // CHECK-C-SAME: <vscale x 4 x float> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 401 // CHECK-C-NEXT:  entry:
 402 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 403 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sme.read.horiz.nxv4f32(<vscale x 4 x float> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 404 // CHECK-C-NEXT:    ret <vscale x 4 x float> [[TMP1]]
 405 //
 406 // CHECK-CXX-LABEL: define dso_local <vscale x 4 x float> @_Z24test_svread_hor_za32_f32u13__SVFloat32_tu10__SVBool_tj(
 407 // CHECK-CXX-SAME: <vscale x 4 x float> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 408 // CHECK-CXX-NEXT:  entry:
 409 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 410 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sme.read.horiz.nxv4f32(<vscale x 4 x float> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 411 // CHECK-CXX-NEXT:    ret <vscale x 4 x float> [[TMP1]]
 412 //
 413 svfloat32_t test_svread_hor_za32_f32(svfloat32_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 414     return SME_ACLE_FUNC(svread_hor_za32, _f32, _m)(zd, pg, 0, slice_base);
 415 }
 416
 417 // CHECK-C-LABEL: define dso_local <vscale x 4 x float> @test_svread_hor_za32_f32_1(
 418 // CHECK-C-SAME: <vscale x 4 x float> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 419 // CHECK-C-NEXT:  entry:
 420 // CHECK-C-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 3
 421 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 422 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sme.read.horiz.nxv4f32(<vscale x 4 x float> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 3, i32 [[ADD]])
 423 // CHECK-C-NEXT:    ret <vscale x 4 x float> [[TMP1]]
 424 //
 425 // CHECK-CXX-LABEL: define dso_local <vscale x 4 x float> @_Z26test_svread_hor_za32_f32_1u13__SVFloat32_tu10__SVBool_tj(
 426 // CHECK-CXX-SAME: <vscale x 4 x float> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 427 // CHECK-CXX-NEXT:  entry:
 428 // CHECK-CXX-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 3
 429 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 430 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sme.read.horiz.nxv4f32(<vscale x 4 x float> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 3, i32 [[ADD]])
 431 // CHECK-CXX-NEXT:    ret <vscale x 4 x float> [[TMP1]]
 432 //
 433 svfloat32_t test_svread_hor_za32_f32_1(svfloat32_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 434     uint32_t slice = slice_base + 3;
 435     return SME_ACLE_FUNC(svread_hor_za32, _f32, _m)(zd, pg, 3, slice);
 436 }
 437
 438 // CHECK-C-LABEL: define dso_local <vscale x 2 x double> @test_svread_hor_za64_f64(
 439 // CHECK-C-SAME: <vscale x 2 x double> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 440 // CHECK-C-NEXT:  entry:
 441 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
 442 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sme.read.horiz.nxv2f64(<vscale x 2 x double> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 443 // CHECK-C-NEXT:    ret <vscale x 2 x double> [[TMP1]]
 444 //
 445 // CHECK-CXX-LABEL: define dso_local <vscale x 2 x double> @_Z24test_svread_hor_za64_f64u13__SVFloat64_tu10__SVBool_tj(
 446 // CHECK-CXX-SAME: <vscale x 2 x double> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 447 // CHECK-CXX-NEXT:  entry:
 448 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
 449 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sme.read.horiz.nxv2f64(<vscale x 2 x double> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 450 // CHECK-CXX-NEXT:    ret <vscale x 2 x double> [[TMP1]]
 451 //
 452 svfloat64_t test_svread_hor_za64_f64(svfloat64_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 453     return SME_ACLE_FUNC(svread_hor_za64, _f64, _m)(zd, pg, 0, slice_base);
 454 }
 455
 456 // CHECK-C-LABEL: define dso_local <vscale x 2 x double> @test_svread_hor_za64_f64_1(
 457 // CHECK-C-SAME: <vscale x 2 x double> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 458 // CHECK-C-NEXT:  entry:
 459 // CHECK-C-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 1
 460 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
 461 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sme.read.horiz.nxv2f64(<vscale x 2 x double> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 7, i32 [[ADD]])
 462 // CHECK-C-NEXT:    ret <vscale x 2 x double> [[TMP1]]
 463 //
 464 // CHECK-CXX-LABEL: define dso_local <vscale x 2 x double> @_Z26test_svread_hor_za64_f64_1u13__SVFloat64_tu10__SVBool_tj(
 465 // CHECK-CXX-SAME: <vscale x 2 x double> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 466 // CHECK-CXX-NEXT:  entry:
 467 // CHECK-CXX-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 1
 468 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
 469 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sme.read.horiz.nxv2f64(<vscale x 2 x double> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 7, i32 [[ADD]])
 470 // CHECK-CXX-NEXT:    ret <vscale x 2 x double> [[TMP1]]
 471 //
 472 svfloat64_t test_svread_hor_za64_f64_1(svfloat64_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 473     uint32_t slice = slice_base + 1;
 474     return SME_ACLE_FUNC(svread_hor_za64, _f64, _m)(zd, pg, 7, slice);
 475 }
 476
 477 // CHECK-C-LABEL: define dso_local <vscale x 16 x i8> @test_svread_hor_za128_s8(
 478 // CHECK-C-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 479 // CHECK-C-NEXT:  entry:
 480 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.readq.horiz.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 0, i32 [[SLICE_BASE]])
 481 // CHECK-C-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 482 //
 483 // CHECK-CXX-LABEL: define dso_local <vscale x 16 x i8> @_Z24test_svread_hor_za128_s8u10__SVInt8_tu10__SVBool_tj(
 484 // CHECK-CXX-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 485 // CHECK-CXX-NEXT:  entry:
 486 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.readq.horiz.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 0, i32 [[SLICE_BASE]])
 487 // CHECK-CXX-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 488 //
 489 svint8_t test_svread_hor_za128_s8(svint8_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 490     return SME_ACLE_FUNC(svread_hor_za128, _s8, _m)(zd, pg, 0, slice_base);
 491 }
 492
 493 // CHECK-C-LABEL: define dso_local <vscale x 16 x i8> @test_svread_hor_za128_s8_1(
 494 // CHECK-C-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 495 // CHECK-C-NEXT:  entry:
 496 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.readq.horiz.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 15, i32 [[SLICE_BASE]])
 497 // CHECK-C-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 498 //
 499 // CHECK-CXX-LABEL: define dso_local <vscale x 16 x i8> @_Z26test_svread_hor_za128_s8_1u10__SVInt8_tu10__SVBool_tj(
 500 // CHECK-CXX-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 501 // CHECK-CXX-NEXT:  entry:
 502 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.readq.horiz.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 15, i32 [[SLICE_BASE]])
 503 // CHECK-CXX-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 504 //
 505 svint8_t test_svread_hor_za128_s8_1(svint8_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 506     return SME_ACLE_FUNC(svread_hor_za128, _s8, _m)(zd, pg, 15, slice_base);
 507 }
 508
 509 // CHECK-C-LABEL: define dso_local <vscale x 8 x i16> @test_svread_hor_za128_s16(
 510 // CHECK-C-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 511 // CHECK-C-NEXT:  entry:
 512 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 513 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.readq.horiz.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 514 // CHECK-C-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 515 //
 516 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x i16> @_Z25test_svread_hor_za128_s16u11__SVInt16_tu10__SVBool_tj(
 517 // CHECK-CXX-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 518 // CHECK-CXX-NEXT:  entry:
 519 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 520 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.readq.horiz.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 521 // CHECK-CXX-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 522 //
 523 svint16_t test_svread_hor_za128_s16(svint16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 524     return SME_ACLE_FUNC(svread_hor_za128, _s16, _m)(zd, pg, 0, slice_base);
 525 }
 526
 527 // CHECK-C-LABEL: define dso_local <vscale x 8 x i16> @test_svread_hor_za128_s16_1(
 528 // CHECK-C-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 529 // CHECK-C-NEXT:  entry:
 530 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 531 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.readq.horiz.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
 532 // CHECK-C-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 533 //
 534 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x i16> @_Z27test_svread_hor_za128_s16_1u11__SVInt16_tu10__SVBool_tj(
 535 // CHECK-CXX-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 536 // CHECK-CXX-NEXT:  entry:
 537 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 538 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.readq.horiz.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
 539 // CHECK-CXX-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 540 //
 541 svint16_t test_svread_hor_za128_s16_1(svint16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 542     return SME_ACLE_FUNC(svread_hor_za128, _s16, _m)(zd, pg, 15, slice_base);
 543 }
 544
 545 // CHECK-C-LABEL: define dso_local <vscale x 4 x i32> @test_svread_hor_za128_s32(
 546 // CHECK-C-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 547 // CHECK-C-NEXT:  entry:
 548 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 549 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.readq.horiz.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 550 // CHECK-C-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 551 //
 552 // CHECK-CXX-LABEL: define dso_local <vscale x 4 x i32> @_Z25test_svread_hor_za128_s32u11__SVInt32_tu10__SVBool_tj(
 553 // CHECK-CXX-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 554 // CHECK-CXX-NEXT:  entry:
 555 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 556 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.readq.horiz.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 557 // CHECK-CXX-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 558 //
 559 svint32_t test_svread_hor_za128_s32(svint32_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 560     return SME_ACLE_FUNC(svread_hor_za128, _s32, _m)(zd, pg, 0, slice_base);
 561 }
 562
 563 // CHECK-C-LABEL: define dso_local <vscale x 4 x i32> @test_svread_hor_za128_s32_1(
 564 // CHECK-C-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 565 // CHECK-C-NEXT:  entry:
 566 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 567 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.readq.horiz.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
 568 // CHECK-C-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 569 //
 570 // CHECK-CXX-LABEL: define dso_local <vscale x 4 x i32> @_Z27test_svread_hor_za128_s32_1u11__SVInt32_tu10__SVBool_tj(
 571 // CHECK-CXX-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 572 // CHECK-CXX-NEXT:  entry:
 573 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 574 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.readq.horiz.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
 575 // CHECK-CXX-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 576 //
 577 svint32_t test_svread_hor_za128_s32_1(svint32_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 578     return SME_ACLE_FUNC(svread_hor_za128, _s32, _m)(zd, pg, 15, slice_base);
 579 }
 580
 581 // CHECK-C-LABEL: define dso_local <vscale x 2 x i64> @test_svread_hor_za128_s64(
 582 // CHECK-C-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 583 // CHECK-C-NEXT:  entry:
 584 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
 585 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.readq.horiz.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 586 // CHECK-C-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 587 //
 588 // CHECK-CXX-LABEL: define dso_local <vscale x 2 x i64> @_Z25test_svread_hor_za128_s64u11__SVInt64_tu10__SVBool_tj(
 589 // CHECK-CXX-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 590 // CHECK-CXX-NEXT:  entry:
 591 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
 592 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.readq.horiz.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 593 // CHECK-CXX-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 594 //
 595 svint64_t test_svread_hor_za128_s64(svint64_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 596     return SME_ACLE_FUNC(svread_hor_za128, _s64, _m)(zd, pg, 0, slice_base);
 597 }
 598
 599 // CHECK-C-LABEL: define dso_local <vscale x 2 x i64> @test_svread_hor_za128_s64_1(
 600 // CHECK-C-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 601 // CHECK-C-NEXT:  entry:
 602 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
 603 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.readq.horiz.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
 604 // CHECK-C-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 605 //
 606 // CHECK-CXX-LABEL: define dso_local <vscale x 2 x i64> @_Z27test_svread_hor_za128_s64_1u11__SVInt64_tu10__SVBool_tj(
 607 // CHECK-CXX-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 608 // CHECK-CXX-NEXT:  entry:
 609 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
 610 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.readq.horiz.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
 611 // CHECK-CXX-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 612 //
 613 svint64_t test_svread_hor_za128_s64_1(svint64_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 614     return SME_ACLE_FUNC(svread_hor_za128, _s64, _m)(zd, pg, 15, slice_base);
 615 }
 616
 617 // CHECK-C-LABEL: define dso_local <vscale x 16 x i8> @test_svread_hor_za128_u8(
 618 // CHECK-C-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 619 // CHECK-C-NEXT:  entry:
 620 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.readq.horiz.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 0, i32 [[SLICE_BASE]])
 621 // CHECK-C-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 622 //
 623 // CHECK-CXX-LABEL: define dso_local <vscale x 16 x i8> @_Z24test_svread_hor_za128_u8u11__SVUint8_tu10__SVBool_tj(
 624 // CHECK-CXX-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 625 // CHECK-CXX-NEXT:  entry:
 626 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.readq.horiz.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 0, i32 [[SLICE_BASE]])
 627 // CHECK-CXX-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 628 //
 629 svuint8_t test_svread_hor_za128_u8(svuint8_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 630     return SME_ACLE_FUNC(svread_hor_za128, _u8, _m)(zd, pg, 0, slice_base);
 631 }
 632
 633 // CHECK-C-LABEL: define dso_local <vscale x 16 x i8> @test_svread_hor_za128_u8_1(
 634 // CHECK-C-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 635 // CHECK-C-NEXT:  entry:
 636 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.readq.horiz.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 15, i32 [[SLICE_BASE]])
 637 // CHECK-C-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 638 //
 639 // CHECK-CXX-LABEL: define dso_local <vscale x 16 x i8> @_Z26test_svread_hor_za128_u8_1u11__SVUint8_tu10__SVBool_tj(
 640 // CHECK-CXX-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 641 // CHECK-CXX-NEXT:  entry:
 642 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.readq.horiz.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 15, i32 [[SLICE_BASE]])
 643 // CHECK-CXX-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 644 //
 645 svuint8_t test_svread_hor_za128_u8_1(svuint8_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 646     return SME_ACLE_FUNC(svread_hor_za128, _u8, _m)(zd, pg, 15, slice_base);
 647 }
 648
 649 // CHECK-C-LABEL: define dso_local <vscale x 8 x i16> @test_svread_hor_za128_u16(
 650 // CHECK-C-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 651 // CHECK-C-NEXT:  entry:
 652 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 653 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.readq.horiz.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 654 // CHECK-C-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 655 //
 656 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x i16> @_Z25test_svread_hor_za128_u16u12__SVUint16_tu10__SVBool_tj(
 657 // CHECK-CXX-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 658 // CHECK-CXX-NEXT:  entry:
 659 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 660 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.readq.horiz.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 661 // CHECK-CXX-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 662 //
 663 svuint16_t test_svread_hor_za128_u16(svuint16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 664     return SME_ACLE_FUNC(svread_hor_za128, _u16, _m)(zd, pg, 0, slice_base);
 665 }
 666
 667 // CHECK-C-LABEL: define dso_local <vscale x 8 x i16> @test_svread_hor_za128_u16_1(
 668 // CHECK-C-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 669 // CHECK-C-NEXT:  entry:
 670 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 671 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.readq.horiz.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
 672 // CHECK-C-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 673 //
 674 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x i16> @_Z27test_svread_hor_za128_u16_1u12__SVUint16_tu10__SVBool_tj(
 675 // CHECK-CXX-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 676 // CHECK-CXX-NEXT:  entry:
 677 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 678 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.readq.horiz.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
 679 // CHECK-CXX-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 680 //
 681 svuint16_t test_svread_hor_za128_u16_1(svuint16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 682     return SME_ACLE_FUNC(svread_hor_za128, _u16, _m)(zd, pg, 15, slice_base);
 683 }
 684
 685 // CHECK-C-LABEL: define dso_local <vscale x 4 x i32> @test_svread_hor_za128_u32(
 686 // CHECK-C-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 687 // CHECK-C-NEXT:  entry:
 688 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 689 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.readq.horiz.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 690 // CHECK-C-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 691 //
 692 // CHECK-CXX-LABEL: define dso_local <vscale x 4 x i32> @_Z25test_svread_hor_za128_u32u12__SVUint32_tu10__SVBool_tj(
 693 // CHECK-CXX-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 694 // CHECK-CXX-NEXT:  entry:
 695 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 696 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.readq.horiz.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 697 // CHECK-CXX-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 698 //
 699 svuint32_t test_svread_hor_za128_u32(svuint32_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 700     return SME_ACLE_FUNC(svread_hor_za128, _u32, _m)(zd, pg, 0, slice_base);
 701 }
 702
 703 // CHECK-C-LABEL: define dso_local <vscale x 4 x i32> @test_svread_hor_za128_u32_1(
 704 // CHECK-C-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 705 // CHECK-C-NEXT:  entry:
 706 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 707 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.readq.horiz.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
 708 // CHECK-C-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 709 //
 710 // CHECK-CXX-LABEL: define dso_local <vscale x 4 x i32> @_Z27test_svread_hor_za128_u32_1u12__SVUint32_tu10__SVBool_tj(
 711 // CHECK-CXX-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 712 // CHECK-CXX-NEXT:  entry:
 713 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 714 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.readq.horiz.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
 715 // CHECK-CXX-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 716 //
 717 svuint32_t test_svread_hor_za128_u32_1(svuint32_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 718     return SME_ACLE_FUNC(svread_hor_za128, _u32, _m)(zd, pg, 15, slice_base);
 719 }
 720
 721 // CHECK-C-LABEL: define dso_local <vscale x 2 x i64> @test_svread_hor_za128_u64(
 722 // CHECK-C-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 723 // CHECK-C-NEXT:  entry:
 724 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
 725 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.readq.horiz.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 726 // CHECK-C-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 727 //
 728 // CHECK-CXX-LABEL: define dso_local <vscale x 2 x i64> @_Z25test_svread_hor_za128_u64u12__SVUint64_tu10__SVBool_tj(
 729 // CHECK-CXX-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 730 // CHECK-CXX-NEXT:  entry:
 731 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
 732 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.readq.horiz.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 733 // CHECK-CXX-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 734 //
 735 svuint64_t test_svread_hor_za128_u64(svuint64_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 736     return SME_ACLE_FUNC(svread_hor_za128, _u64, _m)(zd, pg, 0, slice_base);
 737 }
 738
 739 // CHECK-C-LABEL: define dso_local <vscale x 2 x i64> @test_svread_hor_za128_u64_1(
 740 // CHECK-C-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 741 // CHECK-C-NEXT:  entry:
 742 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
 743 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.readq.horiz.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
 744 // CHECK-C-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 745 //
 746 // CHECK-CXX-LABEL: define dso_local <vscale x 2 x i64> @_Z27test_svread_hor_za128_u64_1u12__SVUint64_tu10__SVBool_tj(
 747 // CHECK-CXX-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 748 // CHECK-CXX-NEXT:  entry:
 749 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
 750 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.readq.horiz.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
 751 // CHECK-CXX-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 752 //
 753 svuint64_t test_svread_hor_za128_u64_1(svuint64_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 754     return SME_ACLE_FUNC(svread_hor_za128, _u64, _m)(zd, pg, 15, slice_base);
 755 }
 756
 757 // CHECK-C-LABEL: define dso_local <vscale x 8 x half> @test_svread_hor_za128_f16(
 758 // CHECK-C-SAME: <vscale x 8 x half> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 759 // CHECK-C-NEXT:  entry:
 760 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 761 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sme.readq.horiz.nxv8f16(<vscale x 8 x half> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 762 // CHECK-C-NEXT:    ret <vscale x 8 x half> [[TMP1]]
 763 //
 764 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x half> @_Z25test_svread_hor_za128_f16u13__SVFloat16_tu10__SVBool_tj(
 765 // CHECK-CXX-SAME: <vscale x 8 x half> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 766 // CHECK-CXX-NEXT:  entry:
 767 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 768 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sme.readq.horiz.nxv8f16(<vscale x 8 x half> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 769 // CHECK-CXX-NEXT:    ret <vscale x 8 x half> [[TMP1]]
 770 //
 771 svfloat16_t test_svread_hor_za128_f16(svfloat16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 772     return SME_ACLE_FUNC(svread_hor_za128, _f16, _m)(zd, pg, 0, slice_base);
 773 }
 774
 775 // CHECK-C-LABEL: define dso_local <vscale x 8 x half> @test_svread_hor_za128_f16_1(
 776 // CHECK-C-SAME: <vscale x 8 x half> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 777 // CHECK-C-NEXT:  entry:
 778 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 779 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sme.readq.horiz.nxv8f16(<vscale x 8 x half> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
 780 // CHECK-C-NEXT:    ret <vscale x 8 x half> [[TMP1]]
 781 //
 782 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x half> @_Z27test_svread_hor_za128_f16_1u13__SVFloat16_tu10__SVBool_tj(
 783 // CHECK-CXX-SAME: <vscale x 8 x half> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 784 // CHECK-CXX-NEXT:  entry:
 785 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 786 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sme.readq.horiz.nxv8f16(<vscale x 8 x half> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
 787 // CHECK-CXX-NEXT:    ret <vscale x 8 x half> [[TMP1]]
 788 //
 789 svfloat16_t test_svread_hor_za128_f16_1(svfloat16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 790     return SME_ACLE_FUNC(svread_hor_za128, _f16, _m)(zd, pg, 15, slice_base);
 791 }
 792
 793 // CHECK-C-LABEL: define dso_local <vscale x 8 x bfloat> @test_svread_hor_za128_bf16(
 794 // CHECK-C-SAME: <vscale x 8 x bfloat> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 795 // CHECK-C-NEXT:  entry:
 796 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 797 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sme.readq.horiz.nxv8bf16(<vscale x 8 x bfloat> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 798 // CHECK-C-NEXT:    ret <vscale x 8 x bfloat> [[TMP1]]
 799 //
 800 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x bfloat> @_Z26test_svread_hor_za128_bf16u14__SVBfloat16_tu10__SVBool_tj(
 801 // CHECK-CXX-SAME: <vscale x 8 x bfloat> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 802 // CHECK-CXX-NEXT:  entry:
 803 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 804 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sme.readq.horiz.nxv8bf16(<vscale x 8 x bfloat> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 805 // CHECK-CXX-NEXT:    ret <vscale x 8 x bfloat> [[TMP1]]
 806 //
 807 svbfloat16_t test_svread_hor_za128_bf16(svbfloat16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 808     return SME_ACLE_FUNC(svread_hor_za128, _bf16, _m)(zd, pg, 0, slice_base);
 809 }
 810
 811 // CHECK-C-LABEL: define dso_local <vscale x 8 x bfloat> @test_svread_hor_za128_bf16_1(
 812 // CHECK-C-SAME: <vscale x 8 x bfloat> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 813 // CHECK-C-NEXT:  entry:
 814 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 815 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sme.readq.horiz.nxv8bf16(<vscale x 8 x bfloat> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
 816 // CHECK-C-NEXT:    ret <vscale x 8 x bfloat> [[TMP1]]
 817 //
 818 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x bfloat> @_Z28test_svread_hor_za128_bf16_1u14__SVBfloat16_tu10__SVBool_tj(
 819 // CHECK-CXX-SAME: <vscale x 8 x bfloat> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 820 // CHECK-CXX-NEXT:  entry:
 821 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 822 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sme.readq.horiz.nxv8bf16(<vscale x 8 x bfloat> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
 823 // CHECK-CXX-NEXT:    ret <vscale x 8 x bfloat> [[TMP1]]
 824 //
 825 svbfloat16_t test_svread_hor_za128_bf16_1(svbfloat16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 826     return SME_ACLE_FUNC(svread_hor_za128, _bf16, _m)(zd, pg, 15, slice_base);
 827 }
 828
 829 // CHECK-C-LABEL: define dso_local <vscale x 4 x float> @test_svread_hor_za128_f32(
 830 // CHECK-C-SAME: <vscale x 4 x float> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 831 // CHECK-C-NEXT:  entry:
 832 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 833 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sme.readq.horiz.nxv4f32(<vscale x 4 x float> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 834 // CHECK-C-NEXT:    ret <vscale x 4 x float> [[TMP1]]
 835 //
 836 // CHECK-CXX-LABEL: define dso_local <vscale x 4 x float> @_Z25test_svread_hor_za128_f32u13__SVFloat32_tu10__SVBool_tj(
 837 // CHECK-CXX-SAME: <vscale x 4 x float> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 838 // CHECK-CXX-NEXT:  entry:
 839 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 840 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sme.readq.horiz.nxv4f32(<vscale x 4 x float> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 841 // CHECK-CXX-NEXT:    ret <vscale x 4 x float> [[TMP1]]
 842 //
 843 svfloat32_t test_svread_hor_za128_f32(svfloat32_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 844     return SME_ACLE_FUNC(svread_hor_za128, _f32, _m)(zd, pg, 0, slice_base);
 845 }
 846
 847 // CHECK-C-LABEL: define dso_local <vscale x 4 x float> @test_svread_hor_za128_f32_1(
 848 // CHECK-C-SAME: <vscale x 4 x float> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 849 // CHECK-C-NEXT:  entry:
 850 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 851 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sme.readq.horiz.nxv4f32(<vscale x 4 x float> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
 852 // CHECK-C-NEXT:    ret <vscale x 4 x float> [[TMP1]]
 853 //
 854 // CHECK-CXX-LABEL: define dso_local <vscale x 4 x float> @_Z27test_svread_hor_za128_f32_1u13__SVFloat32_tu10__SVBool_tj(
 855 // CHECK-CXX-SAME: <vscale x 4 x float> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 856 // CHECK-CXX-NEXT:  entry:
 857 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 858 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sme.readq.horiz.nxv4f32(<vscale x 4 x float> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
 859 // CHECK-CXX-NEXT:    ret <vscale x 4 x float> [[TMP1]]
 860 //
 861 svfloat32_t test_svread_hor_za128_f32_1(svfloat32_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 862     return SME_ACLE_FUNC(svread_hor_za128, _f32, _m)(zd, pg, 15, slice_base);
 863 }
 864
 865 // CHECK-C-LABEL: define dso_local <vscale x 2 x double> @test_svread_hor_za128_f64(
 866 // CHECK-C-SAME: <vscale x 2 x double> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 867 // CHECK-C-NEXT:  entry:
 868 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
 869 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sme.readq.horiz.nxv2f64(<vscale x 2 x double> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 870 // CHECK-C-NEXT:    ret <vscale x 2 x double> [[TMP1]]
 871 //
 872 // CHECK-CXX-LABEL: define dso_local <vscale x 2 x double> @_Z25test_svread_hor_za128_f64u13__SVFloat64_tu10__SVBool_tj(
 873 // CHECK-CXX-SAME: <vscale x 2 x double> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 874 // CHECK-CXX-NEXT:  entry:
 875 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
 876 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sme.readq.horiz.nxv2f64(<vscale x 2 x double> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 877 // CHECK-CXX-NEXT:    ret <vscale x 2 x double> [[TMP1]]
 878 //
 879 svfloat64_t test_svread_hor_za128_f64(svfloat64_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 880     return SME_ACLE_FUNC(svread_hor_za128, _f64, _m)(zd, pg, 0, slice_base);
 881 }
 882
 883 // CHECK-C-LABEL: define dso_local <vscale x 2 x double> @test_svread_hor_za128_f64_1(
 884 // CHECK-C-SAME: <vscale x 2 x double> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 885 // CHECK-C-NEXT:  entry:
 886 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
 887 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sme.readq.horiz.nxv2f64(<vscale x 2 x double> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
 888 // CHECK-C-NEXT:    ret <vscale x 2 x double> [[TMP1]]
 889 //
 890 // CHECK-CXX-LABEL: define dso_local <vscale x 2 x double> @_Z27test_svread_hor_za128_f64_1u13__SVFloat64_tu10__SVBool_tj(
 891 // CHECK-CXX-SAME: <vscale x 2 x double> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 892 // CHECK-CXX-NEXT:  entry:
 893 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
 894 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sme.readq.horiz.nxv2f64(<vscale x 2 x double> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
 895 // CHECK-CXX-NEXT:    ret <vscale x 2 x double> [[TMP1]]
 896 //
 897 svfloat64_t test_svread_hor_za128_f64_1(svfloat64_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 898     return SME_ACLE_FUNC(svread_hor_za128, _f64, _m)(zd, pg, 15, slice_base);
 899 }
 900
 901 // CHECK-C-LABEL: define dso_local <vscale x 16 x i8> @test_svread_ver_za8_s8(
 902 // CHECK-C-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 903 // CHECK-C-NEXT:  entry:
 904 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.read.vert.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 0, i32 [[SLICE_BASE]])
 905 // CHECK-C-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 906 //
 907 // CHECK-CXX-LABEL: define dso_local <vscale x 16 x i8> @_Z22test_svread_ver_za8_s8u10__SVInt8_tu10__SVBool_tj(
 908 // CHECK-CXX-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 909 // CHECK-CXX-NEXT:  entry:
 910 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.read.vert.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 0, i32 [[SLICE_BASE]])
 911 // CHECK-CXX-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 912 //
 913 svint8_t test_svread_ver_za8_s8(svint8_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 914     return SME_ACLE_FUNC(svread_ver_za8, _s8, _m)(zd, pg, 0, slice_base);
 915 }
 916
 917 // CHECK-C-LABEL: define dso_local <vscale x 16 x i8> @test_svread_ver_za8_s8_1(
 918 // CHECK-C-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 919 // CHECK-C-NEXT:  entry:
 920 // CHECK-C-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 15
 921 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.read.vert.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 0, i32 [[ADD]])
 922 // CHECK-C-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 923 //
 924 // CHECK-CXX-LABEL: define dso_local <vscale x 16 x i8> @_Z24test_svread_ver_za8_s8_1u10__SVInt8_tu10__SVBool_tj(
 925 // CHECK-CXX-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 926 // CHECK-CXX-NEXT:  entry:
 927 // CHECK-CXX-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 15
 928 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.read.vert.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 0, i32 [[ADD]])
 929 // CHECK-CXX-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 930 //
 931 svint8_t test_svread_ver_za8_s8_1(svint8_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 932     uint32_t slice = slice_base + 15;
 933     return SME_ACLE_FUNC(svread_ver_za8, _s8, _m)(zd, pg, 0, slice);
 934 }
 935
 936 // CHECK-C-LABEL: define dso_local <vscale x 8 x i16> @test_svread_ver_za16_s16(
 937 // CHECK-C-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 938 // CHECK-C-NEXT:  entry:
 939 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 940 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.read.vert.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 941 // CHECK-C-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 942 //
 943 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x i16> @_Z24test_svread_ver_za16_s16u11__SVInt16_tu10__SVBool_tj(
 944 // CHECK-CXX-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 945 // CHECK-CXX-NEXT:  entry:
 946 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 947 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.read.vert.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 948 // CHECK-CXX-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 949 //
 950 svint16_t test_svread_ver_za16_s16(svint16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 951      return SME_ACLE_FUNC(svread_ver_za16, _s16, _m)(zd, pg, 0, slice_base);
 952 }
 953
 954 // CHECK-C-LABEL: define dso_local <vscale x 8 x i16> @test_svread_ver_za16_s16_1(
 955 // CHECK-C-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 956 // CHECK-C-NEXT:  entry:
 957 // CHECK-C-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 7
 958 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 959 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.read.vert.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 1, i32 [[ADD]])
 960 // CHECK-C-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 961 //
 962 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x i16> @_Z26test_svread_ver_za16_s16_1u11__SVInt16_tu10__SVBool_tj(
 963 // CHECK-CXX-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 964 // CHECK-CXX-NEXT:  entry:
 965 // CHECK-CXX-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 7
 966 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
 967 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.read.vert.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 1, i32 [[ADD]])
 968 // CHECK-CXX-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 969 //
 970 svint16_t test_svread_ver_za16_s16_1(svint16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 971      uint32_t slice = slice_base + 7;
 972      return SME_ACLE_FUNC(svread_ver_za16, _s16, _m)(zd, pg, 1, slice);
 973 }
 974
 975 // CHECK-C-LABEL: define dso_local <vscale x 4 x i32> @test_svread_ver_za32_s32(
 976 // CHECK-C-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 977 // CHECK-C-NEXT:  entry:
 978 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 979 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.read.vert.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 980 // CHECK-C-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 981 //
 982 // CHECK-CXX-LABEL: define dso_local <vscale x 4 x i32> @_Z24test_svread_ver_za32_s32u11__SVInt32_tu10__SVBool_tj(
 983 // CHECK-CXX-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 984 // CHECK-CXX-NEXT:  entry:
 985 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 986 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.read.vert.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
 987 // CHECK-CXX-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 988 //
 989 svint32_t test_svread_ver_za32_s32(svint32_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
 990     return SME_ACLE_FUNC(svread_ver_za32, _s32, _m)(zd, pg, 0, slice_base);
 991 }
 992
 993 // CHECK-C-LABEL: define dso_local <vscale x 4 x i32> @test_svread_ver_za32_s32_1(
 994 // CHECK-C-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
 995 // CHECK-C-NEXT:  entry:
 996 // CHECK-C-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 3
 997 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
 998 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.read.vert.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 3, i32 [[ADD]])
 999 // CHECK-C-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
1000 //
1001 // CHECK-CXX-LABEL: define dso_local <vscale x 4 x i32> @_Z26test_svread_ver_za32_s32_1u11__SVInt32_tu10__SVBool_tj(
1002 // CHECK-CXX-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1003 // CHECK-CXX-NEXT:  entry:
1004 // CHECK-CXX-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 3
1005 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
1006 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.read.vert.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 3, i32 [[ADD]])
1007 // CHECK-CXX-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
1008 //
1009 svint32_t test_svread_ver_za32_s32_1(svint32_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1010     uint32_t slice = slice_base + 3;
1011     return SME_ACLE_FUNC(svread_ver_za32, _s32, _m)(zd, pg, 3, slice);
1012 }
1013
1014 // CHECK-C-LABEL: define dso_local <vscale x 2 x i64> @test_svread_ver_za64_s64(
1015 // CHECK-C-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1016 // CHECK-C-NEXT:  entry:
1017 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
1018 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.read.vert.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1019 // CHECK-C-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
1020 //
1021 // CHECK-CXX-LABEL: define dso_local <vscale x 2 x i64> @_Z24test_svread_ver_za64_s64u11__SVInt64_tu10__SVBool_tj(
1022 // CHECK-CXX-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1023 // CHECK-CXX-NEXT:  entry:
1024 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
1025 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.read.vert.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1026 // CHECK-CXX-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
1027 //
1028 svint64_t test_svread_ver_za64_s64(svint64_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1029     return SME_ACLE_FUNC(svread_ver_za64, _s64, _m)(zd, pg, 0, slice_base);
1030 }
1031
1032 // CHECK-C-LABEL: define dso_local <vscale x 2 x i64> @test_svread_ver_za64_s64_1(
1033 // CHECK-C-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1034 // CHECK-C-NEXT:  entry:
1035 // CHECK-C-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 1
1036 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
1037 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.read.vert.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 7, i32 [[ADD]])
1038 // CHECK-C-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
1039 //
1040 // CHECK-CXX-LABEL: define dso_local <vscale x 2 x i64> @_Z26test_svread_ver_za64_s64_1u11__SVInt64_tu10__SVBool_tj(
1041 // CHECK-CXX-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1042 // CHECK-CXX-NEXT:  entry:
1043 // CHECK-CXX-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 1
1044 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
1045 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.read.vert.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 7, i32 [[ADD]])
1046 // CHECK-CXX-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
1047 //
1048 svint64_t test_svread_ver_za64_s64_1(svint64_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1049     uint32_t slice = slice_base + 1;
1050     return SME_ACLE_FUNC(svread_ver_za64, _s64, _m)(zd, pg, 7, slice);
1051 }
1052
1053 // CHECK-C-LABEL: define dso_local <vscale x 16 x i8> @test_svread_ver_za8_u8(
1054 // CHECK-C-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1055 // CHECK-C-NEXT:  entry:
1056 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.read.vert.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 0, i32 [[SLICE_BASE]])
1057 // CHECK-C-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
1058 //
1059 // CHECK-CXX-LABEL: define dso_local <vscale x 16 x i8> @_Z22test_svread_ver_za8_u8u11__SVUint8_tu10__SVBool_tj(
1060 // CHECK-CXX-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1061 // CHECK-CXX-NEXT:  entry:
1062 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.read.vert.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 0, i32 [[SLICE_BASE]])
1063 // CHECK-CXX-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
1064 //
1065 svuint8_t test_svread_ver_za8_u8(svuint8_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1066     return SME_ACLE_FUNC(svread_ver_za8, _u8, _m)(zd, pg, 0, slice_base);
1067 }
1068
1069 // CHECK-C-LABEL: define dso_local <vscale x 16 x i8> @test_svread_ver_za8_u8_1(
1070 // CHECK-C-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1071 // CHECK-C-NEXT:  entry:
1072 // CHECK-C-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 15
1073 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.read.vert.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 0, i32 [[ADD]])
1074 // CHECK-C-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
1075 //
1076 // CHECK-CXX-LABEL: define dso_local <vscale x 16 x i8> @_Z24test_svread_ver_za8_u8_1u11__SVUint8_tu10__SVBool_tj(
1077 // CHECK-CXX-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1078 // CHECK-CXX-NEXT:  entry:
1079 // CHECK-CXX-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 15
1080 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.read.vert.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 0, i32 [[ADD]])
1081 // CHECK-CXX-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
1082 //
1083 svuint8_t test_svread_ver_za8_u8_1(svuint8_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1084     uint32_t slice = slice_base + 15;
1085     return SME_ACLE_FUNC(svread_ver_za8, _u8, _m)(zd, pg, 0, slice);
1086 }
1087
1088 // CHECK-C-LABEL: define dso_local <vscale x 8 x i16> @test_svread_ver_za16_u16(
1089 // CHECK-C-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1090 // CHECK-C-NEXT:  entry:
1091 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1092 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.read.vert.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1093 // CHECK-C-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
1094 //
1095 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x i16> @_Z24test_svread_ver_za16_u16u12__SVUint16_tu10__SVBool_tj(
1096 // CHECK-CXX-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1097 // CHECK-CXX-NEXT:  entry:
1098 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1099 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.read.vert.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1100 // CHECK-CXX-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
1101 //
1102 svuint16_t test_svread_ver_za16_u16(svuint16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1103     return SME_ACLE_FUNC(svread_ver_za16, _u16, _m)(zd, pg, 0, slice_base);
1104 }
1105
1106 // CHECK-C-LABEL: define dso_local <vscale x 8 x i16> @test_svread_ver_za16_u16_1(
1107 // CHECK-C-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1108 // CHECK-C-NEXT:  entry:
1109 // CHECK-C-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 7
1110 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1111 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.read.vert.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 1, i32 [[ADD]])
1112 // CHECK-C-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
1113 //
1114 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x i16> @_Z26test_svread_ver_za16_u16_1u12__SVUint16_tu10__SVBool_tj(
1115 // CHECK-CXX-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1116 // CHECK-CXX-NEXT:  entry:
1117 // CHECK-CXX-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 7
1118 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1119 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.read.vert.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 1, i32 [[ADD]])
1120 // CHECK-CXX-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
1121 //
1122 svuint16_t test_svread_ver_za16_u16_1(svuint16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1123     uint32_t slice = slice_base + 7;
1124     return SME_ACLE_FUNC(svread_ver_za16, _u16, _m)(zd, pg, 1, slice);
1125 }
1126
1127 // CHECK-C-LABEL: define dso_local <vscale x 4 x i32> @test_svread_ver_za32_u32(
1128 // CHECK-C-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1129 // CHECK-C-NEXT:  entry:
1130 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
1131 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.read.vert.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1132 // CHECK-C-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
1133 //
1134 // CHECK-CXX-LABEL: define dso_local <vscale x 4 x i32> @_Z24test_svread_ver_za32_u32u12__SVUint32_tu10__SVBool_tj(
1135 // CHECK-CXX-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1136 // CHECK-CXX-NEXT:  entry:
1137 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
1138 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.read.vert.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1139 // CHECK-CXX-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
1140 //
1141 svuint32_t test_svread_ver_za32_u32(svuint32_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1142     return SME_ACLE_FUNC(svread_ver_za32, _u32, _m)(zd, pg, 0, slice_base);
1143 }
1144
1145 // CHECK-C-LABEL: define dso_local <vscale x 4 x i32> @test_svread_ver_za32_u32_1(
1146 // CHECK-C-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1147 // CHECK-C-NEXT:  entry:
1148 // CHECK-C-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 3
1149 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
1150 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.read.vert.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 3, i32 [[ADD]])
1151 // CHECK-C-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
1152 //
1153 // CHECK-CXX-LABEL: define dso_local <vscale x 4 x i32> @_Z26test_svread_ver_za32_u32_1u12__SVUint32_tu10__SVBool_tj(
1154 // CHECK-CXX-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1155 // CHECK-CXX-NEXT:  entry:
1156 // CHECK-CXX-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 3
1157 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
1158 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.read.vert.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 3, i32 [[ADD]])
1159 // CHECK-CXX-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
1160 //
1161 svuint32_t test_svread_ver_za32_u32_1(svuint32_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1162     uint32_t slice = slice_base + 3;
1163     return SME_ACLE_FUNC(svread_ver_za32, _u32, _m)(zd, pg, 3, slice);
1164 }
1165
1166 // CHECK-C-LABEL: define dso_local <vscale x 2 x i64> @test_svread_ver_za64_u64(
1167 // CHECK-C-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1168 // CHECK-C-NEXT:  entry:
1169 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
1170 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.read.vert.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1171 // CHECK-C-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
1172 //
1173 // CHECK-CXX-LABEL: define dso_local <vscale x 2 x i64> @_Z24test_svread_ver_za64_u64u12__SVUint64_tu10__SVBool_tj(
1174 // CHECK-CXX-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1175 // CHECK-CXX-NEXT:  entry:
1176 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
1177 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.read.vert.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1178 // CHECK-CXX-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
1179 //
1180 svuint64_t test_svread_ver_za64_u64(svuint64_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1181     return SME_ACLE_FUNC(svread_ver_za64, _u64, _m)(zd, pg, 0, slice_base);
1182 }
1183
1184 // CHECK-C-LABEL: define dso_local <vscale x 2 x i64> @test_svread_ver_za64_u64_1(
1185 // CHECK-C-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1186 // CHECK-C-NEXT:  entry:
1187 // CHECK-C-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 1
1188 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
1189 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.read.vert.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 7, i32 [[ADD]])
1190 // CHECK-C-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
1191 //
1192 // CHECK-CXX-LABEL: define dso_local <vscale x 2 x i64> @_Z26test_svread_ver_za64_u64_1u12__SVUint64_tu10__SVBool_tj(
1193 // CHECK-CXX-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1194 // CHECK-CXX-NEXT:  entry:
1195 // CHECK-CXX-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 1
1196 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
1197 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.read.vert.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 7, i32 [[ADD]])
1198 // CHECK-CXX-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
1199 //
1200 svuint64_t test_svread_ver_za64_u64_1(svuint64_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1201     uint32_t slice = slice_base + 1;
1202     return SME_ACLE_FUNC(svread_ver_za64, _u64, _m)(zd, pg, 7, slice);
1203 }
1204
1205 // CHECK-C-LABEL: define dso_local <vscale x 8 x half> @test_svread_ver_za16_f16(
1206 // CHECK-C-SAME: <vscale x 8 x half> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1207 // CHECK-C-NEXT:  entry:
1208 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1209 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sme.read.vert.nxv8f16(<vscale x 8 x half> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1210 // CHECK-C-NEXT:    ret <vscale x 8 x half> [[TMP1]]
1211 //
1212 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x half> @_Z24test_svread_ver_za16_f16u13__SVFloat16_tu10__SVBool_tj(
1213 // CHECK-CXX-SAME: <vscale x 8 x half> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1214 // CHECK-CXX-NEXT:  entry:
1215 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1216 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sme.read.vert.nxv8f16(<vscale x 8 x half> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1217 // CHECK-CXX-NEXT:    ret <vscale x 8 x half> [[TMP1]]
1218 //
1219 svfloat16_t test_svread_ver_za16_f16(svfloat16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1220     return SME_ACLE_FUNC(svread_ver_za16, _f16, _m)(zd, pg, 0, slice_base);
1221 }
1222
1223 // CHECK-C-LABEL: define dso_local <vscale x 8 x half> @test_svread_ver_za16_f16_1(
1224 // CHECK-C-SAME: <vscale x 8 x half> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1225 // CHECK-C-NEXT:  entry:
1226 // CHECK-C-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 7
1227 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1228 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sme.read.vert.nxv8f16(<vscale x 8 x half> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 1, i32 [[ADD]])
1229 // CHECK-C-NEXT:    ret <vscale x 8 x half> [[TMP1]]
1230 //
1231 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x half> @_Z26test_svread_ver_za16_f16_1u13__SVFloat16_tu10__SVBool_tj(
1232 // CHECK-CXX-SAME: <vscale x 8 x half> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1233 // CHECK-CXX-NEXT:  entry:
1234 // CHECK-CXX-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 7
1235 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1236 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sme.read.vert.nxv8f16(<vscale x 8 x half> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 1, i32 [[ADD]])
1237 // CHECK-CXX-NEXT:    ret <vscale x 8 x half> [[TMP1]]
1238 //
1239 svfloat16_t test_svread_ver_za16_f16_1(svfloat16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1240     uint32_t slice = slice_base + 7;
1241     return SME_ACLE_FUNC(svread_ver_za16, _f16, _m)(zd, pg, 1, slice);
1242 }
1243
1244 // CHECK-C-LABEL: define dso_local <vscale x 8 x bfloat> @test_svread_ver_za16_bf16(
1245 // CHECK-C-SAME: <vscale x 8 x bfloat> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1246 // CHECK-C-NEXT:  entry:
1247 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1248 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sme.read.vert.nxv8bf16(<vscale x 8 x bfloat> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1249 // CHECK-C-NEXT:    ret <vscale x 8 x bfloat> [[TMP1]]
1250 //
1251 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x bfloat> @_Z25test_svread_ver_za16_bf16u14__SVBfloat16_tu10__SVBool_tj(
1252 // CHECK-CXX-SAME: <vscale x 8 x bfloat> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1253 // CHECK-CXX-NEXT:  entry:
1254 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1255 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sme.read.vert.nxv8bf16(<vscale x 8 x bfloat> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1256 // CHECK-CXX-NEXT:    ret <vscale x 8 x bfloat> [[TMP1]]
1257 //
1258 svbfloat16_t test_svread_ver_za16_bf16(svbfloat16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1259     return SME_ACLE_FUNC(svread_ver_za16, _bf16, _m)(zd, pg, 0, slice_base);
1260 }
1261
1262 // CHECK-C-LABEL: define dso_local <vscale x 8 x bfloat> @test_svread_ver_za16_bf16_1(
1263 // CHECK-C-SAME: <vscale x 8 x bfloat> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1264 // CHECK-C-NEXT:  entry:
1265 // CHECK-C-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 7
1266 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1267 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sme.read.vert.nxv8bf16(<vscale x 8 x bfloat> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 1, i32 [[ADD]])
1268 // CHECK-C-NEXT:    ret <vscale x 8 x bfloat> [[TMP1]]
1269 //
1270 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x bfloat> @_Z27test_svread_ver_za16_bf16_1u14__SVBfloat16_tu10__SVBool_tj(
1271 // CHECK-CXX-SAME: <vscale x 8 x bfloat> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1272 // CHECK-CXX-NEXT:  entry:
1273 // CHECK-CXX-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 7
1274 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1275 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sme.read.vert.nxv8bf16(<vscale x 8 x bfloat> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 1, i32 [[ADD]])
1276 // CHECK-CXX-NEXT:    ret <vscale x 8 x bfloat> [[TMP1]]
1277 //
1278 svbfloat16_t test_svread_ver_za16_bf16_1(svbfloat16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1279     uint32_t slice = slice_base + 7;
1280     return SME_ACLE_FUNC(svread_ver_za16, _bf16, _m)(zd, pg, 1, slice);
1281 }
1282
1283 // CHECK-C-LABEL: define dso_local <vscale x 4 x float> @test_svread_ver_za32_f32(
1284 // CHECK-C-SAME: <vscale x 4 x float> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1285 // CHECK-C-NEXT:  entry:
1286 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
1287 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sme.read.vert.nxv4f32(<vscale x 4 x float> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1288 // CHECK-C-NEXT:    ret <vscale x 4 x float> [[TMP1]]
1289 //
1290 // CHECK-CXX-LABEL: define dso_local <vscale x 4 x float> @_Z24test_svread_ver_za32_f32u13__SVFloat32_tu10__SVBool_tj(
1291 // CHECK-CXX-SAME: <vscale x 4 x float> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1292 // CHECK-CXX-NEXT:  entry:
1293 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
1294 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sme.read.vert.nxv4f32(<vscale x 4 x float> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1295 // CHECK-CXX-NEXT:    ret <vscale x 4 x float> [[TMP1]]
1296 //
1297 svfloat32_t test_svread_ver_za32_f32(svfloat32_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1298     return SME_ACLE_FUNC(svread_ver_za32, _f32, _m)(zd, pg, 0, slice_base);
1299 }
1300
1301 // CHECK-C-LABEL: define dso_local <vscale x 4 x float> @test_svread_ver_za32_f32_1(
1302 // CHECK-C-SAME: <vscale x 4 x float> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1303 // CHECK-C-NEXT:  entry:
1304 // CHECK-C-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 3
1305 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
1306 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sme.read.vert.nxv4f32(<vscale x 4 x float> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 3, i32 [[ADD]])
1307 // CHECK-C-NEXT:    ret <vscale x 4 x float> [[TMP1]]
1308 //
1309 // CHECK-CXX-LABEL: define dso_local <vscale x 4 x float> @_Z26test_svread_ver_za32_f32_1u13__SVFloat32_tu10__SVBool_tj(
1310 // CHECK-CXX-SAME: <vscale x 4 x float> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1311 // CHECK-CXX-NEXT:  entry:
1312 // CHECK-CXX-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 3
1313 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
1314 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sme.read.vert.nxv4f32(<vscale x 4 x float> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 3, i32 [[ADD]])
1315 // CHECK-CXX-NEXT:    ret <vscale x 4 x float> [[TMP1]]
1316 //
1317 svfloat32_t test_svread_ver_za32_f32_1(svfloat32_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1318     uint32_t slice = slice_base + 3;
1319     return SME_ACLE_FUNC(svread_ver_za32, _f32, _m)(zd, pg, 3, slice);
1320 }
1321
1322 // CHECK-C-LABEL: define dso_local <vscale x 2 x double> @test_svread_ver_za64_f64(
1323 // CHECK-C-SAME: <vscale x 2 x double> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1324 // CHECK-C-NEXT:  entry:
1325 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
1326 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sme.read.vert.nxv2f64(<vscale x 2 x double> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1327 // CHECK-C-NEXT:    ret <vscale x 2 x double> [[TMP1]]
1328 //
1329 // CHECK-CXX-LABEL: define dso_local <vscale x 2 x double> @_Z24test_svread_ver_za64_f64u13__SVFloat64_tu10__SVBool_tj(
1330 // CHECK-CXX-SAME: <vscale x 2 x double> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1331 // CHECK-CXX-NEXT:  entry:
1332 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
1333 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sme.read.vert.nxv2f64(<vscale x 2 x double> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1334 // CHECK-CXX-NEXT:    ret <vscale x 2 x double> [[TMP1]]
1335 //
1336 svfloat64_t test_svread_ver_za64_f64(svfloat64_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1337     return SME_ACLE_FUNC(svread_ver_za64, _f64, _m)(zd, pg, 0, slice_base);
1338 }
1339
1340 // CHECK-C-LABEL: define dso_local <vscale x 2 x double> @test_svread_ver_za64_f64_1(
1341 // CHECK-C-SAME: <vscale x 2 x double> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1342 // CHECK-C-NEXT:  entry:
1343 // CHECK-C-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 1
1344 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
1345 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sme.read.vert.nxv2f64(<vscale x 2 x double> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 7, i32 [[ADD]])
1346 // CHECK-C-NEXT:    ret <vscale x 2 x double> [[TMP1]]
1347 //
1348 // CHECK-CXX-LABEL: define dso_local <vscale x 2 x double> @_Z26test_svread_ver_za64_f64_1u13__SVFloat64_tu10__SVBool_tj(
1349 // CHECK-CXX-SAME: <vscale x 2 x double> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1350 // CHECK-CXX-NEXT:  entry:
1351 // CHECK-CXX-NEXT:    [[ADD:%.*]] = add i32 [[SLICE_BASE]], 1
1352 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
1353 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sme.read.vert.nxv2f64(<vscale x 2 x double> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 7, i32 [[ADD]])
1354 // CHECK-CXX-NEXT:    ret <vscale x 2 x double> [[TMP1]]
1355 //
1356 svfloat64_t test_svread_ver_za64_f64_1(svfloat64_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1357     uint32_t slice = slice_base + 1;
1358     return SME_ACLE_FUNC(svread_ver_za64, _f64, _m)(zd, pg, 7, slice);
1359 }
1360
1361 // CHECK-C-LABEL: define dso_local <vscale x 16 x i8> @test_svread_ver_za128_s8(
1362 // CHECK-C-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1363 // CHECK-C-NEXT:  entry:
1364 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.readq.vert.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 0, i32 [[SLICE_BASE]])
1365 // CHECK-C-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
1366 //
1367 // CHECK-CXX-LABEL: define dso_local <vscale x 16 x i8> @_Z24test_svread_ver_za128_s8u10__SVInt8_tu10__SVBool_tj(
1368 // CHECK-CXX-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1369 // CHECK-CXX-NEXT:  entry:
1370 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.readq.vert.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 0, i32 [[SLICE_BASE]])
1371 // CHECK-CXX-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
1372 //
1373 svint8_t test_svread_ver_za128_s8(svint8_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1374     return SME_ACLE_FUNC(svread_ver_za128, _s8, _m)(zd, pg, 0, slice_base);
1375 }
1376
1377 // CHECK-C-LABEL: define dso_local <vscale x 16 x i8> @test_svread_ver_za128_s8_1(
1378 // CHECK-C-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1379 // CHECK-C-NEXT:  entry:
1380 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.readq.vert.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 15, i32 [[SLICE_BASE]])
1381 // CHECK-C-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
1382 //
1383 // CHECK-CXX-LABEL: define dso_local <vscale x 16 x i8> @_Z26test_svread_ver_za128_s8_1u10__SVInt8_tu10__SVBool_tj(
1384 // CHECK-CXX-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1385 // CHECK-CXX-NEXT:  entry:
1386 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.readq.vert.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 15, i32 [[SLICE_BASE]])
1387 // CHECK-CXX-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
1388 //
1389 svint8_t test_svread_ver_za128_s8_1(svint8_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1390     return SME_ACLE_FUNC(svread_ver_za128, _s8, _m)(zd, pg, 15, slice_base);
1391 }
1392
1393 // CHECK-C-LABEL: define dso_local <vscale x 8 x i16> @test_svread_ver_za128_s16(
1394 // CHECK-C-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1395 // CHECK-C-NEXT:  entry:
1396 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1397 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.readq.vert.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1398 // CHECK-C-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
1399 //
1400 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x i16> @_Z25test_svread_ver_za128_s16u11__SVInt16_tu10__SVBool_tj(
1401 // CHECK-CXX-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1402 // CHECK-CXX-NEXT:  entry:
1403 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1404 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.readq.vert.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1405 // CHECK-CXX-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
1406 //
1407 svint16_t test_svread_ver_za128_s16(svint16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1408     return SME_ACLE_FUNC(svread_ver_za128, _s16, _m)(zd, pg, 0, slice_base);
1409 }
1410
1411 // CHECK-C-LABEL: define dso_local <vscale x 8 x i16> @test_svread_ver_za128_s16_1(
1412 // CHECK-C-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1413 // CHECK-C-NEXT:  entry:
1414 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1415 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.readq.vert.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
1416 // CHECK-C-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
1417 //
1418 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x i16> @_Z27test_svread_ver_za128_s16_1u11__SVInt16_tu10__SVBool_tj(
1419 // CHECK-CXX-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1420 // CHECK-CXX-NEXT:  entry:
1421 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1422 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.readq.vert.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
1423 // CHECK-CXX-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
1424 //
1425 svint16_t test_svread_ver_za128_s16_1(svint16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1426     return SME_ACLE_FUNC(svread_ver_za128, _s16, _m)(zd, pg, 15, slice_base);
1427 }
1428
1429 // CHECK-C-LABEL: define dso_local <vscale x 4 x i32> @test_svread_ver_za128_s32(
1430 // CHECK-C-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1431 // CHECK-C-NEXT:  entry:
1432 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
1433 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.readq.vert.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1434 // CHECK-C-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
1435 //
1436 // CHECK-CXX-LABEL: define dso_local <vscale x 4 x i32> @_Z25test_svread_ver_za128_s32u11__SVInt32_tu10__SVBool_tj(
1437 // CHECK-CXX-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1438 // CHECK-CXX-NEXT:  entry:
1439 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
1440 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.readq.vert.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1441 // CHECK-CXX-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
1442 //
1443 svint32_t test_svread_ver_za128_s32(svint32_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1444     return SME_ACLE_FUNC(svread_ver_za128, _s32, _m)(zd, pg, 0, slice_base);
1445 }
1446
1447 // CHECK-C-LABEL: define dso_local <vscale x 4 x i32> @test_svread_ver_za128_s32_1(
1448 // CHECK-C-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1449 // CHECK-C-NEXT:  entry:
1450 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
1451 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.readq.vert.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
1452 // CHECK-C-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
1453 //
1454 // CHECK-CXX-LABEL: define dso_local <vscale x 4 x i32> @_Z27test_svread_ver_za128_s32_1u11__SVInt32_tu10__SVBool_tj(
1455 // CHECK-CXX-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1456 // CHECK-CXX-NEXT:  entry:
1457 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
1458 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.readq.vert.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
1459 // CHECK-CXX-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
1460 //
1461 svint32_t test_svread_ver_za128_s32_1(svint32_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1462     return SME_ACLE_FUNC(svread_ver_za128, _s32, _m)(zd, pg, 15, slice_base);
1463 }
1464
1465 // CHECK-C-LABEL: define dso_local <vscale x 2 x i64> @test_svread_ver_za128_s64(
1466 // CHECK-C-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1467 // CHECK-C-NEXT:  entry:
1468 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
1469 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.readq.vert.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1470 // CHECK-C-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
1471 //
1472 // CHECK-CXX-LABEL: define dso_local <vscale x 2 x i64> @_Z25test_svread_ver_za128_s64u11__SVInt64_tu10__SVBool_tj(
1473 // CHECK-CXX-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1474 // CHECK-CXX-NEXT:  entry:
1475 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
1476 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.readq.vert.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1477 // CHECK-CXX-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
1478 //
1479 svint64_t test_svread_ver_za128_s64(svint64_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1480     return SME_ACLE_FUNC(svread_ver_za128, _s64, _m)(zd, pg, 0, slice_base);
1481 }
1482
1483 // CHECK-C-LABEL: define dso_local <vscale x 2 x i64> @test_svread_ver_za128_s64_1(
1484 // CHECK-C-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1485 // CHECK-C-NEXT:  entry:
1486 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
1487 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.readq.vert.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
1488 // CHECK-C-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
1489 //
1490 // CHECK-CXX-LABEL: define dso_local <vscale x 2 x i64> @_Z27test_svread_ver_za128_s64_1u11__SVInt64_tu10__SVBool_tj(
1491 // CHECK-CXX-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1492 // CHECK-CXX-NEXT:  entry:
1493 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
1494 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.readq.vert.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
1495 // CHECK-CXX-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
1496 //
1497 svint64_t test_svread_ver_za128_s64_1(svint64_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1498     return SME_ACLE_FUNC(svread_ver_za128, _s64, _m)(zd, pg, 15, slice_base);
1499 }
1500
1501 // CHECK-C-LABEL: define dso_local <vscale x 16 x i8> @test_svread_ver_za128_u8(
1502 // CHECK-C-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1503 // CHECK-C-NEXT:  entry:
1504 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.readq.vert.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 0, i32 [[SLICE_BASE]])
1505 // CHECK-C-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
1506 //
1507 // CHECK-CXX-LABEL: define dso_local <vscale x 16 x i8> @_Z24test_svread_ver_za128_u8u11__SVUint8_tu10__SVBool_tj(
1508 // CHECK-CXX-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1509 // CHECK-CXX-NEXT:  entry:
1510 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.readq.vert.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 0, i32 [[SLICE_BASE]])
1511 // CHECK-CXX-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
1512 //
1513 svuint8_t test_svread_ver_za128_u8(svuint8_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1514     return SME_ACLE_FUNC(svread_ver_za128, _u8, _m)(zd, pg, 0, slice_base);
1515 }
1516
1517 // CHECK-C-LABEL: define dso_local <vscale x 16 x i8> @test_svread_ver_za128_u8_1(
1518 // CHECK-C-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1519 // CHECK-C-NEXT:  entry:
1520 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.readq.vert.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 15, i32 [[SLICE_BASE]])
1521 // CHECK-C-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
1522 //
1523 // CHECK-CXX-LABEL: define dso_local <vscale x 16 x i8> @_Z26test_svread_ver_za128_u8_1u11__SVUint8_tu10__SVBool_tj(
1524 // CHECK-CXX-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1525 // CHECK-CXX-NEXT:  entry:
1526 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.readq.vert.nxv16i8(<vscale x 16 x i8> [[ZD]], <vscale x 16 x i1> [[PG]], i32 15, i32 [[SLICE_BASE]])
1527 // CHECK-CXX-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
1528 //
1529 svuint8_t test_svread_ver_za128_u8_1(svuint8_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1530     return SME_ACLE_FUNC(svread_ver_za128, _u8, _m)(zd, pg, 15, slice_base);
1531 }
1532
1533 // CHECK-C-LABEL: define dso_local <vscale x 8 x i16> @test_svread_ver_za128_u16(
1534 // CHECK-C-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1535 // CHECK-C-NEXT:  entry:
1536 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1537 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.readq.vert.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1538 // CHECK-C-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
1539 //
1540 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x i16> @_Z25test_svread_ver_za128_u16u12__SVUint16_tu10__SVBool_tj(
1541 // CHECK-CXX-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1542 // CHECK-CXX-NEXT:  entry:
1543 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1544 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.readq.vert.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1545 // CHECK-CXX-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
1546 //
1547 svuint16_t test_svread_ver_za128_u16(svuint16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1548     return SME_ACLE_FUNC(svread_ver_za128, _u16, _m)(zd, pg, 0, slice_base);
1549 }
1550
1551 // CHECK-C-LABEL: define dso_local <vscale x 8 x i16> @test_svread_ver_za128_u16_1(
1552 // CHECK-C-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1553 // CHECK-C-NEXT:  entry:
1554 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1555 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.readq.vert.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
1556 // CHECK-C-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
1557 //
1558 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x i16> @_Z27test_svread_ver_za128_u16_1u12__SVUint16_tu10__SVBool_tj(
1559 // CHECK-CXX-SAME: <vscale x 8 x i16> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1560 // CHECK-CXX-NEXT:  entry:
1561 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1562 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.readq.vert.nxv8i16(<vscale x 8 x i16> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
1563 // CHECK-CXX-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
1564 //
1565 svuint16_t test_svread_ver_za128_u16_1(svuint16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1566     return SME_ACLE_FUNC(svread_ver_za128, _u16, _m)(zd, pg, 15, slice_base);
1567 }
1568
1569 // CHECK-C-LABEL: define dso_local <vscale x 4 x i32> @test_svread_ver_za128_u32(
1570 // CHECK-C-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1571 // CHECK-C-NEXT:  entry:
1572 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
1573 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.readq.vert.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1574 // CHECK-C-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
1575 //
1576 // CHECK-CXX-LABEL: define dso_local <vscale x 4 x i32> @_Z25test_svread_ver_za128_u32u12__SVUint32_tu10__SVBool_tj(
1577 // CHECK-CXX-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1578 // CHECK-CXX-NEXT:  entry:
1579 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
1580 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.readq.vert.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1581 // CHECK-CXX-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
1582 //
1583 svuint32_t test_svread_ver_za128_u32(svuint32_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1584     return SME_ACLE_FUNC(svread_ver_za128, _u32, _m)(zd, pg, 0, slice_base);
1585 }
1586
1587 // CHECK-C-LABEL: define dso_local <vscale x 4 x i32> @test_svread_ver_za128_u32_1(
1588 // CHECK-C-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1589 // CHECK-C-NEXT:  entry:
1590 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
1591 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.readq.vert.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
1592 // CHECK-C-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
1593 //
1594 // CHECK-CXX-LABEL: define dso_local <vscale x 4 x i32> @_Z27test_svread_ver_za128_u32_1u12__SVUint32_tu10__SVBool_tj(
1595 // CHECK-CXX-SAME: <vscale x 4 x i32> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1596 // CHECK-CXX-NEXT:  entry:
1597 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
1598 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.readq.vert.nxv4i32(<vscale x 4 x i32> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
1599 // CHECK-CXX-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
1600 //
1601 svuint32_t test_svread_ver_za128_u32_1(svuint32_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1602     return SME_ACLE_FUNC(svread_ver_za128, _u32, _m)(zd, pg, 15, slice_base);
1603 }
1604
1605 // CHECK-C-LABEL: define dso_local <vscale x 2 x i64> @test_svread_ver_za128_u64(
1606 // CHECK-C-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1607 // CHECK-C-NEXT:  entry:
1608 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
1609 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.readq.vert.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1610 // CHECK-C-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
1611 //
1612 // CHECK-CXX-LABEL: define dso_local <vscale x 2 x i64> @_Z25test_svread_ver_za128_u64u12__SVUint64_tu10__SVBool_tj(
1613 // CHECK-CXX-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1614 // CHECK-CXX-NEXT:  entry:
1615 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
1616 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.readq.vert.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1617 // CHECK-CXX-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
1618 //
1619 svuint64_t test_svread_ver_za128_u64(svuint64_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1620     return SME_ACLE_FUNC(svread_ver_za128, _u64, _m)(zd, pg, 0, slice_base);
1621 }
1622
1623 // CHECK-C-LABEL: define dso_local <vscale x 2 x i64> @test_svread_ver_za128_u64_1(
1624 // CHECK-C-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1625 // CHECK-C-NEXT:  entry:
1626 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
1627 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.readq.vert.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
1628 // CHECK-C-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
1629 //
1630 // CHECK-CXX-LABEL: define dso_local <vscale x 2 x i64> @_Z27test_svread_ver_za128_u64_1u12__SVUint64_tu10__SVBool_tj(
1631 // CHECK-CXX-SAME: <vscale x 2 x i64> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1632 // CHECK-CXX-NEXT:  entry:
1633 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
1634 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sme.readq.vert.nxv2i64(<vscale x 2 x i64> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
1635 // CHECK-CXX-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
1636 //
1637 svuint64_t test_svread_ver_za128_u64_1(svuint64_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1638     return SME_ACLE_FUNC(svread_ver_za128, _u64, _m)(zd, pg, 15, slice_base);
1639 }
1640
1641 // CHECK-C-LABEL: define dso_local <vscale x 8 x half> @test_svread_ver_za128_f16(
1642 // CHECK-C-SAME: <vscale x 8 x half> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1643 // CHECK-C-NEXT:  entry:
1644 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1645 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sme.readq.vert.nxv8f16(<vscale x 8 x half> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1646 // CHECK-C-NEXT:    ret <vscale x 8 x half> [[TMP1]]
1647 //
1648 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x half> @_Z25test_svread_ver_za128_f16u13__SVFloat16_tu10__SVBool_tj(
1649 // CHECK-CXX-SAME: <vscale x 8 x half> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1650 // CHECK-CXX-NEXT:  entry:
1651 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1652 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sme.readq.vert.nxv8f16(<vscale x 8 x half> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1653 // CHECK-CXX-NEXT:    ret <vscale x 8 x half> [[TMP1]]
1654 //
1655 svfloat16_t test_svread_ver_za128_f16(svfloat16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1656     return SME_ACLE_FUNC(svread_ver_za128, _f16, _m)(zd, pg, 0, slice_base);
1657 }
1658
1659 // CHECK-C-LABEL: define dso_local <vscale x 8 x half> @test_svread_ver_za128_f16_1(
1660 // CHECK-C-SAME: <vscale x 8 x half> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1661 // CHECK-C-NEXT:  entry:
1662 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1663 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sme.readq.vert.nxv8f16(<vscale x 8 x half> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
1664 // CHECK-C-NEXT:    ret <vscale x 8 x half> [[TMP1]]
1665 //
1666 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x half> @_Z27test_svread_ver_za128_f16_1u13__SVFloat16_tu10__SVBool_tj(
1667 // CHECK-CXX-SAME: <vscale x 8 x half> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1668 // CHECK-CXX-NEXT:  entry:
1669 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1670 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sme.readq.vert.nxv8f16(<vscale x 8 x half> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
1671 // CHECK-CXX-NEXT:    ret <vscale x 8 x half> [[TMP1]]
1672 //
1673 svfloat16_t test_svread_ver_za128_f16_1(svfloat16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1674     return SME_ACLE_FUNC(svread_ver_za128, _f16, _m)(zd, pg, 15, slice_base);
1675 }
1676
1677 // CHECK-C-LABEL: define dso_local <vscale x 8 x bfloat> @test_svread_ver_za128_bf16(
1678 // CHECK-C-SAME: <vscale x 8 x bfloat> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1679 // CHECK-C-NEXT:  entry:
1680 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1681 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sme.readq.vert.nxv8bf16(<vscale x 8 x bfloat> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1682 // CHECK-C-NEXT:    ret <vscale x 8 x bfloat> [[TMP1]]
1683 //
1684 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x bfloat> @_Z26test_svread_ver_za128_bf16u14__SVBfloat16_tu10__SVBool_tj(
1685 // CHECK-CXX-SAME: <vscale x 8 x bfloat> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1686 // CHECK-CXX-NEXT:  entry:
1687 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1688 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sme.readq.vert.nxv8bf16(<vscale x 8 x bfloat> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1689 // CHECK-CXX-NEXT:    ret <vscale x 8 x bfloat> [[TMP1]]
1690 //
1691 svbfloat16_t test_svread_ver_za128_bf16(svbfloat16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1692     return SME_ACLE_FUNC(svread_ver_za128, _bf16, _m)(zd, pg, 0, slice_base);
1693 }
1694
1695 // CHECK-C-LABEL: define dso_local <vscale x 8 x bfloat> @test_svread_ver_za128_bf16_1(
1696 // CHECK-C-SAME: <vscale x 8 x bfloat> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1697 // CHECK-C-NEXT:  entry:
1698 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1699 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sme.readq.vert.nxv8bf16(<vscale x 8 x bfloat> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
1700 // CHECK-C-NEXT:    ret <vscale x 8 x bfloat> [[TMP1]]
1701 //
1702 // CHECK-CXX-LABEL: define dso_local <vscale x 8 x bfloat> @_Z28test_svread_ver_za128_bf16_1u14__SVBfloat16_tu10__SVBool_tj(
1703 // CHECK-CXX-SAME: <vscale x 8 x bfloat> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1704 // CHECK-CXX-NEXT:  entry:
1705 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG]])
1706 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sme.readq.vert.nxv8bf16(<vscale x 8 x bfloat> [[ZD]], <vscale x 8 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
1707 // CHECK-CXX-NEXT:    ret <vscale x 8 x bfloat> [[TMP1]]
1708 //
1709 svbfloat16_t test_svread_ver_za128_bf16_1(svbfloat16_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1710     return SME_ACLE_FUNC(svread_ver_za128, _bf16, _m)(zd, pg, 15, slice_base);
1711 }
1712
1713 // CHECK-C-LABEL: define dso_local <vscale x 4 x float> @test_svread_ver_za128_f32(
1714 // CHECK-C-SAME: <vscale x 4 x float> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1715 // CHECK-C-NEXT:  entry:
1716 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
1717 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sme.readq.vert.nxv4f32(<vscale x 4 x float> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1718 // CHECK-C-NEXT:    ret <vscale x 4 x float> [[TMP1]]
1719 //
1720 // CHECK-CXX-LABEL: define dso_local <vscale x 4 x float> @_Z25test_svread_ver_za128_f32u13__SVFloat32_tu10__SVBool_tj(
1721 // CHECK-CXX-SAME: <vscale x 4 x float> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1722 // CHECK-CXX-NEXT:  entry:
1723 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
1724 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sme.readq.vert.nxv4f32(<vscale x 4 x float> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1725 // CHECK-CXX-NEXT:    ret <vscale x 4 x float> [[TMP1]]
1726 //
1727 svfloat32_t test_svread_ver_za128_f32(svfloat32_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1728     return SME_ACLE_FUNC(svread_ver_za128, _f32, _m)(zd, pg, 0, slice_base);
1729 }
1730
1731 // CHECK-C-LABEL: define dso_local <vscale x 4 x float> @test_svread_ver_za128_f32_1(
1732 // CHECK-C-SAME: <vscale x 4 x float> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1733 // CHECK-C-NEXT:  entry:
1734 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
1735 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sme.readq.vert.nxv4f32(<vscale x 4 x float> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
1736 // CHECK-C-NEXT:    ret <vscale x 4 x float> [[TMP1]]
1737 //
1738 // CHECK-CXX-LABEL: define dso_local <vscale x 4 x float> @_Z27test_svread_ver_za128_f32_1u13__SVFloat32_tu10__SVBool_tj(
1739 // CHECK-CXX-SAME: <vscale x 4 x float> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1740 // CHECK-CXX-NEXT:  entry:
1741 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG]])
1742 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sme.readq.vert.nxv4f32(<vscale x 4 x float> [[ZD]], <vscale x 4 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
1743 // CHECK-CXX-NEXT:    ret <vscale x 4 x float> [[TMP1]]
1744 //
1745 svfloat32_t test_svread_ver_za128_f32_1(svfloat32_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1746     return SME_ACLE_FUNC(svread_ver_za128, _f32, _m)(zd, pg, 15, slice_base);
1747 }
1748
1749 // CHECK-C-LABEL: define dso_local <vscale x 2 x double> @test_svread_ver_za128_f64(
1750 // CHECK-C-SAME: <vscale x 2 x double> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1751 // CHECK-C-NEXT:  entry:
1752 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
1753 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sme.readq.vert.nxv2f64(<vscale x 2 x double> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1754 // CHECK-C-NEXT:    ret <vscale x 2 x double> [[TMP1]]
1755 //
1756 // CHECK-CXX-LABEL: define dso_local <vscale x 2 x double> @_Z25test_svread_ver_za128_f64u13__SVFloat64_tu10__SVBool_tj(
1757 // CHECK-CXX-SAME: <vscale x 2 x double> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1758 // CHECK-CXX-NEXT:  entry:
1759 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
1760 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sme.readq.vert.nxv2f64(<vscale x 2 x double> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 0, i32 [[SLICE_BASE]])
1761 // CHECK-CXX-NEXT:    ret <vscale x 2 x double> [[TMP1]]
1762 //
1763 svfloat64_t test_svread_ver_za128_f64(svfloat64_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1764     return SME_ACLE_FUNC(svread_ver_za128, _f64, _m)(zd, pg, 0, slice_base);
1765 }
1766
1767 // CHECK-C-LABEL: define dso_local <vscale x 2 x double> @test_svread_ver_za128_f64_1(
1768 // CHECK-C-SAME: <vscale x 2 x double> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1769 // CHECK-C-NEXT:  entry:
1770 // CHECK-C-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
1771 // CHECK-C-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sme.readq.vert.nxv2f64(<vscale x 2 x double> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
1772 // CHECK-C-NEXT:    ret <vscale x 2 x double> [[TMP1]]
1773 //
1774 // CHECK-CXX-LABEL: define dso_local <vscale x 2 x double> @_Z27test_svread_ver_za128_f64_1u13__SVFloat64_tu10__SVBool_tj(
1775 // CHECK-CXX-SAME: <vscale x 2 x double> [[ZD:%.*]], <vscale x 16 x i1> [[PG:%.*]], i32 noundef [[SLICE_BASE:%.*]]) local_unnamed_addr #[[ATTR0]] {
1776 // CHECK-CXX-NEXT:  entry:
1777 // CHECK-CXX-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG]])
1778 // CHECK-CXX-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sme.readq.vert.nxv2f64(<vscale x 2 x double> [[ZD]], <vscale x 2 x i1> [[TMP0]], i32 15, i32 [[SLICE_BASE]])
1779 // CHECK-CXX-NEXT:    ret <vscale x 2 x double> [[TMP1]]
1780 //
1781 svfloat64_t test_svread_ver_za128_f64_1(svfloat64_t zd, svbool_t pg, uint32_t slice_base) __arm_streaming __arm_in("za") {
1782     return SME_ACLE_FUNC(svread_ver_za128, _f64, _m)(zd, pg, 15, slice_base);
1783 }
1784 //// NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
1785 // CHECK: {{.*}}