clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2
   3 // REQUIRES: aarch64-registered-target
   4
   5 // RUN: %clang_cc1 -triple aarch64 -target-feature +bf16 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
   6 // RUN: %clang_cc1 -triple aarch64 -target-feature +bf16 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
   7 // RUN: %clang_cc1 -triple aarch64 -target-feature +bf16 -target-feature +sme -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
   8
   9 #include <arm_sme.h>
  10
  11
  12 // CHECK-LABEL: @test_svluti4_lane_zt_u8(
  13 // CHECK-NEXT:  entry:
  14 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 7)
  15 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  16 //
  17 // CPP-CHECK-LABEL: @_Z23test_svluti4_lane_zt_u8u11__SVUint8_t(
  18 // CPP-CHECK-NEXT:  entry:
  19 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 7)
  20 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  21 //
  22 svuint8_t test_svluti4_lane_zt_u8(svuint8_t zn) __arm_streaming __arm_in("zt0") {
  23   return svluti4_lane_zt_u8(0, zn, 7);
  24 }
  25
  26
  27 // CHECK-LABEL: @test_svluti4_lane_zt_s8(
  28 // CHECK-NEXT:  entry:
  29 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 7)
  30 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  31 //
  32 // CPP-CHECK-LABEL: @_Z23test_svluti4_lane_zt_s8u11__SVUint8_t(
  33 // CPP-CHECK-NEXT:  entry:
  34 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 7)
  35 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  36 //
  37 svint8_t test_svluti4_lane_zt_s8(svuint8_t zn) __arm_streaming __arm_in("zt0") {
  38   return svluti4_lane_zt_s8(0, zn, 7);
  39 }
  40
  41 // CHECK-LABEL: @test_svluti4_lane_zt_u16(
  42 // CHECK-NEXT:  entry:
  43 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 7)
  44 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  45 //
  46 // CPP-CHECK-LABEL: @_Z24test_svluti4_lane_zt_u16u11__SVUint8_t(
  47 // CPP-CHECK-NEXT:  entry:
  48 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 7)
  49 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  50 //
  51 svuint16_t test_svluti4_lane_zt_u16(svuint8_t zn) __arm_streaming __arm_in("zt0") {
  52   return svluti4_lane_zt_u16(0, zn, 7);
  53 }
  54
  55 // CHECK-LABEL: @test_svluti4_lane_zt_s16(
  56 // CHECK-NEXT:  entry:
  57 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 7)
  58 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  59 //
  60 // CPP-CHECK-LABEL: @_Z24test_svluti4_lane_zt_s16u11__SVUint8_t(
  61 // CPP-CHECK-NEXT:  entry:
  62 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 7)
  63 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  64 //
  65 svint16_t test_svluti4_lane_zt_s16(svuint8_t zn) __arm_streaming __arm_in("zt0") {
  66   return svluti4_lane_zt_s16(0, zn, 7);
  67 }
  68
  69 // CHECK-LABEL: @test_svluti4_lane_zt_f16(
  70 // CHECK-NEXT:  entry:
  71 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 7)
  72 // CHECK-NEXT:    ret <vscale x 8 x half> [[TMP0]]
  73 //
  74 // CPP-CHECK-LABEL: @_Z24test_svluti4_lane_zt_f16u11__SVUint8_t(
  75 // CPP-CHECK-NEXT:  entry:
  76 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 7)
  77 // CPP-CHECK-NEXT:    ret <vscale x 8 x half> [[TMP0]]
  78 //
  79 svfloat16_t test_svluti4_lane_zt_f16(svuint8_t zn) __arm_streaming __arm_in("zt0") {
  80   return svluti4_lane_zt_f16(0, zn, 7);
  81 }
  82
  83 // CHECK-LABEL: @test_svluti4_lane_zt_bf16(
  84 // CHECK-NEXT:  entry:
  85 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 7)
  86 // CHECK-NEXT:    ret <vscale x 8 x bfloat> [[TMP0]]
  87 //
  88 // CPP-CHECK-LABEL: @_Z25test_svluti4_lane_zt_bf16u11__SVUint8_t(
  89 // CPP-CHECK-NEXT:  entry:
  90 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 7)
  91 // CPP-CHECK-NEXT:    ret <vscale x 8 x bfloat> [[TMP0]]
  92 //
  93 svbfloat16_t test_svluti4_lane_zt_bf16(svuint8_t zn) __arm_streaming __arm_in("zt0") {
  94   return svluti4_lane_zt_bf16(0, zn, 7);
  95 }
  96
  97 // CHECK-LABEL: @test_svluti4_lane_zt_u32(
  98 // CHECK-NEXT:  entry:
  99 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 7)
 100 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 101 //
 102 // CPP-CHECK-LABEL: @_Z24test_svluti4_lane_zt_u32u11__SVUint8_t(
 103 // CPP-CHECK-NEXT:  entry:
 104 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 7)
 105 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 106 //
 107 svuint32_t test_svluti4_lane_zt_u32(svuint8_t zn) __arm_streaming __arm_in("zt0") {
 108   return svluti4_lane_zt_u32(0, zn, 7);
 109 }
 110
 111 // CHECK-LABEL: @test_svluti4_lane_zt_s32(
 112 // CHECK-NEXT:  entry:
 113 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 7)
 114 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 115 //
 116 // CPP-CHECK-LABEL: @_Z24test_svluti4_lane_zt_s32u11__SVUint8_t(
 117 // CPP-CHECK-NEXT:  entry:
 118 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 7)
 119 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 120 //
 121 svint32_t test_svluti4_lane_zt_s32(svuint8_t zn) __arm_streaming __arm_in("zt0") {
 122   return svluti4_lane_zt_s32(0, zn, 7);
 123 }
 124
 125 // CHECK-LABEL: @test_svluti4_lane_zt_f32(
 126 // CHECK-NEXT:  entry:
 127 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 7)
 128 // CHECK-NEXT:    ret <vscale x 4 x float> [[TMP0]]
 129 //
 130 // CPP-CHECK-LABEL: @_Z24test_svluti4_lane_zt_f32u11__SVUint8_t(
 131 // CPP-CHECK-NEXT:  entry:
 132 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 7)
 133 // CPP-CHECK-NEXT:    ret <vscale x 4 x float> [[TMP0]]
 134 //
 135 svfloat32_t test_svluti4_lane_zt_f32(svuint8_t zn) __arm_streaming __arm_in("zt0") {
 136   return svluti4_lane_zt_f32(0, zn, 7);
 137 }