clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature
   2 // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a\
   3 // RUN: -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - %s \
   4 // RUN: | opt -S -passes=mem2reg \
   5 // RUN: | FileCheck %s
   6
   7 // REQUIRES: aarch64-registered-target
   8
   9 #include <arm_neon.h>
  10
  11 // CHECK-LABEL: define {{[^@]+}}@test_vabs_f16
  12 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] {
  13 // CHECK-NEXT:  entry:
  14 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
  15 // CHECK-NEXT:    [[VABS1_I:%.*]] = call <4 x half> @llvm.fabs.v4f16(<4 x half> [[A]])
  16 // CHECK-NEXT:    ret <4 x half> [[VABS1_I]]
  17 //
  18 float16x4_t test_vabs_f16(float16x4_t a) {
  19   return vabs_f16(a);
  20 }
  21
  22 // CHECK-LABEL: define {{[^@]+}}@test_vabsq_f16
  23 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
  24 // CHECK-NEXT:  entry:
  25 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
  26 // CHECK-NEXT:    [[VABS1_I:%.*]] = call <8 x half> @llvm.fabs.v8f16(<8 x half> [[A]])
  27 // CHECK-NEXT:    ret <8 x half> [[VABS1_I]]
  28 //
  29 float16x8_t test_vabsq_f16(float16x8_t a) {
  30   return vabsq_f16(a);
  31 }
  32
  33 // CHECK-LABEL: define {{[^@]+}}@test_vceqz_f16
  34 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
  35 // CHECK-NEXT:  entry:
  36 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
  37 // CHECK-NEXT:    [[TMP1:%.*]] = fcmp oeq <4 x half> [[A]], zeroinitializer
  38 // CHECK-NEXT:    [[VCEQZ_I:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16>
  39 // CHECK-NEXT:    ret <4 x i16> [[VCEQZ_I]]
  40 //
  41 uint16x4_t test_vceqz_f16(float16x4_t a) {
  42   return vceqz_f16(a);
  43 }
  44
  45 // CHECK-LABEL: define {{[^@]+}}@test_vceqzq_f16
  46 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
  47 // CHECK-NEXT:  entry:
  48 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
  49 // CHECK-NEXT:    [[TMP1:%.*]] = fcmp oeq <8 x half> [[A]], zeroinitializer
  50 // CHECK-NEXT:    [[VCEQZ_I:%.*]] = sext <8 x i1> [[TMP1]] to <8 x i16>
  51 // CHECK-NEXT:    ret <8 x i16> [[VCEQZ_I]]
  52 //
  53 uint16x8_t test_vceqzq_f16(float16x8_t a) {
  54   return vceqzq_f16(a);
  55 }
  56
  57 // CHECK-LABEL: define {{[^@]+}}@test_vcgez_f16
  58 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
  59 // CHECK-NEXT:  entry:
  60 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
  61 // CHECK-NEXT:    [[TMP1:%.*]] = fcmp oge <4 x half> [[A]], zeroinitializer
  62 // CHECK-NEXT:    [[VCGEZ_I:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16>
  63 // CHECK-NEXT:    ret <4 x i16> [[VCGEZ_I]]
  64 //
  65 uint16x4_t test_vcgez_f16(float16x4_t a) {
  66   return vcgez_f16(a);
  67 }
  68
  69 // CHECK-LABEL: define {{[^@]+}}@test_vcgezq_f16
  70 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
  71 // CHECK-NEXT:  entry:
  72 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
  73 // CHECK-NEXT:    [[TMP1:%.*]] = fcmp oge <8 x half> [[A]], zeroinitializer
  74 // CHECK-NEXT:    [[VCGEZ_I:%.*]] = sext <8 x i1> [[TMP1]] to <8 x i16>
  75 // CHECK-NEXT:    ret <8 x i16> [[VCGEZ_I]]
  76 //
  77 uint16x8_t test_vcgezq_f16(float16x8_t a) {
  78   return vcgezq_f16(a);
  79 }
  80
  81 // CHECK-LABEL: define {{[^@]+}}@test_vcgtz_f16
  82 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
  83 // CHECK-NEXT:  entry:
  84 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
  85 // CHECK-NEXT:    [[TMP1:%.*]] = fcmp ogt <4 x half> [[A]], zeroinitializer
  86 // CHECK-NEXT:    [[VCGTZ_I:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16>
  87 // CHECK-NEXT:    ret <4 x i16> [[VCGTZ_I]]
  88 //
  89 uint16x4_t test_vcgtz_f16(float16x4_t a) {
  90   return vcgtz_f16(a);
  91 }
  92
  93 // CHECK-LABEL: define {{[^@]+}}@test_vcgtzq_f16
  94 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
  95 // CHECK-NEXT:  entry:
  96 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
  97 // CHECK-NEXT:    [[TMP1:%.*]] = fcmp ogt <8 x half> [[A]], zeroinitializer
  98 // CHECK-NEXT:    [[VCGTZ_I:%.*]] = sext <8 x i1> [[TMP1]] to <8 x i16>
  99 // CHECK-NEXT:    ret <8 x i16> [[VCGTZ_I]]
 100 //
 101 uint16x8_t test_vcgtzq_f16(float16x8_t a) {
 102   return vcgtzq_f16(a);
 103 }
 104
 105 // CHECK-LABEL: define {{[^@]+}}@test_vclez_f16
 106 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 107 // CHECK-NEXT:  entry:
 108 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 109 // CHECK-NEXT:    [[TMP1:%.*]] = fcmp ole <4 x half> [[A]], zeroinitializer
 110 // CHECK-NEXT:    [[VCLEZ_I:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16>
 111 // CHECK-NEXT:    ret <4 x i16> [[VCLEZ_I]]
 112 //
 113 uint16x4_t test_vclez_f16(float16x4_t a) {
 114   return vclez_f16(a);
 115 }
 116
 117 // CHECK-LABEL: define {{[^@]+}}@test_vclezq_f16
 118 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 119 // CHECK-NEXT:  entry:
 120 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 121 // CHECK-NEXT:    [[TMP1:%.*]] = fcmp ole <8 x half> [[A]], zeroinitializer
 122 // CHECK-NEXT:    [[VCLEZ_I:%.*]] = sext <8 x i1> [[TMP1]] to <8 x i16>
 123 // CHECK-NEXT:    ret <8 x i16> [[VCLEZ_I]]
 124 //
 125 uint16x8_t test_vclezq_f16(float16x8_t a) {
 126   return vclezq_f16(a);
 127 }
 128
 129 // CHECK-LABEL: define {{[^@]+}}@test_vcltz_f16
 130 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 131 // CHECK-NEXT:  entry:
 132 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 133 // CHECK-NEXT:    [[TMP1:%.*]] = fcmp olt <4 x half> [[A]], zeroinitializer
 134 // CHECK-NEXT:    [[VCLTZ_I:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16>
 135 // CHECK-NEXT:    ret <4 x i16> [[VCLTZ_I]]
 136 //
 137 uint16x4_t test_vcltz_f16(float16x4_t a) {
 138   return vcltz_f16(a);
 139 }
 140
 141 // CHECK-LABEL: define {{[^@]+}}@test_vcltzq_f16
 142 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 143 // CHECK-NEXT:  entry:
 144 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 145 // CHECK-NEXT:    [[TMP1:%.*]] = fcmp olt <8 x half> [[A]], zeroinitializer
 146 // CHECK-NEXT:    [[VCLTZ_I:%.*]] = sext <8 x i1> [[TMP1]] to <8 x i16>
 147 // CHECK-NEXT:    ret <8 x i16> [[VCLTZ_I]]
 148 //
 149 uint16x8_t test_vcltzq_f16(float16x8_t a) {
 150   return vcltzq_f16(a);
 151 }
 152
 153 // CHECK-LABEL: define {{[^@]+}}@test_vcvt_f16_s16
 154 // CHECK-SAME: (<4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
 155 // CHECK-NEXT:  entry:
 156 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
 157 // CHECK-NEXT:    [[VCVT_I:%.*]] = sitofp <4 x i16> [[A]] to <4 x half>
 158 // CHECK-NEXT:    ret <4 x half> [[VCVT_I]]
 159 //
 160 float16x4_t test_vcvt_f16_s16 (int16x4_t a) {
 161   return vcvt_f16_s16(a);
 162 }
 163
 164 // CHECK-LABEL: define {{[^@]+}}@test_vcvtq_f16_s16
 165 // CHECK-SAME: (<8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
 166 // CHECK-NEXT:  entry:
 167 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
 168 // CHECK-NEXT:    [[VCVT_I:%.*]] = sitofp <8 x i16> [[A]] to <8 x half>
 169 // CHECK-NEXT:    ret <8 x half> [[VCVT_I]]
 170 //
 171 float16x8_t test_vcvtq_f16_s16 (int16x8_t a) {
 172   return vcvtq_f16_s16(a);
 173 }
 174
 175 // CHECK-LABEL: define {{[^@]+}}@test_vcvt_f16_u16
 176 // CHECK-SAME: (<4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
 177 // CHECK-NEXT:  entry:
 178 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
 179 // CHECK-NEXT:    [[VCVT_I:%.*]] = uitofp <4 x i16> [[A]] to <4 x half>
 180 // CHECK-NEXT:    ret <4 x half> [[VCVT_I]]
 181 //
 182 float16x4_t test_vcvt_f16_u16 (uint16x4_t a) {
 183   return vcvt_f16_u16(a);
 184 }
 185
 186 // CHECK-LABEL: define {{[^@]+}}@test_vcvtq_f16_u16
 187 // CHECK-SAME: (<8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
 188 // CHECK-NEXT:  entry:
 189 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
 190 // CHECK-NEXT:    [[VCVT_I:%.*]] = uitofp <8 x i16> [[A]] to <8 x half>
 191 // CHECK-NEXT:    ret <8 x half> [[VCVT_I]]
 192 //
 193 float16x8_t test_vcvtq_f16_u16 (uint16x8_t a) {
 194   return vcvtq_f16_u16(a);
 195 }
 196
 197 // CHECK-LABEL: define {{[^@]+}}@test_vcvt_s16_f16
 198 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 199 // CHECK-NEXT:  entry:
 200 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 201 // CHECK-NEXT:    [[VCVTZ1_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtzs.v4i16.v4f16(<4 x half> [[A]])
 202 // CHECK-NEXT:    ret <4 x i16> [[VCVTZ1_I]]
 203 //
 204 int16x4_t test_vcvt_s16_f16 (float16x4_t a) {
 205   return vcvt_s16_f16(a);
 206 }
 207
 208 // CHECK-LABEL: define {{[^@]+}}@test_vcvtq_s16_f16
 209 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 210 // CHECK-NEXT:  entry:
 211 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 212 // CHECK-NEXT:    [[VCVTZ1_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.fcvtzs.v8i16.v8f16(<8 x half> [[A]])
 213 // CHECK-NEXT:    ret <8 x i16> [[VCVTZ1_I]]
 214 //
 215 int16x8_t test_vcvtq_s16_f16 (float16x8_t a) {
 216   return vcvtq_s16_f16(a);
 217 }
 218
 219 // CHECK-LABEL: define {{[^@]+}}@test_vcvt_u16_f16
 220 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 221 // CHECK-NEXT:  entry:
 222 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 223 // CHECK-NEXT:    [[VCVTZ1_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtzu.v4i16.v4f16(<4 x half> [[A]])
 224 // CHECK-NEXT:    ret <4 x i16> [[VCVTZ1_I]]
 225 //
 226 uint16x4_t test_vcvt_u16_f16 (float16x4_t a) {
 227   return vcvt_u16_f16(a);
 228 }
 229
 230 // CHECK-LABEL: define {{[^@]+}}@test_vcvtq_u16_f16
 231 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 232 // CHECK-NEXT:  entry:
 233 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 234 // CHECK-NEXT:    [[VCVTZ1_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.fcvtzu.v8i16.v8f16(<8 x half> [[A]])
 235 // CHECK-NEXT:    ret <8 x i16> [[VCVTZ1_I]]
 236 //
 237 uint16x8_t test_vcvtq_u16_f16 (float16x8_t a) {
 238   return vcvtq_u16_f16(a);
 239 }
 240
 241 // CHECK-LABEL: define {{[^@]+}}@test_vcvta_s16_f16
 242 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 243 // CHECK-NEXT:  entry:
 244 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 245 // CHECK-NEXT:    [[VCVTA1_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtas.v4i16.v4f16(<4 x half> [[A]])
 246 // CHECK-NEXT:    ret <4 x i16> [[VCVTA1_I]]
 247 //
 248 int16x4_t test_vcvta_s16_f16 (float16x4_t a) {
 249   return vcvta_s16_f16(a);
 250 }
 251
 252 // CHECK-LABEL: define {{[^@]+}}@test_vcvta_u16_f16
 253 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 254 // CHECK-NEXT:  entry:
 255 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 256 // CHECK-NEXT:    [[VCVTA1_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtau.v4i16.v4f16(<4 x half> [[A]])
 257 // CHECK-NEXT:    ret <4 x i16> [[VCVTA1_I]]
 258 //
 259 uint16x4_t test_vcvta_u16_f16 (float16x4_t a) {
 260   return vcvta_u16_f16(a);
 261 }
 262
 263 // CHECK-LABEL: define {{[^@]+}}@test_vcvtaq_s16_f16
 264 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 265 // CHECK-NEXT:  entry:
 266 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 267 // CHECK-NEXT:    [[VCVTA1_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.fcvtas.v8i16.v8f16(<8 x half> [[A]])
 268 // CHECK-NEXT:    ret <8 x i16> [[VCVTA1_I]]
 269 //
 270 int16x8_t test_vcvtaq_s16_f16 (float16x8_t a) {
 271   return vcvtaq_s16_f16(a);
 272 }
 273
 274 // CHECK-LABEL: define {{[^@]+}}@test_vcvtm_s16_f16
 275 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 276 // CHECK-NEXT:  entry:
 277 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 278 // CHECK-NEXT:    [[VCVTM1_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtms.v4i16.v4f16(<4 x half> [[A]])
 279 // CHECK-NEXT:    ret <4 x i16> [[VCVTM1_I]]
 280 //
 281 int16x4_t test_vcvtm_s16_f16 (float16x4_t a) {
 282   return vcvtm_s16_f16(a);
 283 }
 284
 285 // CHECK-LABEL: define {{[^@]+}}@test_vcvtmq_s16_f16
 286 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 287 // CHECK-NEXT:  entry:
 288 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 289 // CHECK-NEXT:    [[VCVTM1_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.fcvtms.v8i16.v8f16(<8 x half> [[A]])
 290 // CHECK-NEXT:    ret <8 x i16> [[VCVTM1_I]]
 291 //
 292 int16x8_t test_vcvtmq_s16_f16 (float16x8_t a) {
 293   return vcvtmq_s16_f16(a);
 294 }
 295
 296 // CHECK-LABEL: define {{[^@]+}}@test_vcvtm_u16_f16
 297 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 298 // CHECK-NEXT:  entry:
 299 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 300 // CHECK-NEXT:    [[VCVTM1_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtmu.v4i16.v4f16(<4 x half> [[A]])
 301 // CHECK-NEXT:    ret <4 x i16> [[VCVTM1_I]]
 302 //
 303 uint16x4_t test_vcvtm_u16_f16 (float16x4_t a) {
 304   return vcvtm_u16_f16(a);
 305 }
 306
 307 // CHECK-LABEL: define {{[^@]+}}@test_vcvtmq_u16_f16
 308 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 309 // CHECK-NEXT:  entry:
 310 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 311 // CHECK-NEXT:    [[VCVTM1_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.fcvtmu.v8i16.v8f16(<8 x half> [[A]])
 312 // CHECK-NEXT:    ret <8 x i16> [[VCVTM1_I]]
 313 //
 314 uint16x8_t test_vcvtmq_u16_f16 (float16x8_t a) {
 315   return vcvtmq_u16_f16(a);
 316 }
 317
 318 // CHECK-LABEL: define {{[^@]+}}@test_vcvtn_s16_f16
 319 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 320 // CHECK-NEXT:  entry:
 321 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 322 // CHECK-NEXT:    [[VCVTN1_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtns.v4i16.v4f16(<4 x half> [[A]])
 323 // CHECK-NEXT:    ret <4 x i16> [[VCVTN1_I]]
 324 //
 325 int16x4_t test_vcvtn_s16_f16 (float16x4_t a) {
 326   return vcvtn_s16_f16(a);
 327 }
 328
 329 // CHECK-LABEL: define {{[^@]+}}@test_vcvtnq_s16_f16
 330 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 331 // CHECK-NEXT:  entry:
 332 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 333 // CHECK-NEXT:    [[VCVTN1_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.fcvtns.v8i16.v8f16(<8 x half> [[A]])
 334 // CHECK-NEXT:    ret <8 x i16> [[VCVTN1_I]]
 335 //
 336 int16x8_t test_vcvtnq_s16_f16 (float16x8_t a) {
 337   return vcvtnq_s16_f16(a);
 338 }
 339
 340 // CHECK-LABEL: define {{[^@]+}}@test_vcvtn_u16_f16
 341 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 342 // CHECK-NEXT:  entry:
 343 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 344 // CHECK-NEXT:    [[VCVTN1_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtnu.v4i16.v4f16(<4 x half> [[A]])
 345 // CHECK-NEXT:    ret <4 x i16> [[VCVTN1_I]]
 346 //
 347 uint16x4_t test_vcvtn_u16_f16 (float16x4_t a) {
 348   return vcvtn_u16_f16(a);
 349 }
 350
 351 // CHECK-LABEL: define {{[^@]+}}@test_vcvtnq_u16_f16
 352 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 353 // CHECK-NEXT:  entry:
 354 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 355 // CHECK-NEXT:    [[VCVTN1_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.fcvtnu.v8i16.v8f16(<8 x half> [[A]])
 356 // CHECK-NEXT:    ret <8 x i16> [[VCVTN1_I]]
 357 //
 358 uint16x8_t test_vcvtnq_u16_f16 (float16x8_t a) {
 359   return vcvtnq_u16_f16(a);
 360 }
 361
 362 // CHECK-LABEL: define {{[^@]+}}@test_vcvtp_s16_f16
 363 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 364 // CHECK-NEXT:  entry:
 365 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 366 // CHECK-NEXT:    [[VCVTP1_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtps.v4i16.v4f16(<4 x half> [[A]])
 367 // CHECK-NEXT:    ret <4 x i16> [[VCVTP1_I]]
 368 //
 369 int16x4_t test_vcvtp_s16_f16 (float16x4_t a) {
 370   return vcvtp_s16_f16(a);
 371 }
 372
 373 // CHECK-LABEL: define {{[^@]+}}@test_vcvtpq_s16_f16
 374 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 375 // CHECK-NEXT:  entry:
 376 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 377 // CHECK-NEXT:    [[VCVTP1_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.fcvtps.v8i16.v8f16(<8 x half> [[A]])
 378 // CHECK-NEXT:    ret <8 x i16> [[VCVTP1_I]]
 379 //
 380 int16x8_t test_vcvtpq_s16_f16 (float16x8_t a) {
 381   return vcvtpq_s16_f16(a);
 382 }
 383
 384 // CHECK-LABEL: define {{[^@]+}}@test_vcvtp_u16_f16
 385 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 386 // CHECK-NEXT:  entry:
 387 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 388 // CHECK-NEXT:    [[VCVTP1_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtpu.v4i16.v4f16(<4 x half> [[A]])
 389 // CHECK-NEXT:    ret <4 x i16> [[VCVTP1_I]]
 390 //
 391 uint16x4_t test_vcvtp_u16_f16 (float16x4_t a) {
 392   return vcvtp_u16_f16(a);
 393 }
 394
 395 // CHECK-LABEL: define {{[^@]+}}@test_vcvtpq_u16_f16
 396 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 397 // CHECK-NEXT:  entry:
 398 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 399 // CHECK-NEXT:    [[VCVTP1_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.fcvtpu.v8i16.v8f16(<8 x half> [[A]])
 400 // CHECK-NEXT:    ret <8 x i16> [[VCVTP1_I]]
 401 //
 402 uint16x8_t test_vcvtpq_u16_f16 (float16x8_t a) {
 403   return vcvtpq_u16_f16(a);
 404 }
 405
 406 // FIXME: Fix the zero constant when fp16 non-storage-only type becomes available.
 407 // CHECK-LABEL: define {{[^@]+}}@test_vneg_f16
 408 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 409 // CHECK-NEXT:  entry:
 410 // CHECK-NEXT:    [[FNEG_I:%.*]] = fneg <4 x half> [[A]]
 411 // CHECK-NEXT:    ret <4 x half> [[FNEG_I]]
 412 //
 413 float16x4_t test_vneg_f16(float16x4_t a) {
 414   return vneg_f16(a);
 415 }
 416
 417 // CHECK-LABEL: define {{[^@]+}}@test_vnegq_f16
 418 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 419 // CHECK-NEXT:  entry:
 420 // CHECK-NEXT:    [[FNEG_I:%.*]] = fneg <8 x half> [[A]]
 421 // CHECK-NEXT:    ret <8 x half> [[FNEG_I]]
 422 //
 423 float16x8_t test_vnegq_f16(float16x8_t a) {
 424   return vnegq_f16(a);
 425 }
 426
 427 // CHECK-LABEL: define {{[^@]+}}@test_vrecpe_f16
 428 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 429 // CHECK-NEXT:  entry:
 430 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 431 // CHECK-NEXT:    [[VRECPE_V1_I:%.*]] = call <4 x half> @llvm.aarch64.neon.frecpe.v4f16(<4 x half> [[A]])
 432 // CHECK-NEXT:    ret <4 x half> [[VRECPE_V1_I]]
 433 //
 434 float16x4_t test_vrecpe_f16(float16x4_t a) {
 435   return vrecpe_f16(a);
 436 }
 437
 438 // CHECK-LABEL: define {{[^@]+}}@test_vrecpeq_f16
 439 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 440 // CHECK-NEXT:  entry:
 441 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 442 // CHECK-NEXT:    [[VRECPEQ_V1_I:%.*]] = call <8 x half> @llvm.aarch64.neon.frecpe.v8f16(<8 x half> [[A]])
 443 // CHECK-NEXT:    ret <8 x half> [[VRECPEQ_V1_I]]
 444 //
 445 float16x8_t test_vrecpeq_f16(float16x8_t a) {
 446   return vrecpeq_f16(a);
 447 }
 448
 449 // CHECK-LABEL: define {{[^@]+}}@test_vrnd_f16
 450 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 451 // CHECK-NEXT:  entry:
 452 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 453 // CHECK-NEXT:    [[VRNDZ1_I:%.*]] = call <4 x half> @llvm.trunc.v4f16(<4 x half> [[A]])
 454 // CHECK-NEXT:    ret <4 x half> [[VRNDZ1_I]]
 455 //
 456 float16x4_t test_vrnd_f16(float16x4_t a) {
 457   return vrnd_f16(a);
 458 }
 459
 460 // CHECK-LABEL: define {{[^@]+}}@test_vrndq_f16
 461 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 462 // CHECK-NEXT:  entry:
 463 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 464 // CHECK-NEXT:    [[VRNDZ1_I:%.*]] = call <8 x half> @llvm.trunc.v8f16(<8 x half> [[A]])
 465 // CHECK-NEXT:    ret <8 x half> [[VRNDZ1_I]]
 466 //
 467 float16x8_t test_vrndq_f16(float16x8_t a) {
 468   return vrndq_f16(a);
 469 }
 470
 471 // CHECK-LABEL: define {{[^@]+}}@test_vrnda_f16
 472 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 473 // CHECK-NEXT:  entry:
 474 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 475 // CHECK-NEXT:    [[VRNDA1_I:%.*]] = call <4 x half> @llvm.round.v4f16(<4 x half> [[A]])
 476 // CHECK-NEXT:    ret <4 x half> [[VRNDA1_I]]
 477 //
 478 float16x4_t test_vrnda_f16(float16x4_t a) {
 479   return vrnda_f16(a);
 480 }
 481
 482 // CHECK-LABEL: define {{[^@]+}}@test_vrndaq_f16
 483 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 484 // CHECK-NEXT:  entry:
 485 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 486 // CHECK-NEXT:    [[VRNDA1_I:%.*]] = call <8 x half> @llvm.round.v8f16(<8 x half> [[A]])
 487 // CHECK-NEXT:    ret <8 x half> [[VRNDA1_I]]
 488 //
 489 float16x8_t test_vrndaq_f16(float16x8_t a) {
 490   return vrndaq_f16(a);
 491 }
 492
 493 // CHECK-LABEL: define {{[^@]+}}@test_vrndi_f16
 494 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 495 // CHECK-NEXT:  entry:
 496 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 497 // CHECK-NEXT:    [[VRNDI_V1_I:%.*]] = call <4 x half> @llvm.nearbyint.v4f16(<4 x half> [[A]])
 498 // CHECK-NEXT:    ret <4 x half> [[VRNDI_V1_I]]
 499 //
 500 float16x4_t test_vrndi_f16(float16x4_t a) {
 501   return vrndi_f16(a);
 502 }
 503
 504 // CHECK-LABEL: define {{[^@]+}}@test_vrndiq_f16
 505 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 506 // CHECK-NEXT:  entry:
 507 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 508 // CHECK-NEXT:    [[VRNDIQ_V1_I:%.*]] = call <8 x half> @llvm.nearbyint.v8f16(<8 x half> [[A]])
 509 // CHECK-NEXT:    ret <8 x half> [[VRNDIQ_V1_I]]
 510 //
 511 float16x8_t test_vrndiq_f16(float16x8_t a) {
 512   return vrndiq_f16(a);
 513 }
 514
 515 // CHECK-LABEL: define {{[^@]+}}@test_vrndm_f16
 516 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 517 // CHECK-NEXT:  entry:
 518 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 519 // CHECK-NEXT:    [[VRNDM1_I:%.*]] = call <4 x half> @llvm.floor.v4f16(<4 x half> [[A]])
 520 // CHECK-NEXT:    ret <4 x half> [[VRNDM1_I]]
 521 //
 522 float16x4_t test_vrndm_f16(float16x4_t a) {
 523   return vrndm_f16(a);
 524 }
 525
 526 // CHECK-LABEL: define {{[^@]+}}@test_vrndmq_f16
 527 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 528 // CHECK-NEXT:  entry:
 529 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 530 // CHECK-NEXT:    [[VRNDM1_I:%.*]] = call <8 x half> @llvm.floor.v8f16(<8 x half> [[A]])
 531 // CHECK-NEXT:    ret <8 x half> [[VRNDM1_I]]
 532 //
 533 float16x8_t test_vrndmq_f16(float16x8_t a) {
 534   return vrndmq_f16(a);
 535 }
 536
 537 // CHECK-LABEL: define {{[^@]+}}@test_vrndn_f16
 538 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 539 // CHECK-NEXT:  entry:
 540 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 541 // CHECK-NEXT:    [[VRNDN1_I:%.*]] = call <4 x half> @llvm.roundeven.v4f16(<4 x half> [[A]])
 542 // CHECK-NEXT:    ret <4 x half> [[VRNDN1_I]]
 543 //
 544 float16x4_t test_vrndn_f16(float16x4_t a) {
 545   return vrndn_f16(a);
 546 }
 547
 548 // CHECK-LABEL: define {{[^@]+}}@test_vrndnq_f16
 549 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 550 // CHECK-NEXT:  entry:
 551 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 552 // CHECK-NEXT:    [[VRNDN1_I:%.*]] = call <8 x half> @llvm.roundeven.v8f16(<8 x half> [[A]])
 553 // CHECK-NEXT:    ret <8 x half> [[VRNDN1_I]]
 554 //
 555 float16x8_t test_vrndnq_f16(float16x8_t a) {
 556   return vrndnq_f16(a);
 557 }
 558
 559 // CHECK-LABEL: define {{[^@]+}}@test_vrndp_f16
 560 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 561 // CHECK-NEXT:  entry:
 562 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 563 // CHECK-NEXT:    [[VRNDP1_I:%.*]] = call <4 x half> @llvm.ceil.v4f16(<4 x half> [[A]])
 564 // CHECK-NEXT:    ret <4 x half> [[VRNDP1_I]]
 565 //
 566 float16x4_t test_vrndp_f16(float16x4_t a) {
 567   return vrndp_f16(a);
 568 }
 569
 570 // CHECK-LABEL: define {{[^@]+}}@test_vrndpq_f16
 571 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 572 // CHECK-NEXT:  entry:
 573 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 574 // CHECK-NEXT:    [[VRNDP1_I:%.*]] = call <8 x half> @llvm.ceil.v8f16(<8 x half> [[A]])
 575 // CHECK-NEXT:    ret <8 x half> [[VRNDP1_I]]
 576 //
 577 float16x8_t test_vrndpq_f16(float16x8_t a) {
 578   return vrndpq_f16(a);
 579 }
 580
 581 // CHECK-LABEL: define {{[^@]+}}@test_vrndx_f16
 582 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 583 // CHECK-NEXT:  entry:
 584 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 585 // CHECK-NEXT:    [[VRNDX1_I:%.*]] = call <4 x half> @llvm.rint.v4f16(<4 x half> [[A]])
 586 // CHECK-NEXT:    ret <4 x half> [[VRNDX1_I]]
 587 //
 588 float16x4_t test_vrndx_f16(float16x4_t a) {
 589   return vrndx_f16(a);
 590 }
 591
 592 // CHECK-LABEL: define {{[^@]+}}@test_vrndxq_f16
 593 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 594 // CHECK-NEXT:  entry:
 595 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 596 // CHECK-NEXT:    [[VRNDX1_I:%.*]] = call <8 x half> @llvm.rint.v8f16(<8 x half> [[A]])
 597 // CHECK-NEXT:    ret <8 x half> [[VRNDX1_I]]
 598 //
 599 float16x8_t test_vrndxq_f16(float16x8_t a) {
 600   return vrndxq_f16(a);
 601 }
 602
 603 // CHECK-LABEL: define {{[^@]+}}@test_vrsqrte_f16
 604 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 605 // CHECK-NEXT:  entry:
 606 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 607 // CHECK-NEXT:    [[VRSQRTE_V1_I:%.*]] = call <4 x half> @llvm.aarch64.neon.frsqrte.v4f16(<4 x half> [[A]])
 608 // CHECK-NEXT:    ret <4 x half> [[VRSQRTE_V1_I]]
 609 //
 610 float16x4_t test_vrsqrte_f16(float16x4_t a) {
 611   return vrsqrte_f16(a);
 612 }
 613
 614 // CHECK-LABEL: define {{[^@]+}}@test_vrsqrteq_f16
 615 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 616 // CHECK-NEXT:  entry:
 617 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 618 // CHECK-NEXT:    [[VRSQRTEQ_V1_I:%.*]] = call <8 x half> @llvm.aarch64.neon.frsqrte.v8f16(<8 x half> [[A]])
 619 // CHECK-NEXT:    ret <8 x half> [[VRSQRTEQ_V1_I]]
 620 //
 621 float16x8_t test_vrsqrteq_f16(float16x8_t a) {
 622   return vrsqrteq_f16(a);
 623 }
 624
 625 // CHECK-LABEL: define {{[^@]+}}@test_vsqrt_f16
 626 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 627 // CHECK-NEXT:  entry:
 628 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 629 // CHECK-NEXT:    [[VSQRT_I:%.*]] = call <4 x half> @llvm.sqrt.v4f16(<4 x half> [[A]])
 630 // CHECK-NEXT:    ret <4 x half> [[VSQRT_I]]
 631 //
 632 float16x4_t test_vsqrt_f16(float16x4_t a) {
 633   return vsqrt_f16(a);
 634 }
 635
 636 // CHECK-LABEL: define {{[^@]+}}@test_vsqrtq_f16
 637 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 638 // CHECK-NEXT:  entry:
 639 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 640 // CHECK-NEXT:    [[VSQRT_I:%.*]] = call <8 x half> @llvm.sqrt.v8f16(<8 x half> [[A]])
 641 // CHECK-NEXT:    ret <8 x half> [[VSQRT_I]]
 642 //
 643 float16x8_t test_vsqrtq_f16(float16x8_t a) {
 644   return vsqrtq_f16(a);
 645 }
 646
 647 // CHECK-LABEL: define {{[^@]+}}@test_vadd_f16
 648 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
 649 // CHECK-NEXT:  entry:
 650 // CHECK-NEXT:    [[ADD_I:%.*]] = fadd <4 x half> [[A]], [[B]]
 651 // CHECK-NEXT:    ret <4 x half> [[ADD_I]]
 652 //
 653 float16x4_t test_vadd_f16(float16x4_t a, float16x4_t b) {
 654   return vadd_f16(a, b);
 655 }
 656
 657 // CHECK-LABEL: define {{[^@]+}}@test_vaddq_f16
 658 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
 659 // CHECK-NEXT:  entry:
 660 // CHECK-NEXT:    [[ADD_I:%.*]] = fadd <8 x half> [[A]], [[B]]
 661 // CHECK-NEXT:    ret <8 x half> [[ADD_I]]
 662 //
 663 float16x8_t test_vaddq_f16(float16x8_t a, float16x8_t b) {
 664   return vaddq_f16(a, b);
 665 }
 666
 667 // CHECK-LABEL: define {{[^@]+}}@test_vabd_f16
 668 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
 669 // CHECK-NEXT:  entry:
 670 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 671 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[B]] to <8 x i8>
 672 // CHECK-NEXT:    [[VABD2_I:%.*]] = call <4 x half> @llvm.aarch64.neon.fabd.v4f16(<4 x half> [[A]], <4 x half> [[B]])
 673 // CHECK-NEXT:    ret <4 x half> [[VABD2_I]]
 674 //
 675 float16x4_t test_vabd_f16(float16x4_t a, float16x4_t b) {
 676   return vabd_f16(a, b);
 677 }
 678
 679 // CHECK-LABEL: define {{[^@]+}}@test_vabdq_f16
 680 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
 681 // CHECK-NEXT:  entry:
 682 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 683 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[B]] to <16 x i8>
 684 // CHECK-NEXT:    [[VABD2_I:%.*]] = call <8 x half> @llvm.aarch64.neon.fabd.v8f16(<8 x half> [[A]], <8 x half> [[B]])
 685 // CHECK-NEXT:    ret <8 x half> [[VABD2_I]]
 686 //
 687 float16x8_t test_vabdq_f16(float16x8_t a, float16x8_t b) {
 688   return vabdq_f16(a, b);
 689 }
 690
 691 // CHECK-LABEL: define {{[^@]+}}@test_vcage_f16
 692 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
 693 // CHECK-NEXT:  entry:
 694 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 695 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[B]] to <8 x i8>
 696 // CHECK-NEXT:    [[VCAGE_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.facge.v4i16.v4f16(<4 x half> [[A]], <4 x half> [[B]])
 697 // CHECK-NEXT:    ret <4 x i16> [[VCAGE_V2_I]]
 698 //
 699 uint16x4_t test_vcage_f16(float16x4_t a, float16x4_t b) {
 700   return vcage_f16(a, b);
 701 }
 702
 703 // CHECK-LABEL: define {{[^@]+}}@test_vcageq_f16
 704 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
 705 // CHECK-NEXT:  entry:
 706 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 707 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[B]] to <16 x i8>
 708 // CHECK-NEXT:    [[VCAGEQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.facge.v8i16.v8f16(<8 x half> [[A]], <8 x half> [[B]])
 709 // CHECK-NEXT:    ret <8 x i16> [[VCAGEQ_V2_I]]
 710 //
 711 uint16x8_t test_vcageq_f16(float16x8_t a, float16x8_t b) {
 712   return vcageq_f16(a, b);
 713 }
 714
 715 // CHECK-LABEL: define {{[^@]+}}@test_vcagt_f16
 716 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
 717 // CHECK-NEXT:  entry:
 718 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 719 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[B]] to <8 x i8>
 720 // CHECK-NEXT:    [[VCAGT_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.facgt.v4i16.v4f16(<4 x half> [[A]], <4 x half> [[B]])
 721 // CHECK-NEXT:    ret <4 x i16> [[VCAGT_V2_I]]
 722 //
 723 uint16x4_t test_vcagt_f16(float16x4_t a, float16x4_t b) {
 724   return vcagt_f16(a, b);
 725 }
 726
 727 // CHECK-LABEL: define {{[^@]+}}@test_vcagtq_f16
 728 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
 729 // CHECK-NEXT:  entry:
 730 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 731 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[B]] to <16 x i8>
 732 // CHECK-NEXT:    [[VCAGTQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.facgt.v8i16.v8f16(<8 x half> [[A]], <8 x half> [[B]])
 733 // CHECK-NEXT:    ret <8 x i16> [[VCAGTQ_V2_I]]
 734 //
 735 uint16x8_t test_vcagtq_f16(float16x8_t a, float16x8_t b) {
 736   return vcagtq_f16(a, b);
 737 }
 738
 739 // CHECK-LABEL: define {{[^@]+}}@test_vcale_f16
 740 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
 741 // CHECK-NEXT:  entry:
 742 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 743 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[B]] to <8 x i8>
 744 // CHECK-NEXT:    [[VCALE_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.facge.v4i16.v4f16(<4 x half> [[B]], <4 x half> [[A]])
 745 // CHECK-NEXT:    ret <4 x i16> [[VCALE_V2_I]]
 746 //
 747 uint16x4_t test_vcale_f16(float16x4_t a, float16x4_t b) {
 748   return vcale_f16(a, b);
 749 }
 750
 751 // CHECK-LABEL: define {{[^@]+}}@test_vcaleq_f16
 752 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
 753 // CHECK-NEXT:  entry:
 754 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 755 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[B]] to <16 x i8>
 756 // CHECK-NEXT:    [[VCALEQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.facge.v8i16.v8f16(<8 x half> [[B]], <8 x half> [[A]])
 757 // CHECK-NEXT:    ret <8 x i16> [[VCALEQ_V2_I]]
 758 //
 759 uint16x8_t test_vcaleq_f16(float16x8_t a, float16x8_t b) {
 760   return vcaleq_f16(a, b);
 761 }
 762
 763 // CHECK-LABEL: define {{[^@]+}}@test_vcalt_f16
 764 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
 765 // CHECK-NEXT:  entry:
 766 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 767 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[B]] to <8 x i8>
 768 // CHECK-NEXT:    [[VCALT_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.facgt.v4i16.v4f16(<4 x half> [[B]], <4 x half> [[A]])
 769 // CHECK-NEXT:    ret <4 x i16> [[VCALT_V2_I]]
 770 //
 771 uint16x4_t test_vcalt_f16(float16x4_t a, float16x4_t b) {
 772   return vcalt_f16(a, b);
 773 }
 774
 775 // CHECK-LABEL: define {{[^@]+}}@test_vcaltq_f16
 776 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
 777 // CHECK-NEXT:  entry:
 778 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 779 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[B]] to <16 x i8>
 780 // CHECK-NEXT:    [[VCALTQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.facgt.v8i16.v8f16(<8 x half> [[B]], <8 x half> [[A]])
 781 // CHECK-NEXT:    ret <8 x i16> [[VCALTQ_V2_I]]
 782 //
 783 uint16x8_t test_vcaltq_f16(float16x8_t a, float16x8_t b) {
 784   return vcaltq_f16(a, b);
 785 }
 786
 787 // CHECK-LABEL: define {{[^@]+}}@test_vceq_f16
 788 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
 789 // CHECK-NEXT:  entry:
 790 // CHECK-NEXT:    [[CMP_I:%.*]] = fcmp oeq <4 x half> [[A]], [[B]]
 791 // CHECK-NEXT:    [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
 792 // CHECK-NEXT:    ret <4 x i16> [[SEXT_I]]
 793 //
 794 uint16x4_t test_vceq_f16(float16x4_t a, float16x4_t b) {
 795   return vceq_f16(a, b);
 796 }
 797
 798 // CHECK-LABEL: define {{[^@]+}}@test_vceqq_f16
 799 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
 800 // CHECK-NEXT:  entry:
 801 // CHECK-NEXT:    [[CMP_I:%.*]] = fcmp oeq <8 x half> [[A]], [[B]]
 802 // CHECK-NEXT:    [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i16>
 803 // CHECK-NEXT:    ret <8 x i16> [[SEXT_I]]
 804 //
 805 uint16x8_t test_vceqq_f16(float16x8_t a, float16x8_t b) {
 806   return vceqq_f16(a, b);
 807 }
 808
 809 // CHECK-LABEL: define {{[^@]+}}@test_vcge_f16
 810 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
 811 // CHECK-NEXT:  entry:
 812 // CHECK-NEXT:    [[CMP_I:%.*]] = fcmp oge <4 x half> [[A]], [[B]]
 813 // CHECK-NEXT:    [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
 814 // CHECK-NEXT:    ret <4 x i16> [[SEXT_I]]
 815 //
 816 uint16x4_t test_vcge_f16(float16x4_t a, float16x4_t b) {
 817   return vcge_f16(a, b);
 818 }
 819
 820 // CHECK-LABEL: define {{[^@]+}}@test_vcgeq_f16
 821 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
 822 // CHECK-NEXT:  entry:
 823 // CHECK-NEXT:    [[CMP_I:%.*]] = fcmp oge <8 x half> [[A]], [[B]]
 824 // CHECK-NEXT:    [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i16>
 825 // CHECK-NEXT:    ret <8 x i16> [[SEXT_I]]
 826 //
 827 uint16x8_t test_vcgeq_f16(float16x8_t a, float16x8_t b) {
 828   return vcgeq_f16(a, b);
 829 }
 830
 831 // CHECK-LABEL: define {{[^@]+}}@test_vcgt_f16
 832 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
 833 // CHECK-NEXT:  entry:
 834 // CHECK-NEXT:    [[CMP_I:%.*]] = fcmp ogt <4 x half> [[A]], [[B]]
 835 // CHECK-NEXT:    [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
 836 // CHECK-NEXT:    ret <4 x i16> [[SEXT_I]]
 837 //
 838 uint16x4_t test_vcgt_f16(float16x4_t a, float16x4_t b) {
 839   return vcgt_f16(a, b);
 840 }
 841
 842 // CHECK-LABEL: define {{[^@]+}}@test_vcgtq_f16
 843 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
 844 // CHECK-NEXT:  entry:
 845 // CHECK-NEXT:    [[CMP_I:%.*]] = fcmp ogt <8 x half> [[A]], [[B]]
 846 // CHECK-NEXT:    [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i16>
 847 // CHECK-NEXT:    ret <8 x i16> [[SEXT_I]]
 848 //
 849 uint16x8_t test_vcgtq_f16(float16x8_t a, float16x8_t b) {
 850   return vcgtq_f16(a, b);
 851 }
 852
 853 // CHECK-LABEL: define {{[^@]+}}@test_vcle_f16
 854 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
 855 // CHECK-NEXT:  entry:
 856 // CHECK-NEXT:    [[CMP_I:%.*]] = fcmp ole <4 x half> [[A]], [[B]]
 857 // CHECK-NEXT:    [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
 858 // CHECK-NEXT:    ret <4 x i16> [[SEXT_I]]
 859 //
 860 uint16x4_t test_vcle_f16(float16x4_t a, float16x4_t b) {
 861   return vcle_f16(a, b);
 862 }
 863
 864 // CHECK-LABEL: define {{[^@]+}}@test_vcleq_f16
 865 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
 866 // CHECK-NEXT:  entry:
 867 // CHECK-NEXT:    [[CMP_I:%.*]] = fcmp ole <8 x half> [[A]], [[B]]
 868 // CHECK-NEXT:    [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i16>
 869 // CHECK-NEXT:    ret <8 x i16> [[SEXT_I]]
 870 //
 871 uint16x8_t test_vcleq_f16(float16x8_t a, float16x8_t b) {
 872   return vcleq_f16(a, b);
 873 }
 874
 875 // CHECK-LABEL: define {{[^@]+}}@test_vclt_f16
 876 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
 877 // CHECK-NEXT:  entry:
 878 // CHECK-NEXT:    [[CMP_I:%.*]] = fcmp olt <4 x half> [[A]], [[B]]
 879 // CHECK-NEXT:    [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
 880 // CHECK-NEXT:    ret <4 x i16> [[SEXT_I]]
 881 //
 882 uint16x4_t test_vclt_f16(float16x4_t a, float16x4_t b) {
 883   return vclt_f16(a, b);
 884 }
 885
 886 // CHECK-LABEL: define {{[^@]+}}@test_vcltq_f16
 887 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
 888 // CHECK-NEXT:  entry:
 889 // CHECK-NEXT:    [[CMP_I:%.*]] = fcmp olt <8 x half> [[A]], [[B]]
 890 // CHECK-NEXT:    [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i16>
 891 // CHECK-NEXT:    ret <8 x i16> [[SEXT_I]]
 892 //
 893 uint16x8_t test_vcltq_f16(float16x8_t a, float16x8_t b) {
 894   return vcltq_f16(a, b);
 895 }
 896
 897 // CHECK-LABEL: define {{[^@]+}}@test_vcvt_n_f16_s16
 898 // CHECK-SAME: (<4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
 899 // CHECK-NEXT:  entry:
 900 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
 901 // CHECK-NEXT:    [[VCVT_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
 902 // CHECK-NEXT:    [[VCVT_N1:%.*]] = call <4 x half> @llvm.aarch64.neon.vcvtfxs2fp.v4f16.v4i16(<4 x i16> [[VCVT_N]], i32 2)
 903 // CHECK-NEXT:    ret <4 x half> [[VCVT_N1]]
 904 //
 905 float16x4_t test_vcvt_n_f16_s16(int16x4_t a) {
 906   return vcvt_n_f16_s16(a, 2);
 907 }
 908
 909 // CHECK-LABEL: define {{[^@]+}}@test_vcvtq_n_f16_s16
 910 // CHECK-SAME: (<8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
 911 // CHECK-NEXT:  entry:
 912 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
 913 // CHECK-NEXT:    [[VCVT_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
 914 // CHECK-NEXT:    [[VCVT_N1:%.*]] = call <8 x half> @llvm.aarch64.neon.vcvtfxs2fp.v8f16.v8i16(<8 x i16> [[VCVT_N]], i32 2)
 915 // CHECK-NEXT:    ret <8 x half> [[VCVT_N1]]
 916 //
 917 float16x8_t test_vcvtq_n_f16_s16(int16x8_t a) {
 918   return vcvtq_n_f16_s16(a, 2);
 919 }
 920
 921 // CHECK-LABEL: define {{[^@]+}}@test_vcvt_n_f16_u16
 922 // CHECK-SAME: (<4 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
 923 // CHECK-NEXT:  entry:
 924 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
 925 // CHECK-NEXT:    [[VCVT_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
 926 // CHECK-NEXT:    [[VCVT_N1:%.*]] = call <4 x half> @llvm.aarch64.neon.vcvtfxu2fp.v4f16.v4i16(<4 x i16> [[VCVT_N]], i32 2)
 927 // CHECK-NEXT:    ret <4 x half> [[VCVT_N1]]
 928 //
 929 float16x4_t test_vcvt_n_f16_u16(uint16x4_t a) {
 930   return vcvt_n_f16_u16(a, 2);
 931 }
 932
 933 // CHECK-LABEL: define {{[^@]+}}@test_vcvtq_n_f16_u16
 934 // CHECK-SAME: (<8 x i16> noundef [[A:%.*]]) #[[ATTR0]] {
 935 // CHECK-NEXT:  entry:
 936 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
 937 // CHECK-NEXT:    [[VCVT_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
 938 // CHECK-NEXT:    [[VCVT_N1:%.*]] = call <8 x half> @llvm.aarch64.neon.vcvtfxu2fp.v8f16.v8i16(<8 x i16> [[VCVT_N]], i32 2)
 939 // CHECK-NEXT:    ret <8 x half> [[VCVT_N1]]
 940 //
 941 float16x8_t test_vcvtq_n_f16_u16(uint16x8_t a) {
 942   return vcvtq_n_f16_u16(a, 2);
 943 }
 944
 945 // CHECK-LABEL: define {{[^@]+}}@test_vcvt_n_s16_f16
 946 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 947 // CHECK-NEXT:  entry:
 948 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 949 // CHECK-NEXT:    [[VCVT_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>
 950 // CHECK-NEXT:    [[VCVT_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.vcvtfp2fxs.v4i16.v4f16(<4 x half> [[VCVT_N]], i32 2)
 951 // CHECK-NEXT:    ret <4 x i16> [[VCVT_N1]]
 952 //
 953 int16x4_t test_vcvt_n_s16_f16(float16x4_t a) {
 954   return vcvt_n_s16_f16(a, 2);
 955 }
 956
 957 // CHECK-LABEL: define {{[^@]+}}@test_vcvtq_n_s16_f16
 958 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 959 // CHECK-NEXT:  entry:
 960 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 961 // CHECK-NEXT:    [[VCVT_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>
 962 // CHECK-NEXT:    [[VCVT_N1:%.*]] = call <8 x i16> @llvm.aarch64.neon.vcvtfp2fxs.v8i16.v8f16(<8 x half> [[VCVT_N]], i32 2)
 963 // CHECK-NEXT:    ret <8 x i16> [[VCVT_N1]]
 964 //
 965 int16x8_t test_vcvtq_n_s16_f16(float16x8_t a) {
 966   return vcvtq_n_s16_f16(a, 2);
 967 }
 968
 969 // CHECK-LABEL: define {{[^@]+}}@test_vcvt_n_u16_f16
 970 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 971 // CHECK-NEXT:  entry:
 972 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
 973 // CHECK-NEXT:    [[VCVT_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>
 974 // CHECK-NEXT:    [[VCVT_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.vcvtfp2fxu.v4i16.v4f16(<4 x half> [[VCVT_N]], i32 2)
 975 // CHECK-NEXT:    ret <4 x i16> [[VCVT_N1]]
 976 //
 977 uint16x4_t test_vcvt_n_u16_f16(float16x4_t a) {
 978   return vcvt_n_u16_f16(a, 2);
 979 }
 980
 981 // CHECK-LABEL: define {{[^@]+}}@test_vcvtq_n_u16_f16
 982 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
 983 // CHECK-NEXT:  entry:
 984 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
 985 // CHECK-NEXT:    [[VCVT_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>
 986 // CHECK-NEXT:    [[VCVT_N1:%.*]] = call <8 x i16> @llvm.aarch64.neon.vcvtfp2fxu.v8i16.v8f16(<8 x half> [[VCVT_N]], i32 2)
 987 // CHECK-NEXT:    ret <8 x i16> [[VCVT_N1]]
 988 //
 989 uint16x8_t test_vcvtq_n_u16_f16(float16x8_t a) {
 990   return vcvtq_n_u16_f16(a, 2);
 991 }
 992
 993 // CHECK-LABEL: define {{[^@]+}}@test_vdiv_f16
 994 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
 995 // CHECK-NEXT:  entry:
 996 // CHECK-NEXT:    [[DIV_I:%.*]] = fdiv <4 x half> [[A]], [[B]]
 997 // CHECK-NEXT:    ret <4 x half> [[DIV_I]]
 998 //
 999 float16x4_t test_vdiv_f16(float16x4_t a, float16x4_t b) {
1000   return vdiv_f16(a, b);
1001 }
1002
1003 // CHECK-LABEL: define {{[^@]+}}@test_vdivq_f16
1004 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1005 // CHECK-NEXT:  entry:
1006 // CHECK-NEXT:    [[DIV_I:%.*]] = fdiv <8 x half> [[A]], [[B]]
1007 // CHECK-NEXT:    ret <8 x half> [[DIV_I]]
1008 //
1009 float16x8_t test_vdivq_f16(float16x8_t a, float16x8_t b) {
1010   return vdivq_f16(a, b);
1011 }
1012
1013 // CHECK-LABEL: define {{[^@]+}}@test_vmax_f16
1014 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1015 // CHECK-NEXT:  entry:
1016 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1017 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[B]] to <8 x i8>
1018 // CHECK-NEXT:    [[VMAX2_I:%.*]] = call <4 x half> @llvm.aarch64.neon.fmax.v4f16(<4 x half> [[A]], <4 x half> [[B]])
1019 // CHECK-NEXT:    ret <4 x half> [[VMAX2_I]]
1020 //
1021 float16x4_t test_vmax_f16(float16x4_t a, float16x4_t b) {
1022   return vmax_f16(a, b);
1023 }
1024
1025 // CHECK-LABEL: define {{[^@]+}}@test_vmaxq_f16
1026 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1027 // CHECK-NEXT:  entry:
1028 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1029 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[B]] to <16 x i8>
1030 // CHECK-NEXT:    [[VMAX2_I:%.*]] = call <8 x half> @llvm.aarch64.neon.fmax.v8f16(<8 x half> [[A]], <8 x half> [[B]])
1031 // CHECK-NEXT:    ret <8 x half> [[VMAX2_I]]
1032 //
1033 float16x8_t test_vmaxq_f16(float16x8_t a, float16x8_t b) {
1034   return vmaxq_f16(a, b);
1035 }
1036
1037 // CHECK-LABEL: define {{[^@]+}}@test_vmaxnm_f16
1038 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1039 // CHECK-NEXT:  entry:
1040 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1041 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[B]] to <8 x i8>
1042 // CHECK-NEXT:    [[VMAXNM2_I:%.*]] = call <4 x half> @llvm.aarch64.neon.fmaxnm.v4f16(<4 x half> [[A]], <4 x half> [[B]])
1043 // CHECK-NEXT:    ret <4 x half> [[VMAXNM2_I]]
1044 //
1045 float16x4_t test_vmaxnm_f16(float16x4_t a, float16x4_t b) {
1046   return vmaxnm_f16(a, b);
1047 }
1048
1049 // CHECK-LABEL: define {{[^@]+}}@test_vmaxnmq_f16
1050 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1051 // CHECK-NEXT:  entry:
1052 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1053 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[B]] to <16 x i8>
1054 // CHECK-NEXT:    [[VMAXNM2_I:%.*]] = call <8 x half> @llvm.aarch64.neon.fmaxnm.v8f16(<8 x half> [[A]], <8 x half> [[B]])
1055 // CHECK-NEXT:    ret <8 x half> [[VMAXNM2_I]]
1056 //
1057 float16x8_t test_vmaxnmq_f16(float16x8_t a, float16x8_t b) {
1058   return vmaxnmq_f16(a, b);
1059 }
1060
1061 // CHECK-LABEL: define {{[^@]+}}@test_vmin_f16
1062 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1063 // CHECK-NEXT:  entry:
1064 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1065 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[B]] to <8 x i8>
1066 // CHECK-NEXT:    [[VMIN2_I:%.*]] = call <4 x half> @llvm.aarch64.neon.fmin.v4f16(<4 x half> [[A]], <4 x half> [[B]])
1067 // CHECK-NEXT:    ret <4 x half> [[VMIN2_I]]
1068 //
1069 float16x4_t test_vmin_f16(float16x4_t a, float16x4_t b) {
1070   return vmin_f16(a, b);
1071 }
1072
1073 // CHECK-LABEL: define {{[^@]+}}@test_vminq_f16
1074 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1075 // CHECK-NEXT:  entry:
1076 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1077 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[B]] to <16 x i8>
1078 // CHECK-NEXT:    [[VMIN2_I:%.*]] = call <8 x half> @llvm.aarch64.neon.fmin.v8f16(<8 x half> [[A]], <8 x half> [[B]])
1079 // CHECK-NEXT:    ret <8 x half> [[VMIN2_I]]
1080 //
1081 float16x8_t test_vminq_f16(float16x8_t a, float16x8_t b) {
1082   return vminq_f16(a, b);
1083 }
1084
1085 // CHECK-LABEL: define {{[^@]+}}@test_vminnm_f16
1086 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1087 // CHECK-NEXT:  entry:
1088 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1089 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[B]] to <8 x i8>
1090 // CHECK-NEXT:    [[VMINNM2_I:%.*]] = call <4 x half> @llvm.aarch64.neon.fminnm.v4f16(<4 x half> [[A]], <4 x half> [[B]])
1091 // CHECK-NEXT:    ret <4 x half> [[VMINNM2_I]]
1092 //
1093 float16x4_t test_vminnm_f16(float16x4_t a, float16x4_t b) {
1094   return vminnm_f16(a, b);
1095 }
1096
1097 // CHECK-LABEL: define {{[^@]+}}@test_vminnmq_f16
1098 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1099 // CHECK-NEXT:  entry:
1100 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1101 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[B]] to <16 x i8>
1102 // CHECK-NEXT:    [[VMINNM2_I:%.*]] = call <8 x half> @llvm.aarch64.neon.fminnm.v8f16(<8 x half> [[A]], <8 x half> [[B]])
1103 // CHECK-NEXT:    ret <8 x half> [[VMINNM2_I]]
1104 //
1105 float16x8_t test_vminnmq_f16(float16x8_t a, float16x8_t b) {
1106   return vminnmq_f16(a, b);
1107 }
1108
1109 // CHECK-LABEL: define {{[^@]+}}@test_vmul_f16
1110 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1111 // CHECK-NEXT:  entry:
1112 // CHECK-NEXT:    [[MUL_I:%.*]] = fmul <4 x half> [[A]], [[B]]
1113 // CHECK-NEXT:    ret <4 x half> [[MUL_I]]
1114 //
1115 float16x4_t test_vmul_f16(float16x4_t a, float16x4_t b) {
1116   return vmul_f16(a, b);
1117 }
1118
1119 // CHECK-LABEL: define {{[^@]+}}@test_vmulq_f16
1120 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1121 // CHECK-NEXT:  entry:
1122 // CHECK-NEXT:    [[MUL_I:%.*]] = fmul <8 x half> [[A]], [[B]]
1123 // CHECK-NEXT:    ret <8 x half> [[MUL_I]]
1124 //
1125 float16x8_t test_vmulq_f16(float16x8_t a, float16x8_t b) {
1126   return vmulq_f16(a, b);
1127 }
1128
1129 // CHECK-LABEL: define {{[^@]+}}@test_vmulx_f16
1130 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1131 // CHECK-NEXT:  entry:
1132 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1133 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[B]] to <8 x i8>
1134 // CHECK-NEXT:    [[VMULX2_I:%.*]] = call <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half> [[A]], <4 x half> [[B]])
1135 // CHECK-NEXT:    ret <4 x half> [[VMULX2_I]]
1136 //
1137 float16x4_t test_vmulx_f16(float16x4_t a, float16x4_t b) {
1138   return vmulx_f16(a, b);
1139 }
1140
1141 // CHECK-LABEL: define {{[^@]+}}@test_vmulxq_f16
1142 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1143 // CHECK-NEXT:  entry:
1144 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1145 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[B]] to <16 x i8>
1146 // CHECK-NEXT:    [[VMULX2_I:%.*]] = call <8 x half> @llvm.aarch64.neon.fmulx.v8f16(<8 x half> [[A]], <8 x half> [[B]])
1147 // CHECK-NEXT:    ret <8 x half> [[VMULX2_I]]
1148 //
1149 float16x8_t test_vmulxq_f16(float16x8_t a, float16x8_t b) {
1150   return vmulxq_f16(a, b);
1151 }
1152
1153 // CHECK-LABEL: define {{[^@]+}}@test_vpadd_f16
1154 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1155 // CHECK-NEXT:  entry:
1156 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1157 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[B]] to <8 x i8>
1158 // CHECK-NEXT:    [[VPADD_V2_I:%.*]] = call <4 x half> @llvm.aarch64.neon.faddp.v4f16(<4 x half> [[A]], <4 x half> [[B]])
1159 // CHECK-NEXT:    [[VPADD_V3_I:%.*]] = bitcast <4 x half> [[VPADD_V2_I]] to <8 x i8>
1160 // CHECK-NEXT:    ret <4 x half> [[VPADD_V2_I]]
1161 //
1162 float16x4_t test_vpadd_f16(float16x4_t a, float16x4_t b) {
1163   return vpadd_f16(a, b);
1164 }
1165
1166 // CHECK-LABEL: define {{[^@]+}}@test_vpaddq_f16
1167 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1168 // CHECK-NEXT:  entry:
1169 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1170 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[B]] to <16 x i8>
1171 // CHECK-NEXT:    [[VPADDQ_V2_I:%.*]] = call <8 x half> @llvm.aarch64.neon.faddp.v8f16(<8 x half> [[A]], <8 x half> [[B]])
1172 // CHECK-NEXT:    [[VPADDQ_V3_I:%.*]] = bitcast <8 x half> [[VPADDQ_V2_I]] to <16 x i8>
1173 // CHECK-NEXT:    ret <8 x half> [[VPADDQ_V2_I]]
1174 //
1175 float16x8_t test_vpaddq_f16(float16x8_t a, float16x8_t b) {
1176   return vpaddq_f16(a, b);
1177 }
1178
1179 // CHECK-LABEL: define {{[^@]+}}@test_vpmax_f16
1180 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1181 // CHECK-NEXT:  entry:
1182 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1183 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[B]] to <8 x i8>
1184 // CHECK-NEXT:    [[VPMAX2_I:%.*]] = call <4 x half> @llvm.aarch64.neon.fmaxp.v4f16(<4 x half> [[A]], <4 x half> [[B]])
1185 // CHECK-NEXT:    ret <4 x half> [[VPMAX2_I]]
1186 //
1187 float16x4_t test_vpmax_f16(float16x4_t a, float16x4_t b) {
1188   return vpmax_f16(a, b);
1189 }
1190
1191 // CHECK-LABEL: define {{[^@]+}}@test_vpmaxq_f16
1192 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1193 // CHECK-NEXT:  entry:
1194 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1195 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[B]] to <16 x i8>
1196 // CHECK-NEXT:    [[VPMAX2_I:%.*]] = call <8 x half> @llvm.aarch64.neon.fmaxp.v8f16(<8 x half> [[A]], <8 x half> [[B]])
1197 // CHECK-NEXT:    ret <8 x half> [[VPMAX2_I]]
1198 //
1199 float16x8_t test_vpmaxq_f16(float16x8_t a, float16x8_t b) {
1200   return vpmaxq_f16(a, b);
1201 }
1202
1203 // CHECK-LABEL: define {{[^@]+}}@test_vpmaxnm_f16
1204 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1205 // CHECK-NEXT:  entry:
1206 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1207 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[B]] to <8 x i8>
1208 // CHECK-NEXT:    [[VPMAXNM2_I:%.*]] = call <4 x half> @llvm.aarch64.neon.fmaxnmp.v4f16(<4 x half> [[A]], <4 x half> [[B]])
1209 // CHECK-NEXT:    ret <4 x half> [[VPMAXNM2_I]]
1210 //
1211 float16x4_t test_vpmaxnm_f16(float16x4_t a, float16x4_t b) {
1212   return vpmaxnm_f16(a, b);
1213 }
1214
1215 // CHECK-LABEL: define {{[^@]+}}@test_vpmaxnmq_f16
1216 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1217 // CHECK-NEXT:  entry:
1218 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1219 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[B]] to <16 x i8>
1220 // CHECK-NEXT:    [[VPMAXNM2_I:%.*]] = call <8 x half> @llvm.aarch64.neon.fmaxnmp.v8f16(<8 x half> [[A]], <8 x half> [[B]])
1221 // CHECK-NEXT:    ret <8 x half> [[VPMAXNM2_I]]
1222 //
1223 float16x8_t test_vpmaxnmq_f16(float16x8_t a, float16x8_t b) {
1224   return vpmaxnmq_f16(a, b);
1225 }
1226
1227 // CHECK-LABEL: define {{[^@]+}}@test_vpmin_f16
1228 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1229 // CHECK-NEXT:  entry:
1230 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1231 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[B]] to <8 x i8>
1232 // CHECK-NEXT:    [[VPMIN2_I:%.*]] = call <4 x half> @llvm.aarch64.neon.fminp.v4f16(<4 x half> [[A]], <4 x half> [[B]])
1233 // CHECK-NEXT:    ret <4 x half> [[VPMIN2_I]]
1234 //
1235 float16x4_t test_vpmin_f16(float16x4_t a, float16x4_t b) {
1236   return vpmin_f16(a, b);
1237 }
1238
1239 // CHECK-LABEL: define {{[^@]+}}@test_vpminq_f16
1240 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1241 // CHECK-NEXT:  entry:
1242 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1243 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[B]] to <16 x i8>
1244 // CHECK-NEXT:    [[VPMIN2_I:%.*]] = call <8 x half> @llvm.aarch64.neon.fminp.v8f16(<8 x half> [[A]], <8 x half> [[B]])
1245 // CHECK-NEXT:    ret <8 x half> [[VPMIN2_I]]
1246 //
1247 float16x8_t test_vpminq_f16(float16x8_t a, float16x8_t b) {
1248   return vpminq_f16(a, b);
1249 }
1250
1251 // CHECK-LABEL: define {{[^@]+}}@test_vpminnm_f16
1252 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1253 // CHECK-NEXT:  entry:
1254 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1255 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[B]] to <8 x i8>
1256 // CHECK-NEXT:    [[VPMINNM2_I:%.*]] = call <4 x half> @llvm.aarch64.neon.fminnmp.v4f16(<4 x half> [[A]], <4 x half> [[B]])
1257 // CHECK-NEXT:    ret <4 x half> [[VPMINNM2_I]]
1258 //
1259 float16x4_t test_vpminnm_f16(float16x4_t a, float16x4_t b) {
1260   return vpminnm_f16(a, b);
1261 }
1262
1263 // CHECK-LABEL: define {{[^@]+}}@test_vpminnmq_f16
1264 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1265 // CHECK-NEXT:  entry:
1266 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1267 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[B]] to <16 x i8>
1268 // CHECK-NEXT:    [[VPMINNM2_I:%.*]] = call <8 x half> @llvm.aarch64.neon.fminnmp.v8f16(<8 x half> [[A]], <8 x half> [[B]])
1269 // CHECK-NEXT:    ret <8 x half> [[VPMINNM2_I]]
1270 //
1271 float16x8_t test_vpminnmq_f16(float16x8_t a, float16x8_t b) {
1272   return vpminnmq_f16(a, b);
1273 }
1274
1275 // CHECK-LABEL: define {{[^@]+}}@test_vrecps_f16
1276 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1277 // CHECK-NEXT:  entry:
1278 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1279 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[B]] to <8 x i8>
1280 // CHECK-NEXT:    [[VRECPS_V2_I:%.*]] = call <4 x half> @llvm.aarch64.neon.frecps.v4f16(<4 x half> [[A]], <4 x half> [[B]])
1281 // CHECK-NEXT:    [[VRECPS_V3_I:%.*]] = bitcast <4 x half> [[VRECPS_V2_I]] to <8 x i8>
1282 // CHECK-NEXT:    ret <4 x half> [[VRECPS_V2_I]]
1283 //
1284 float16x4_t test_vrecps_f16(float16x4_t a, float16x4_t b) {
1285   return vrecps_f16(a, b);
1286 }
1287
1288 // CHECK-LABEL: define {{[^@]+}}@test_vrecpsq_f16
1289 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1290 // CHECK-NEXT:  entry:
1291 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1292 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[B]] to <16 x i8>
1293 // CHECK-NEXT:    [[VRECPSQ_V2_I:%.*]] = call <8 x half> @llvm.aarch64.neon.frecps.v8f16(<8 x half> [[A]], <8 x half> [[B]])
1294 // CHECK-NEXT:    [[VRECPSQ_V3_I:%.*]] = bitcast <8 x half> [[VRECPSQ_V2_I]] to <16 x i8>
1295 // CHECK-NEXT:    ret <8 x half> [[VRECPSQ_V2_I]]
1296 //
1297 float16x8_t test_vrecpsq_f16(float16x8_t a, float16x8_t b) {
1298   return vrecpsq_f16(a, b);
1299 }
1300
1301 // CHECK-LABEL: define {{[^@]+}}@test_vrsqrts_f16
1302 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1303 // CHECK-NEXT:  entry:
1304 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1305 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[B]] to <8 x i8>
1306 // CHECK-NEXT:    [[VRSQRTS_V2_I:%.*]] = call <4 x half> @llvm.aarch64.neon.frsqrts.v4f16(<4 x half> [[A]], <4 x half> [[B]])
1307 // CHECK-NEXT:    [[VRSQRTS_V3_I:%.*]] = bitcast <4 x half> [[VRSQRTS_V2_I]] to <8 x i8>
1308 // CHECK-NEXT:    ret <4 x half> [[VRSQRTS_V2_I]]
1309 //
1310 float16x4_t test_vrsqrts_f16(float16x4_t a, float16x4_t b) {
1311   return vrsqrts_f16(a, b);
1312 }
1313
1314 // CHECK-LABEL: define {{[^@]+}}@test_vrsqrtsq_f16
1315 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1316 // CHECK-NEXT:  entry:
1317 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1318 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[B]] to <16 x i8>
1319 // CHECK-NEXT:    [[VRSQRTSQ_V2_I:%.*]] = call <8 x half> @llvm.aarch64.neon.frsqrts.v8f16(<8 x half> [[A]], <8 x half> [[B]])
1320 // CHECK-NEXT:    [[VRSQRTSQ_V3_I:%.*]] = bitcast <8 x half> [[VRSQRTSQ_V2_I]] to <16 x i8>
1321 // CHECK-NEXT:    ret <8 x half> [[VRSQRTSQ_V2_I]]
1322 //
1323 float16x8_t test_vrsqrtsq_f16(float16x8_t a, float16x8_t b) {
1324   return vrsqrtsq_f16(a, b);
1325 }
1326
1327 // CHECK-LABEL: define {{[^@]+}}@test_vsub_f16
1328 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1329 // CHECK-NEXT:  entry:
1330 // CHECK-NEXT:    [[SUB_I:%.*]] = fsub <4 x half> [[A]], [[B]]
1331 // CHECK-NEXT:    ret <4 x half> [[SUB_I]]
1332 //
1333 float16x4_t test_vsub_f16(float16x4_t a, float16x4_t b) {
1334   return vsub_f16(a, b);
1335 }
1336
1337 // CHECK-LABEL: define {{[^@]+}}@test_vsubq_f16
1338 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1339 // CHECK-NEXT:  entry:
1340 // CHECK-NEXT:    [[SUB_I:%.*]] = fsub <8 x half> [[A]], [[B]]
1341 // CHECK-NEXT:    ret <8 x half> [[SUB_I]]
1342 //
1343 float16x8_t test_vsubq_f16(float16x8_t a, float16x8_t b) {
1344   return vsubq_f16(a, b);
1345 }
1346
1347 // CHECK-LABEL: define {{[^@]+}}@test_vfma_f16
1348 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]], <4 x half> noundef [[C:%.*]]) #[[ATTR0]] {
1349 // CHECK-NEXT:  entry:
1350 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1351 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[B]] to <8 x i8>
1352 // CHECK-NEXT:    [[TMP2:%.*]] = bitcast <4 x half> [[C]] to <8 x i8>
1353 // CHECK-NEXT:    [[TMP3:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[B]], <4 x half> [[C]], <4 x half> [[A]])
1354 // CHECK-NEXT:    ret <4 x half> [[TMP3]]
1355 //
1356 float16x4_t test_vfma_f16(float16x4_t a, float16x4_t b, float16x4_t c) {
1357   return vfma_f16(a, b, c);
1358 }
1359
1360 // CHECK-LABEL: define {{[^@]+}}@test_vfmaq_f16
1361 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]], <8 x half> noundef [[C:%.*]]) #[[ATTR0]] {
1362 // CHECK-NEXT:  entry:
1363 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1364 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[B]] to <16 x i8>
1365 // CHECK-NEXT:    [[TMP2:%.*]] = bitcast <8 x half> [[C]] to <16 x i8>
1366 // CHECK-NEXT:    [[TMP3:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[B]], <8 x half> [[C]], <8 x half> [[A]])
1367 // CHECK-NEXT:    ret <8 x half> [[TMP3]]
1368 //
1369 float16x8_t test_vfmaq_f16(float16x8_t a, float16x8_t b, float16x8_t c) {
1370   return vfmaq_f16(a, b, c);
1371 }
1372
1373 // CHECK-LABEL: define {{[^@]+}}@test_vfms_f16
1374 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]], <4 x half> noundef [[C:%.*]]) #[[ATTR0]] {
1375 // CHECK-NEXT:  entry:
1376 // CHECK-NEXT:    [[FNEG_I:%.*]] = fneg <4 x half> [[B]]
1377 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1378 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[FNEG_I]] to <8 x i8>
1379 // CHECK-NEXT:    [[TMP2:%.*]] = bitcast <4 x half> [[C]] to <8 x i8>
1380 // CHECK-NEXT:    [[TMP3:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[FNEG_I]], <4 x half> [[C]], <4 x half> [[A]])
1381 // CHECK-NEXT:    ret <4 x half> [[TMP3]]
1382 //
1383 float16x4_t test_vfms_f16(float16x4_t a, float16x4_t b, float16x4_t c) {
1384   return vfms_f16(a, b, c);
1385 }
1386
1387 // CHECK-LABEL: define {{[^@]+}}@test_vfmsq_f16
1388 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]], <8 x half> noundef [[C:%.*]]) #[[ATTR0]] {
1389 // CHECK-NEXT:  entry:
1390 // CHECK-NEXT:    [[FNEG_I:%.*]] = fneg <8 x half> [[B]]
1391 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1392 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[FNEG_I]] to <16 x i8>
1393 // CHECK-NEXT:    [[TMP2:%.*]] = bitcast <8 x half> [[C]] to <16 x i8>
1394 // CHECK-NEXT:    [[TMP3:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[FNEG_I]], <8 x half> [[C]], <8 x half> [[A]])
1395 // CHECK-NEXT:    ret <8 x half> [[TMP3]]
1396 //
1397 float16x8_t test_vfmsq_f16(float16x8_t a, float16x8_t b, float16x8_t c) {
1398   return vfmsq_f16(a, b, c);
1399 }
1400
1401 // CHECK-LABEL: define {{[^@]+}}@test_vfma_lane_f16
1402 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]], <4 x half> noundef [[C:%.*]]) #[[ATTR0]] {
1403 // CHECK-NEXT:  entry:
1404 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1405 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[B]] to <8 x i8>
1406 // CHECK-NEXT:    [[TMP2:%.*]] = bitcast <4 x half> [[C]] to <8 x i8>
1407 // CHECK-NEXT:    [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x half>
1408 // CHECK-NEXT:    [[LANE:%.*]] = shufflevector <4 x half> [[TMP3]], <4 x half> [[TMP3]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>
1409 // CHECK-NEXT:    [[FMLA:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>
1410 // CHECK-NEXT:    [[FMLA1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>
1411 // CHECK-NEXT:    [[FMLA2:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[FMLA]], <4 x half> [[LANE]], <4 x half> [[FMLA1]])
1412 // CHECK-NEXT:    ret <4 x half> [[FMLA2]]
1413 //
1414 float16x4_t test_vfma_lane_f16(float16x4_t a, float16x4_t b, float16x4_t c) {
1415   return vfma_lane_f16(a, b, c, 3);
1416 }
1417
1418 // CHECK-LABEL: define {{[^@]+}}@test_vfmaq_lane_f16
1419 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]], <4 x half> noundef [[C:%.*]]) #[[ATTR0]] {
1420 // CHECK-NEXT:  entry:
1421 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1422 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[B]] to <16 x i8>
1423 // CHECK-NEXT:    [[TMP2:%.*]] = bitcast <4 x half> [[C]] to <8 x i8>
1424 // CHECK-NEXT:    [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x half>
1425 // CHECK-NEXT:    [[LANE:%.*]] = shufflevector <4 x half> [[TMP3]], <4 x half> [[TMP3]], <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
1426 // CHECK-NEXT:    [[FMLA:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>
1427 // CHECK-NEXT:    [[FMLA1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>
1428 // CHECK-NEXT:    [[FMLA2:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[FMLA]], <8 x half> [[LANE]], <8 x half> [[FMLA1]])
1429 // CHECK-NEXT:    ret <8 x half> [[FMLA2]]
1430 //
1431 float16x8_t test_vfmaq_lane_f16(float16x8_t a, float16x8_t b, float16x4_t c) {
1432   return vfmaq_lane_f16(a, b, c, 3);
1433 }
1434
1435 // CHECK-LABEL: define {{[^@]+}}@test_vfma_laneq_f16
1436 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]], <8 x half> noundef [[C:%.*]]) #[[ATTR0]] {
1437 // CHECK-NEXT:  entry:
1438 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1439 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[B]] to <8 x i8>
1440 // CHECK-NEXT:    [[TMP2:%.*]] = bitcast <8 x half> [[C]] to <16 x i8>
1441 // CHECK-NEXT:    [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>
1442 // CHECK-NEXT:    [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>
1443 // CHECK-NEXT:    [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x half>
1444 // CHECK-NEXT:    [[LANE:%.*]] = shufflevector <8 x half> [[TMP5]], <8 x half> [[TMP5]], <4 x i32> <i32 7, i32 7, i32 7, i32 7>
1445 // CHECK-NEXT:    [[TMP6:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[LANE]], <4 x half> [[TMP4]], <4 x half> [[TMP3]])
1446 // CHECK-NEXT:    ret <4 x half> [[TMP6]]
1447 //
1448 float16x4_t test_vfma_laneq_f16(float16x4_t a, float16x4_t b, float16x8_t c) {
1449   return vfma_laneq_f16(a, b, c, 7);
1450 }
1451
1452 // CHECK-LABEL: define {{[^@]+}}@test_vfmaq_laneq_f16
1453 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]], <8 x half> noundef [[C:%.*]]) #[[ATTR0]] {
1454 // CHECK-NEXT:  entry:
1455 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1456 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[B]] to <16 x i8>
1457 // CHECK-NEXT:    [[TMP2:%.*]] = bitcast <8 x half> [[C]] to <16 x i8>
1458 // CHECK-NEXT:    [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>
1459 // CHECK-NEXT:    [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>
1460 // CHECK-NEXT:    [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x half>
1461 // CHECK-NEXT:    [[LANE:%.*]] = shufflevector <8 x half> [[TMP5]], <8 x half> [[TMP5]], <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
1462 // CHECK-NEXT:    [[TMP6:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[LANE]], <8 x half> [[TMP4]], <8 x half> [[TMP3]])
1463 // CHECK-NEXT:    ret <8 x half> [[TMP6]]
1464 //
1465 float16x8_t test_vfmaq_laneq_f16(float16x8_t a, float16x8_t b, float16x8_t c) {
1466   return vfmaq_laneq_f16(a, b, c, 7);
1467 }
1468
1469 // CHECK-LABEL: define {{[^@]+}}@test_vfma_n_f16
1470 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]], half noundef [[C:%.*]]) #[[ATTR0]] {
1471 // CHECK-NEXT:  entry:
1472 // CHECK-NEXT:    [[VECINIT:%.*]] = insertelement <4 x half> poison, half [[C]], i32 0
1473 // CHECK-NEXT:    [[VECINIT1:%.*]] = insertelement <4 x half> [[VECINIT]], half [[C]], i32 1
1474 // CHECK-NEXT:    [[VECINIT2:%.*]] = insertelement <4 x half> [[VECINIT1]], half [[C]], i32 2
1475 // CHECK-NEXT:    [[VECINIT3:%.*]] = insertelement <4 x half> [[VECINIT2]], half [[C]], i32 3
1476 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1477 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[B]] to <8 x i8>
1478 // CHECK-NEXT:    [[TMP2:%.*]] = bitcast <4 x half> [[VECINIT3]] to <8 x i8>
1479 // CHECK-NEXT:    [[TMP3:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[B]], <4 x half> [[VECINIT3]], <4 x half> [[A]])
1480 // CHECK-NEXT:    ret <4 x half> [[TMP3]]
1481 //
1482 float16x4_t test_vfma_n_f16(float16x4_t a, float16x4_t b, float16_t c) {
1483   return vfma_n_f16(a, b, c);
1484 }
1485
1486 // CHECK-LABEL: define {{[^@]+}}@test_vfmaq_n_f16
1487 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]], half noundef [[C:%.*]]) #[[ATTR0]] {
1488 // CHECK-NEXT:  entry:
1489 // CHECK-NEXT:    [[VECINIT:%.*]] = insertelement <8 x half> poison, half [[C]], i32 0
1490 // CHECK-NEXT:    [[VECINIT1:%.*]] = insertelement <8 x half> [[VECINIT]], half [[C]], i32 1
1491 // CHECK-NEXT:    [[VECINIT2:%.*]] = insertelement <8 x half> [[VECINIT1]], half [[C]], i32 2
1492 // CHECK-NEXT:    [[VECINIT3:%.*]] = insertelement <8 x half> [[VECINIT2]], half [[C]], i32 3
1493 // CHECK-NEXT:    [[VECINIT4:%.*]] = insertelement <8 x half> [[VECINIT3]], half [[C]], i32 4
1494 // CHECK-NEXT:    [[VECINIT5:%.*]] = insertelement <8 x half> [[VECINIT4]], half [[C]], i32 5
1495 // CHECK-NEXT:    [[VECINIT6:%.*]] = insertelement <8 x half> [[VECINIT5]], half [[C]], i32 6
1496 // CHECK-NEXT:    [[VECINIT7:%.*]] = insertelement <8 x half> [[VECINIT6]], half [[C]], i32 7
1497 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1498 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[B]] to <16 x i8>
1499 // CHECK-NEXT:    [[TMP2:%.*]] = bitcast <8 x half> [[VECINIT7]] to <16 x i8>
1500 // CHECK-NEXT:    [[TMP3:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[B]], <8 x half> [[VECINIT7]], <8 x half> [[A]])
1501 // CHECK-NEXT:    ret <8 x half> [[TMP3]]
1502 //
1503 float16x8_t test_vfmaq_n_f16(float16x8_t a, float16x8_t b, float16_t c) {
1504   return vfmaq_n_f16(a, b, c);
1505 }
1506
1507 // CHECK-LABEL: define {{[^@]+}}@test_vfmah_lane_f16
1508 // CHECK-SAME: (half noundef [[A:%.*]], half noundef [[B:%.*]], <4 x half> noundef [[C:%.*]]) #[[ATTR0]] {
1509 // CHECK-NEXT:  entry:
1510 // CHECK-NEXT:    [[EXTRACT:%.*]] = extractelement <4 x half> [[C]], i32 3
1511 // CHECK-NEXT:    [[TMP0:%.*]] = call half @llvm.fma.f16(half [[B]], half [[EXTRACT]], half [[A]])
1512 // CHECK-NEXT:    ret half [[TMP0]]
1513 //
1514 float16_t test_vfmah_lane_f16(float16_t a, float16_t b, float16x4_t c) {
1515   return vfmah_lane_f16(a, b, c, 3);
1516 }
1517
1518 // CHECK-LABEL: define {{[^@]+}}@test_vfmah_laneq_f16
1519 // CHECK-SAME: (half noundef [[A:%.*]], half noundef [[B:%.*]], <8 x half> noundef [[C:%.*]]) #[[ATTR0]] {
1520 // CHECK-NEXT:  entry:
1521 // CHECK-NEXT:    [[EXTRACT:%.*]] = extractelement <8 x half> [[C]], i32 7
1522 // CHECK-NEXT:    [[TMP0:%.*]] = call half @llvm.fma.f16(half [[B]], half [[EXTRACT]], half [[A]])
1523 // CHECK-NEXT:    ret half [[TMP0]]
1524 //
1525 float16_t test_vfmah_laneq_f16(float16_t a, float16_t b, float16x8_t c) {
1526   return vfmah_laneq_f16(a, b, c, 7);
1527 }
1528
1529 // CHECK-LABEL: define {{[^@]+}}@test_vfms_lane_f16
1530 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]], <4 x half> noundef [[C:%.*]]) #[[ATTR0]] {
1531 // CHECK-NEXT:  entry:
1532 // CHECK-NEXT:    [[FNEG:%.*]] = fneg <4 x half> [[B]]
1533 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1534 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[FNEG]] to <8 x i8>
1535 // CHECK-NEXT:    [[TMP2:%.*]] = bitcast <4 x half> [[C]] to <8 x i8>
1536 // CHECK-NEXT:    [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x half>
1537 // CHECK-NEXT:    [[LANE:%.*]] = shufflevector <4 x half> [[TMP3]], <4 x half> [[TMP3]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>
1538 // CHECK-NEXT:    [[FMLA:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>
1539 // CHECK-NEXT:    [[FMLA1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>
1540 // CHECK-NEXT:    [[FMLA2:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[FMLA]], <4 x half> [[LANE]], <4 x half> [[FMLA1]])
1541 // CHECK-NEXT:    ret <4 x half> [[FMLA2]]
1542 //
1543 float16x4_t test_vfms_lane_f16(float16x4_t a, float16x4_t b, float16x4_t c) {
1544   return vfms_lane_f16(a, b, c, 3);
1545 }
1546
1547 // CHECK-LABEL: define {{[^@]+}}@test_vfmsq_lane_f16
1548 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]], <4 x half> noundef [[C:%.*]]) #[[ATTR0]] {
1549 // CHECK-NEXT:  entry:
1550 // CHECK-NEXT:    [[FNEG:%.*]] = fneg <8 x half> [[B]]
1551 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1552 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[FNEG]] to <16 x i8>
1553 // CHECK-NEXT:    [[TMP2:%.*]] = bitcast <4 x half> [[C]] to <8 x i8>
1554 // CHECK-NEXT:    [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x half>
1555 // CHECK-NEXT:    [[LANE:%.*]] = shufflevector <4 x half> [[TMP3]], <4 x half> [[TMP3]], <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
1556 // CHECK-NEXT:    [[FMLA:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>
1557 // CHECK-NEXT:    [[FMLA1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>
1558 // CHECK-NEXT:    [[FMLA2:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[FMLA]], <8 x half> [[LANE]], <8 x half> [[FMLA1]])
1559 // CHECK-NEXT:    ret <8 x half> [[FMLA2]]
1560 //
1561 float16x8_t test_vfmsq_lane_f16(float16x8_t a, float16x8_t b, float16x4_t c) {
1562   return vfmsq_lane_f16(a, b, c, 3);
1563 }
1564
1565 // CHECK-LABEL: define {{[^@]+}}@test_vfms_laneq_f16
1566 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]], <8 x half> noundef [[C:%.*]]) #[[ATTR0]] {
1567 // CHECK-NEXT:  entry:
1568 // CHECK-NEXT:    [[FNEG:%.*]] = fneg <4 x half> [[B]]
1569 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1570 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[FNEG]] to <8 x i8>
1571 // CHECK-NEXT:    [[TMP2:%.*]] = bitcast <8 x half> [[C]] to <16 x i8>
1572 // CHECK-NEXT:    [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>
1573 // CHECK-NEXT:    [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>
1574 // CHECK-NEXT:    [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x half>
1575 // CHECK-NEXT:    [[LANE:%.*]] = shufflevector <8 x half> [[TMP5]], <8 x half> [[TMP5]], <4 x i32> <i32 7, i32 7, i32 7, i32 7>
1576 // CHECK-NEXT:    [[TMP6:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[LANE]], <4 x half> [[TMP4]], <4 x half> [[TMP3]])
1577 // CHECK-NEXT:    ret <4 x half> [[TMP6]]
1578 //
1579 float16x4_t test_vfms_laneq_f16(float16x4_t a, float16x4_t b, float16x8_t c) {
1580   return vfms_laneq_f16(a, b, c, 7);
1581 }
1582
1583 // CHECK-LABEL: define {{[^@]+}}@test_vfmsq_laneq_f16
1584 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]], <8 x half> noundef [[C:%.*]]) #[[ATTR0]] {
1585 // CHECK-NEXT:  entry:
1586 // CHECK-NEXT:    [[FNEG:%.*]] = fneg <8 x half> [[B]]
1587 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1588 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[FNEG]] to <16 x i8>
1589 // CHECK-NEXT:    [[TMP2:%.*]] = bitcast <8 x half> [[C]] to <16 x i8>
1590 // CHECK-NEXT:    [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>
1591 // CHECK-NEXT:    [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>
1592 // CHECK-NEXT:    [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x half>
1593 // CHECK-NEXT:    [[LANE:%.*]] = shufflevector <8 x half> [[TMP5]], <8 x half> [[TMP5]], <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
1594 // CHECK-NEXT:    [[TMP6:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[LANE]], <8 x half> [[TMP4]], <8 x half> [[TMP3]])
1595 // CHECK-NEXT:    ret <8 x half> [[TMP6]]
1596 //
1597 float16x8_t test_vfmsq_laneq_f16(float16x8_t a, float16x8_t b, float16x8_t c) {
1598   return vfmsq_laneq_f16(a, b, c, 7);
1599 }
1600
1601 // CHECK-LABEL: define {{[^@]+}}@test_vfms_n_f16
1602 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]], half noundef [[C:%.*]]) #[[ATTR0]] {
1603 // CHECK-NEXT:  entry:
1604 // CHECK-NEXT:    [[FNEG:%.*]] = fneg <4 x half> [[B]]
1605 // CHECK-NEXT:    [[VECINIT:%.*]] = insertelement <4 x half> poison, half [[C]], i32 0
1606 // CHECK-NEXT:    [[VECINIT1:%.*]] = insertelement <4 x half> [[VECINIT]], half [[C]], i32 1
1607 // CHECK-NEXT:    [[VECINIT2:%.*]] = insertelement <4 x half> [[VECINIT1]], half [[C]], i32 2
1608 // CHECK-NEXT:    [[VECINIT3:%.*]] = insertelement <4 x half> [[VECINIT2]], half [[C]], i32 3
1609 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1610 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[FNEG]] to <8 x i8>
1611 // CHECK-NEXT:    [[TMP2:%.*]] = bitcast <4 x half> [[VECINIT3]] to <8 x i8>
1612 // CHECK-NEXT:    [[TMP3:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[FNEG]], <4 x half> [[VECINIT3]], <4 x half> [[A]])
1613 // CHECK-NEXT:    ret <4 x half> [[TMP3]]
1614 //
1615 float16x4_t test_vfms_n_f16(float16x4_t a, float16x4_t b, float16_t c) {
1616   return vfms_n_f16(a, b, c);
1617 }
1618
1619 // CHECK-LABEL: define {{[^@]+}}@test_vfmsq_n_f16
1620 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]], half noundef [[C:%.*]]) #[[ATTR0]] {
1621 // CHECK-NEXT:  entry:
1622 // CHECK-NEXT:    [[FNEG:%.*]] = fneg <8 x half> [[B]]
1623 // CHECK-NEXT:    [[VECINIT:%.*]] = insertelement <8 x half> poison, half [[C]], i32 0
1624 // CHECK-NEXT:    [[VECINIT1:%.*]] = insertelement <8 x half> [[VECINIT]], half [[C]], i32 1
1625 // CHECK-NEXT:    [[VECINIT2:%.*]] = insertelement <8 x half> [[VECINIT1]], half [[C]], i32 2
1626 // CHECK-NEXT:    [[VECINIT3:%.*]] = insertelement <8 x half> [[VECINIT2]], half [[C]], i32 3
1627 // CHECK-NEXT:    [[VECINIT4:%.*]] = insertelement <8 x half> [[VECINIT3]], half [[C]], i32 4
1628 // CHECK-NEXT:    [[VECINIT5:%.*]] = insertelement <8 x half> [[VECINIT4]], half [[C]], i32 5
1629 // CHECK-NEXT:    [[VECINIT6:%.*]] = insertelement <8 x half> [[VECINIT5]], half [[C]], i32 6
1630 // CHECK-NEXT:    [[VECINIT7:%.*]] = insertelement <8 x half> [[VECINIT6]], half [[C]], i32 7
1631 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1632 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[FNEG]] to <16 x i8>
1633 // CHECK-NEXT:    [[TMP2:%.*]] = bitcast <8 x half> [[VECINIT7]] to <16 x i8>
1634 // CHECK-NEXT:    [[TMP3:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[FNEG]], <8 x half> [[VECINIT7]], <8 x half> [[A]])
1635 // CHECK-NEXT:    ret <8 x half> [[TMP3]]
1636 //
1637 float16x8_t test_vfmsq_n_f16(float16x8_t a, float16x8_t b, float16_t c) {
1638   return vfmsq_n_f16(a, b, c);
1639 }
1640
1641 // CHECK-LABEL: define {{[^@]+}}@test_vfmsh_lane_f16
1642 // CHECK-SAME: (half noundef [[A:%.*]], half noundef [[B:%.*]], <4 x half> noundef [[C:%.*]]) #[[ATTR0]] {
1643 // CHECK-NEXT:  entry:
1644 // CHECK-NEXT:    [[CONV:%.*]] = fpext half [[B]] to float
1645 // CHECK-NEXT:    [[FNEG:%.*]] = fneg float [[CONV]]
1646 // CHECK-NEXT:    [[TMP0:%.*]] = fptrunc float [[FNEG]] to half
1647 // CHECK-NEXT:    [[EXTRACT:%.*]] = extractelement <4 x half> [[C]], i32 3
1648 // CHECK-NEXT:    [[TMP1:%.*]] = call half @llvm.fma.f16(half [[TMP0]], half [[EXTRACT]], half [[A]])
1649 // CHECK-NEXT:    ret half [[TMP1]]
1650 //
1651 float16_t test_vfmsh_lane_f16(float16_t a, float16_t b, float16x4_t c) {
1652   return vfmsh_lane_f16(a, b, c, 3);
1653 }
1654
1655 // CHECK-LABEL: define {{[^@]+}}@test_vfmsh_laneq_f16
1656 // CHECK-SAME: (half noundef [[A:%.*]], half noundef [[B:%.*]], <8 x half> noundef [[C:%.*]]) #[[ATTR0]] {
1657 // CHECK-NEXT:  entry:
1658 // CHECK-NEXT:    [[CONV:%.*]] = fpext half [[B]] to float
1659 // CHECK-NEXT:    [[FNEG:%.*]] = fneg float [[CONV]]
1660 // CHECK-NEXT:    [[TMP0:%.*]] = fptrunc float [[FNEG]] to half
1661 // CHECK-NEXT:    [[EXTRACT:%.*]] = extractelement <8 x half> [[C]], i32 7
1662 // CHECK-NEXT:    [[TMP1:%.*]] = call half @llvm.fma.f16(half [[TMP0]], half [[EXTRACT]], half [[A]])
1663 // CHECK-NEXT:    ret half [[TMP1]]
1664 //
1665 float16_t test_vfmsh_laneq_f16(float16_t a, float16_t b, float16x8_t c) {
1666   return vfmsh_laneq_f16(a, b, c, 7);
1667 }
1668
1669 // CHECK-LABEL: define {{[^@]+}}@test_vmul_lane_f16
1670 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1671 // CHECK-NEXT:  entry:
1672 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[B]] to <8 x i8>
1673 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>
1674 // CHECK-NEXT:    [[LANE:%.*]] = shufflevector <4 x half> [[TMP1]], <4 x half> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>
1675 // CHECK-NEXT:    [[MUL:%.*]] = fmul <4 x half> [[A]], [[LANE]]
1676 // CHECK-NEXT:    ret <4 x half> [[MUL]]
1677 //
1678 float16x4_t test_vmul_lane_f16(float16x4_t a, float16x4_t b) {
1679   return vmul_lane_f16(a, b, 3);
1680 }
1681
1682 // CHECK-LABEL: define {{[^@]+}}@test_vmulq_lane_f16
1683 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1684 // CHECK-NEXT:  entry:
1685 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[B]] to <8 x i8>
1686 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>
1687 // CHECK-NEXT:    [[LANE:%.*]] = shufflevector <4 x half> [[TMP1]], <4 x half> [[TMP1]], <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
1688 // CHECK-NEXT:    [[MUL:%.*]] = fmul <8 x half> [[A]], [[LANE]]
1689 // CHECK-NEXT:    ret <8 x half> [[MUL]]
1690 //
1691 float16x8_t test_vmulq_lane_f16(float16x8_t a, float16x4_t b) {
1692   return vmulq_lane_f16(a, b, 3);
1693 }
1694
1695 // CHECK-LABEL: define {{[^@]+}}@test_vmul_laneq_f16
1696 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1697 // CHECK-NEXT:  entry:
1698 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[B]] to <16 x i8>
1699 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>
1700 // CHECK-NEXT:    [[LANE:%.*]] = shufflevector <8 x half> [[TMP1]], <8 x half> [[TMP1]], <4 x i32> <i32 7, i32 7, i32 7, i32 7>
1701 // CHECK-NEXT:    [[MUL:%.*]] = fmul <4 x half> [[A]], [[LANE]]
1702 // CHECK-NEXT:    ret <4 x half> [[MUL]]
1703 //
1704 float16x4_t test_vmul_laneq_f16(float16x4_t a, float16x8_t b) {
1705   return vmul_laneq_f16(a, b, 7);
1706 }
1707
1708 // CHECK-LABEL: define {{[^@]+}}@test_vmulq_laneq_f16
1709 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1710 // CHECK-NEXT:  entry:
1711 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[B]] to <16 x i8>
1712 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>
1713 // CHECK-NEXT:    [[LANE:%.*]] = shufflevector <8 x half> [[TMP1]], <8 x half> [[TMP1]], <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
1714 // CHECK-NEXT:    [[MUL:%.*]] = fmul <8 x half> [[A]], [[LANE]]
1715 // CHECK-NEXT:    ret <8 x half> [[MUL]]
1716 //
1717 float16x8_t test_vmulq_laneq_f16(float16x8_t a, float16x8_t b) {
1718   return vmulq_laneq_f16(a, b, 7);
1719 }
1720
1721 // CHECK-LABEL: define {{[^@]+}}@test_vmul_n_f16
1722 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], half noundef [[B:%.*]]) #[[ATTR0]] {
1723 // CHECK-NEXT:  entry:
1724 // CHECK-NEXT:    [[VECINIT:%.*]] = insertelement <4 x half> poison, half [[B]], i32 0
1725 // CHECK-NEXT:    [[VECINIT1:%.*]] = insertelement <4 x half> [[VECINIT]], half [[B]], i32 1
1726 // CHECK-NEXT:    [[VECINIT2:%.*]] = insertelement <4 x half> [[VECINIT1]], half [[B]], i32 2
1727 // CHECK-NEXT:    [[VECINIT3:%.*]] = insertelement <4 x half> [[VECINIT2]], half [[B]], i32 3
1728 // CHECK-NEXT:    [[MUL:%.*]] = fmul <4 x half> [[A]], [[VECINIT3]]
1729 // CHECK-NEXT:    ret <4 x half> [[MUL]]
1730 //
1731 float16x4_t test_vmul_n_f16(float16x4_t a, float16_t b) {
1732   return vmul_n_f16(a, b);
1733 }
1734
1735 // CHECK-LABEL: define {{[^@]+}}@test_vmulq_n_f16
1736 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], half noundef [[B:%.*]]) #[[ATTR0]] {
1737 // CHECK-NEXT:  entry:
1738 // CHECK-NEXT:    [[VECINIT:%.*]] = insertelement <8 x half> poison, half [[B]], i32 0
1739 // CHECK-NEXT:    [[VECINIT1:%.*]] = insertelement <8 x half> [[VECINIT]], half [[B]], i32 1
1740 // CHECK-NEXT:    [[VECINIT2:%.*]] = insertelement <8 x half> [[VECINIT1]], half [[B]], i32 2
1741 // CHECK-NEXT:    [[VECINIT3:%.*]] = insertelement <8 x half> [[VECINIT2]], half [[B]], i32 3
1742 // CHECK-NEXT:    [[VECINIT4:%.*]] = insertelement <8 x half> [[VECINIT3]], half [[B]], i32 4
1743 // CHECK-NEXT:    [[VECINIT5:%.*]] = insertelement <8 x half> [[VECINIT4]], half [[B]], i32 5
1744 // CHECK-NEXT:    [[VECINIT6:%.*]] = insertelement <8 x half> [[VECINIT5]], half [[B]], i32 6
1745 // CHECK-NEXT:    [[VECINIT7:%.*]] = insertelement <8 x half> [[VECINIT6]], half [[B]], i32 7
1746 // CHECK-NEXT:    [[MUL:%.*]] = fmul <8 x half> [[A]], [[VECINIT7]]
1747 // CHECK-NEXT:    ret <8 x half> [[MUL]]
1748 //
1749 float16x8_t test_vmulq_n_f16(float16x8_t a, float16_t b) {
1750   return vmulq_n_f16(a, b);
1751 }
1752
1753 // FIXME: Fix it when fp16 non-storage-only type becomes available.
1754 // CHECK-LABEL: define {{[^@]+}}@test_vmulh_lane_f16
1755 // CHECK-SAME: (half noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1756 // CHECK-NEXT:  entry:
1757 // CHECK-NEXT:    [[__REINT_847:%.*]] = alloca <4 x half>, align 8
1758 // CHECK-NEXT:    [[__REINT1_847:%.*]] = alloca i16, align 2
1759 // CHECK-NEXT:    [[CONV:%.*]] = fpext half [[A]] to float
1760 // CHECK-NEXT:    store <4 x half> [[B]], ptr [[__REINT_847]], align 8
1761 // CHECK-NEXT:    [[TMP0:%.*]] = load <4 x i16>, ptr [[__REINT_847]], align 8
1762 // CHECK-NEXT:    [[VGET_LANE:%.*]] = extractelement <4 x i16> [[TMP0]], i32 3
1763 // CHECK-NEXT:    store i16 [[VGET_LANE]], ptr [[__REINT1_847]], align 2
1764 // CHECK-NEXT:    [[TMP1:%.*]] = load half, ptr [[__REINT1_847]], align 2
1765 // CHECK-NEXT:    [[CONV2:%.*]] = fpext half [[TMP1]] to float
1766 // CHECK-NEXT:    [[MUL:%.*]] = fmul float [[CONV]], [[CONV2]]
1767 // CHECK-NEXT:    [[TMP2:%.*]] = fptrunc float [[MUL]] to half
1768 // CHECK-NEXT:    ret half [[TMP2]]
1769 //
1770 float16_t test_vmulh_lane_f16(float16_t a, float16x4_t b) {
1771   return vmulh_lane_f16(a, b, 3);
1772 }
1773
1774 // CHECK-LABEL: define {{[^@]+}}@test_vmulh_laneq_f16
1775 // CHECK-SAME: (half noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1776 // CHECK-NEXT:  entry:
1777 // CHECK-NEXT:    [[__REINT_850:%.*]] = alloca <8 x half>, align 16
1778 // CHECK-NEXT:    [[__REINT1_850:%.*]] = alloca i16, align 2
1779 // CHECK-NEXT:    [[CONV:%.*]] = fpext half [[A]] to float
1780 // CHECK-NEXT:    store <8 x half> [[B]], ptr [[__REINT_850]], align 16
1781 // CHECK-NEXT:    [[TMP0:%.*]] = load <8 x i16>, ptr [[__REINT_850]], align 16
1782 // CHECK-NEXT:    [[VGETQ_LANE:%.*]] = extractelement <8 x i16> [[TMP0]], i32 7
1783 // CHECK-NEXT:    store i16 [[VGETQ_LANE]], ptr [[__REINT1_850]], align 2
1784 // CHECK-NEXT:    [[TMP1:%.*]] = load half, ptr [[__REINT1_850]], align 2
1785 // CHECK-NEXT:    [[CONV2:%.*]] = fpext half [[TMP1]] to float
1786 // CHECK-NEXT:    [[MUL:%.*]] = fmul float [[CONV]], [[CONV2]]
1787 // CHECK-NEXT:    [[TMP2:%.*]] = fptrunc float [[MUL]] to half
1788 // CHECK-NEXT:    ret half [[TMP2]]
1789 //
1790 float16_t test_vmulh_laneq_f16(float16_t a, float16x8_t b) {
1791   return vmulh_laneq_f16(a, b, 7);
1792 }
1793
1794 // CHECK-LABEL: define {{[^@]+}}@test_vmulx_lane_f16
1795 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1796 // CHECK-NEXT:  entry:
1797 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[B]] to <8 x i8>
1798 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>
1799 // CHECK-NEXT:    [[LANE:%.*]] = shufflevector <4 x half> [[TMP1]], <4 x half> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>
1800 // CHECK-NEXT:    [[TMP2:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1801 // CHECK-NEXT:    [[TMP3:%.*]] = bitcast <4 x half> [[LANE]] to <8 x i8>
1802 // CHECK-NEXT:    [[VMULX2_I:%.*]] = call <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half> [[A]], <4 x half> [[LANE]])
1803 // CHECK-NEXT:    ret <4 x half> [[VMULX2_I]]
1804 //
1805 float16x4_t test_vmulx_lane_f16(float16x4_t a, float16x4_t b) {
1806   return vmulx_lane_f16(a, b, 3);
1807 }
1808
1809 // CHECK-LABEL: define {{[^@]+}}@test_vmulxq_lane_f16
1810 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1811 // CHECK-NEXT:  entry:
1812 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[B]] to <8 x i8>
1813 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>
1814 // CHECK-NEXT:    [[LANE:%.*]] = shufflevector <4 x half> [[TMP1]], <4 x half> [[TMP1]], <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
1815 // CHECK-NEXT:    [[TMP2:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1816 // CHECK-NEXT:    [[TMP3:%.*]] = bitcast <8 x half> [[LANE]] to <16 x i8>
1817 // CHECK-NEXT:    [[VMULX2_I:%.*]] = call <8 x half> @llvm.aarch64.neon.fmulx.v8f16(<8 x half> [[A]], <8 x half> [[LANE]])
1818 // CHECK-NEXT:    ret <8 x half> [[VMULX2_I]]
1819 //
1820 float16x8_t test_vmulxq_lane_f16(float16x8_t a, float16x4_t b) {
1821   return vmulxq_lane_f16(a, b, 3);
1822 }
1823
1824 // CHECK-LABEL: define {{[^@]+}}@test_vmulx_laneq_f16
1825 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1826 // CHECK-NEXT:  entry:
1827 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[B]] to <16 x i8>
1828 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>
1829 // CHECK-NEXT:    [[LANE:%.*]] = shufflevector <8 x half> [[TMP1]], <8 x half> [[TMP1]], <4 x i32> <i32 7, i32 7, i32 7, i32 7>
1830 // CHECK-NEXT:    [[TMP2:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1831 // CHECK-NEXT:    [[TMP3:%.*]] = bitcast <4 x half> [[LANE]] to <8 x i8>
1832 // CHECK-NEXT:    [[VMULX2_I:%.*]] = call <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half> [[A]], <4 x half> [[LANE]])
1833 // CHECK-NEXT:    ret <4 x half> [[VMULX2_I]]
1834 //
1835 float16x4_t test_vmulx_laneq_f16(float16x4_t a, float16x8_t b) {
1836   return vmulx_laneq_f16(a, b, 7);
1837 }
1838
1839 // CHECK-LABEL: define {{[^@]+}}@test_vmulxq_laneq_f16
1840 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1841 // CHECK-NEXT:  entry:
1842 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[B]] to <16 x i8>
1843 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>
1844 // CHECK-NEXT:    [[LANE:%.*]] = shufflevector <8 x half> [[TMP1]], <8 x half> [[TMP1]], <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
1845 // CHECK-NEXT:    [[TMP2:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1846 // CHECK-NEXT:    [[TMP3:%.*]] = bitcast <8 x half> [[LANE]] to <16 x i8>
1847 // CHECK-NEXT:    [[VMULX2_I:%.*]] = call <8 x half> @llvm.aarch64.neon.fmulx.v8f16(<8 x half> [[A]], <8 x half> [[LANE]])
1848 // CHECK-NEXT:    ret <8 x half> [[VMULX2_I]]
1849 //
1850 float16x8_t test_vmulxq_laneq_f16(float16x8_t a, float16x8_t b) {
1851   return vmulxq_laneq_f16(a, b, 7);
1852 }
1853
1854 // CHECK-LABEL: define {{[^@]+}}@test_vmulx_n_f16
1855 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], half noundef [[B:%.*]]) #[[ATTR0]] {
1856 // CHECK-NEXT:  entry:
1857 // CHECK-NEXT:    [[VECINIT:%.*]] = insertelement <4 x half> poison, half [[B]], i32 0
1858 // CHECK-NEXT:    [[VECINIT1:%.*]] = insertelement <4 x half> [[VECINIT]], half [[B]], i32 1
1859 // CHECK-NEXT:    [[VECINIT2:%.*]] = insertelement <4 x half> [[VECINIT1]], half [[B]], i32 2
1860 // CHECK-NEXT:    [[VECINIT3:%.*]] = insertelement <4 x half> [[VECINIT2]], half [[B]], i32 3
1861 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1862 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x half> [[VECINIT3]] to <8 x i8>
1863 // CHECK-NEXT:    [[VMULX2_I:%.*]] = call <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half> [[A]], <4 x half> [[VECINIT3]])
1864 // CHECK-NEXT:    ret <4 x half> [[VMULX2_I]]
1865 //
1866 float16x4_t test_vmulx_n_f16(float16x4_t a, float16_t b) {
1867   return vmulx_n_f16(a, b);
1868 }
1869
1870 // CHECK-LABEL: define {{[^@]+}}@test_vmulxq_n_f16
1871 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], half noundef [[B:%.*]]) #[[ATTR0]] {
1872 // CHECK-NEXT:  entry:
1873 // CHECK-NEXT:    [[VECINIT:%.*]] = insertelement <8 x half> poison, half [[B]], i32 0
1874 // CHECK-NEXT:    [[VECINIT1:%.*]] = insertelement <8 x half> [[VECINIT]], half [[B]], i32 1
1875 // CHECK-NEXT:    [[VECINIT2:%.*]] = insertelement <8 x half> [[VECINIT1]], half [[B]], i32 2
1876 // CHECK-NEXT:    [[VECINIT3:%.*]] = insertelement <8 x half> [[VECINIT2]], half [[B]], i32 3
1877 // CHECK-NEXT:    [[VECINIT4:%.*]] = insertelement <8 x half> [[VECINIT3]], half [[B]], i32 4
1878 // CHECK-NEXT:    [[VECINIT5:%.*]] = insertelement <8 x half> [[VECINIT4]], half [[B]], i32 5
1879 // CHECK-NEXT:    [[VECINIT6:%.*]] = insertelement <8 x half> [[VECINIT5]], half [[B]], i32 6
1880 // CHECK-NEXT:    [[VECINIT7:%.*]] = insertelement <8 x half> [[VECINIT6]], half [[B]], i32 7
1881 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1882 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x half> [[VECINIT7]] to <16 x i8>
1883 // CHECK-NEXT:    [[VMULX2_I:%.*]] = call <8 x half> @llvm.aarch64.neon.fmulx.v8f16(<8 x half> [[A]], <8 x half> [[VECINIT7]])
1884 // CHECK-NEXT:    ret <8 x half> [[VMULX2_I]]
1885 //
1886 float16x8_t test_vmulxq_n_f16(float16x8_t a, float16_t b) {
1887   return vmulxq_n_f16(a, b);
1888 }
1889
1890 // CHECK-LABEL: define {{[^@]+}}@test_vmulxh_lane_f16
1891 // CHECK-SAME: (half noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1892 // CHECK-NEXT:  entry:
1893 // CHECK-NEXT:    [[EXTRACT:%.*]] = extractelement <4 x half> [[B]], i32 3
1894 // CHECK-NEXT:    [[VMULX:%.*]] = call half @llvm.aarch64.neon.fmulx.f16(half [[A]], half [[EXTRACT]])
1895 // CHECK-NEXT:    ret half [[VMULX]]
1896 //
1897 float16_t test_vmulxh_lane_f16(float16_t a, float16x4_t b) {
1898   return vmulxh_lane_f16(a, b, 3);
1899 }
1900
1901 // CHECK-LABEL: define {{[^@]+}}@test_vmulxh_laneq_f16
1902 // CHECK-SAME: (half noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
1903 // CHECK-NEXT:  entry:
1904 // CHECK-NEXT:    [[EXTRACT:%.*]] = extractelement <8 x half> [[B]], i32 7
1905 // CHECK-NEXT:    [[VMULX:%.*]] = call half @llvm.aarch64.neon.fmulx.f16(half [[A]], half [[EXTRACT]])
1906 // CHECK-NEXT:    ret half [[VMULX]]
1907 //
1908 float16_t test_vmulxh_laneq_f16(float16_t a, float16x8_t b) {
1909   return vmulxh_laneq_f16(a, b, 7);
1910 }
1911
1912 // CHECK-LABEL: define {{[^@]+}}@test_vmaxv_f16
1913 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
1914 // CHECK-NEXT:  entry:
1915 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1916 // CHECK-NEXT:    [[VMAXV:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>
1917 // CHECK-NEXT:    [[VMAXV1:%.*]] = call half @llvm.aarch64.neon.fmaxv.f16.v4f16(<4 x half> [[VMAXV]])
1918 // CHECK-NEXT:    ret half [[VMAXV1]]
1919 //
1920 float16_t test_vmaxv_f16(float16x4_t a) {
1921   return vmaxv_f16(a);
1922 }
1923
1924 // CHECK-LABEL: define {{[^@]+}}@test_vmaxvq_f16
1925 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
1926 // CHECK-NEXT:  entry:
1927 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1928 // CHECK-NEXT:    [[VMAXV:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>
1929 // CHECK-NEXT:    [[VMAXV1:%.*]] = call half @llvm.aarch64.neon.fmaxv.f16.v8f16(<8 x half> [[VMAXV]])
1930 // CHECK-NEXT:    ret half [[VMAXV1]]
1931 //
1932 float16_t test_vmaxvq_f16(float16x8_t a) {
1933   return vmaxvq_f16(a);
1934 }
1935
1936 // CHECK-LABEL: define {{[^@]+}}@test_vminv_f16
1937 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
1938 // CHECK-NEXT:  entry:
1939 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1940 // CHECK-NEXT:    [[VMINV:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>
1941 // CHECK-NEXT:    [[VMINV1:%.*]] = call half @llvm.aarch64.neon.fminv.f16.v4f16(<4 x half> [[VMINV]])
1942 // CHECK-NEXT:    ret half [[VMINV1]]
1943 //
1944 float16_t test_vminv_f16(float16x4_t a) {
1945   return vminv_f16(a);
1946 }
1947
1948 // CHECK-LABEL: define {{[^@]+}}@test_vminvq_f16
1949 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
1950 // CHECK-NEXT:  entry:
1951 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1952 // CHECK-NEXT:    [[VMINV:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>
1953 // CHECK-NEXT:    [[VMINV1:%.*]] = call half @llvm.aarch64.neon.fminv.f16.v8f16(<8 x half> [[VMINV]])
1954 // CHECK-NEXT:    ret half [[VMINV1]]
1955 //
1956 float16_t test_vminvq_f16(float16x8_t a) {
1957   return vminvq_f16(a);
1958 }
1959
1960 // CHECK-LABEL: define {{[^@]+}}@test_vmaxnmv_f16
1961 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
1962 // CHECK-NEXT:  entry:
1963 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1964 // CHECK-NEXT:    [[VMAXNMV:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>
1965 // CHECK-NEXT:    [[VMAXNMV1:%.*]] = call half @llvm.aarch64.neon.fmaxnmv.f16.v4f16(<4 x half> [[VMAXNMV]])
1966 // CHECK-NEXT:    ret half [[VMAXNMV1]]
1967 //
1968 float16_t test_vmaxnmv_f16(float16x4_t a) {
1969   return vmaxnmv_f16(a);
1970 }
1971
1972 // CHECK-LABEL: define {{[^@]+}}@test_vmaxnmvq_f16
1973 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
1974 // CHECK-NEXT:  entry:
1975 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
1976 // CHECK-NEXT:    [[VMAXNMV:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>
1977 // CHECK-NEXT:    [[VMAXNMV1:%.*]] = call half @llvm.aarch64.neon.fmaxnmv.f16.v8f16(<8 x half> [[VMAXNMV]])
1978 // CHECK-NEXT:    ret half [[VMAXNMV1]]
1979 //
1980 float16_t test_vmaxnmvq_f16(float16x8_t a) {
1981   return vmaxnmvq_f16(a);
1982 }
1983
1984 // CHECK-LABEL: define {{[^@]+}}@test_vminnmv_f16
1985 // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] {
1986 // CHECK-NEXT:  entry:
1987 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8>
1988 // CHECK-NEXT:    [[VMINNMV:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>
1989 // CHECK-NEXT:    [[VMINNMV1:%.*]] = call half @llvm.aarch64.neon.fminnmv.f16.v4f16(<4 x half> [[VMINNMV]])
1990 // CHECK-NEXT:    ret half [[VMINNMV1]]
1991 //
1992 float16_t test_vminnmv_f16(float16x4_t a) {
1993   return vminnmv_f16(a);
1994 }
1995
1996 // CHECK-LABEL: define {{[^@]+}}@test_vminnmvq_f16
1997 // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR0]] {
1998 // CHECK-NEXT:  entry:
1999 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8>
2000 // CHECK-NEXT:    [[VMINNMV:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>
2001 // CHECK-NEXT:    [[VMINNMV1:%.*]] = call half @llvm.aarch64.neon.fminnmv.f16.v8f16(<8 x half> [[VMINNMV]])
2002 // CHECK-NEXT:    ret half [[VMINNMV1]]
2003 //
2004 float16_t test_vminnmvq_f16(float16x8_t a) {
2005   return vminnmvq_f16(a);
2006 }