clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cas.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // REQUIRES: powerpc-registered-target
   3 // RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu \
   4 // RUN:    -emit-llvm %s -o -  -target-cpu pwr8 | FileCheck %s
   5 // RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu \
   6 // RUN:   -emit-llvm %s -o -  -target-cpu pwr8 | FileCheck %s
   7
   8
   9 // CHECK-LABEL: @test_builtin_ppc_compare_and_swap(
  10 // CHECK-NEXT:  entry:
  11 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
  12 // CHECK-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
  13 // CHECK-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 4
  14 // CHECK-NEXT:    store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
  15 // CHECK-NEXT:    store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
  16 // CHECK-NEXT:    store i32 [[C:%.*]], ptr [[C_ADDR]], align 4
  17 // CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[B_ADDR]], align 4
  18 // CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr [[C_ADDR]], align 4
  19 // CHECK-NEXT:    [[TMP2:%.*]] = cmpxchg weak volatile ptr [[A_ADDR]], i32 [[TMP0]], i32 [[TMP1]] monotonic monotonic, align 4
  20 // CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { i32, i1 } [[TMP2]], 0
  21 // CHECK-NEXT:    [[TMP4:%.*]] = extractvalue { i32, i1 } [[TMP2]], 1
  22 // CHECK-NEXT:    store i32 [[TMP3]], ptr [[B_ADDR]], align 4
  23 // CHECK-NEXT:    [[TMP5:%.*]] = zext i1 [[TMP4]] to i32
  24 // CHECK-NEXT:    ret i32 [[TMP5]]
  25 //
  26 int test_builtin_ppc_compare_and_swap(int a, int b, int c) {
  27   return __compare_and_swap(&a, &b, c);
  28 }
  29
  30
  31 // CHECK-LABEL: @test_builtin_ppc_compare_and_swaplp(
  32 // CHECK-NEXT:  entry:
  33 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
  34 // CHECK-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
  35 // CHECK-NEXT:    [[C_ADDR:%.*]] = alloca i64, align 8
  36 // CHECK-NEXT:    store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
  37 // CHECK-NEXT:    store i64 [[B:%.*]], ptr [[B_ADDR]], align 8
  38 // CHECK-NEXT:    store i64 [[C:%.*]], ptr [[C_ADDR]], align 8
  39 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr [[B_ADDR]], align 8
  40 // CHECK-NEXT:    [[TMP1:%.*]] = load i64, ptr [[C_ADDR]], align 8
  41 // CHECK-NEXT:    [[TMP2:%.*]] = cmpxchg weak volatile ptr [[A_ADDR]], i64 [[TMP0]], i64 [[TMP1]] monotonic monotonic, align 8
  42 // CHECK-NEXT:    [[TMP3:%.*]] = extractvalue { i64, i1 } [[TMP2]], 0
  43 // CHECK-NEXT:    [[TMP4:%.*]] = extractvalue { i64, i1 } [[TMP2]], 1
  44 // CHECK-NEXT:    store i64 [[TMP3]], ptr [[B_ADDR]], align 8
  45 // CHECK-NEXT:    [[TMP5:%.*]] = zext i1 [[TMP4]] to i32
  46 // CHECK-NEXT:    ret i32 [[TMP5]]
  47 //
  48 int test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
  49   return __compare_and_swaplp(&a, &b, c);
  50 }
  51