clang/test/CodeGen/RISCV/attr-rvv-vector-bits-call.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f -target-feature +d -target-feature +zve64d -mvscale-min=4 -mvscale-max=4 -O1 -emit-llvm -o - %s | FileCheck %s
   3
   4 // REQUIRES: riscv-registered-target
   5
   6 #include <riscv_vector.h>
   7
   8 typedef vint32m1_t fixed_int32m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
   9 typedef vfloat64m1_t fixed_float64m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
  10 typedef vbool1_t fixed_bool1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
  11 typedef vbool4_t fixed_bool4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/4)));
  12
  13 //===----------------------------------------------------------------------===//
  14 // Test caller/callee with VLST <-> VLAT
  15 //===----------------------------------------------------------------------===//
  16
  17 // CHECK-LABEL: @sizeless_callee(
  18 // CHECK-NEXT:  entry:
  19 // CHECK-NEXT:    ret <vscale x 2 x i32> [[X:%.*]]
  20 //
  21 vint32m1_t sizeless_callee(vint32m1_t x) {
  22   return x;
  23 }
  24
  25 // CHECK-LABEL: @fixed_caller(
  26 // CHECK-NEXT:  entry:
  27 // CHECK-NEXT:    ret <vscale x 2 x i32> [[X_COERCE:%.*]]
  28 //
  29 fixed_int32m1_t fixed_caller(fixed_int32m1_t x) {
  30   return sizeless_callee(x);
  31 }
  32
  33 // CHECK-LABEL: @fixed_callee(
  34 // CHECK-NEXT:  entry:
  35 // CHECK-NEXT:    ret <vscale x 2 x i32> [[X_COERCE:%.*]]
  36 //
  37 fixed_int32m1_t fixed_callee(fixed_int32m1_t x) {
  38   return x;
  39 }
  40
  41 // CHECK-LABEL: @sizeless_caller(
  42 // CHECK-NEXT:  entry:
  43 // CHECK-NEXT:    ret <vscale x 2 x i32> [[X:%.*]]
  44 //
  45 vint32m1_t sizeless_caller(vint32m1_t x) {
  46   return fixed_callee(x);
  47 }
  48
  49 //===----------------------------------------------------------------------===//
  50 // fixed, fixed
  51 //===----------------------------------------------------------------------===//
  52
  53 // CHECK-LABEL: @call_int32_ff(
  54 // CHECK-NEXT:  entry:
  55 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1_COERCE:%.*]], <vscale x 2 x i32> [[OP2_COERCE:%.*]], i64 8)
  56 // CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
  57 //
  58 fixed_int32m1_t call_int32_ff(fixed_int32m1_t op1, fixed_int32m1_t op2) {
  59   return __riscv_vadd(op1, op2, __riscv_v_fixed_vlen/32);
  60 }
  61
  62 // CHECK-LABEL: @call_float64_ff(
  63 // CHECK-NEXT:  entry:
  64 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[OP1_COERCE:%.*]], <vscale x 1 x double> [[OP2_COERCE:%.*]], i64 7, i64 4)
  65 // CHECK-NEXT:    ret <vscale x 1 x double> [[TMP0]]
  66 //
  67 fixed_float64m1_t call_float64_ff(fixed_float64m1_t op1, fixed_float64m1_t op2) {
  68   return __riscv_vfadd(op1, op2, __riscv_v_fixed_vlen/64);
  69 }
  70
  71 // CHECK-LABEL: @call_bool1_ff(
  72 // CHECK-NEXT:  entry:
  73 // CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> [[TMP0:%.*]], <vscale x 64 x i1> [[TMP1:%.*]], i64 256)
  74 // CHECK-NEXT:    ret <vscale x 64 x i1> [[TMP2]]
  75 //
  76 fixed_bool1_t call_bool1_ff(fixed_bool1_t op1, fixed_bool1_t op2) {
  77   return __riscv_vmand(op1, op2, __riscv_v_fixed_vlen);
  78 }
  79
  80 // CHECK-LABEL: @call_bool4_ff(
  81 // CHECK-NEXT:  entry:
  82 // CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> [[TMP0:%.*]], <vscale x 16 x i1> [[TMP1:%.*]], i64 64)
  83 // CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP2]]
  84 //
  85 fixed_bool4_t call_bool4_ff(fixed_bool4_t op1, fixed_bool4_t op2) {
  86   return __riscv_vmand(op1, op2, __riscv_v_fixed_vlen / 4);
  87 }
  88
  89 //===----------------------------------------------------------------------===//
  90 // fixed, scalable
  91 //===----------------------------------------------------------------------===//
  92
  93 // CHECK-LABEL: @call_int32_fs(
  94 // CHECK-NEXT:  entry:
  95 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1_COERCE:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 8)
  96 // CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
  97 //
  98 fixed_int32m1_t call_int32_fs(fixed_int32m1_t op1, vint32m1_t op2) {
  99   return __riscv_vadd(op1, op2, __riscv_v_fixed_vlen/32);
 100 }
 101
 102 // CHECK-LABEL: @call_float64_fs(
 103 // CHECK-NEXT:  entry:
 104 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[OP1_COERCE:%.*]], <vscale x 1 x double> [[OP2:%.*]], i64 7, i64 4)
 105 // CHECK-NEXT:    ret <vscale x 1 x double> [[TMP0]]
 106 //
 107 fixed_float64m1_t call_float64_fs(fixed_float64m1_t op1, vfloat64m1_t op2) {
 108   return __riscv_vfadd(op1, op2, __riscv_v_fixed_vlen/64);
 109 }
 110
 111 // CHECK-LABEL: @call_bool1_fs(
 112 // CHECK-NEXT:  entry:
 113 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> [[TMP0:%.*]], <vscale x 64 x i1> [[OP2:%.*]], i64 256)
 114 // CHECK-NEXT:    ret <vscale x 64 x i1> [[TMP1]]
 115 //
 116 fixed_bool1_t call_bool1_fs(fixed_bool1_t op1, vbool1_t op2) {
 117   return __riscv_vmand(op1, op2, __riscv_v_fixed_vlen);
 118 }
 119
 120 // CHECK-LABEL: @call_bool4_fs(
 121 // CHECK-NEXT:  entry:
 122 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> [[TMP0:%.*]], <vscale x 16 x i1> [[OP2:%.*]], i64 64)
 123 // CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP1]]
 124 //
 125 fixed_bool4_t call_bool4_fs(fixed_bool4_t op1, vbool4_t op2) {
 126   return __riscv_vmand(op1, op2, __riscv_v_fixed_vlen / 4);
 127 }
 128
 129 //===----------------------------------------------------------------------===//
 130 // scalable, scalable
 131 //===----------------------------------------------------------------------===//
 132
 133 // CHECK-LABEL: @call_int32_ss(
 134 // CHECK-NEXT:  entry:
 135 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 8)
 136 // CHECK-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 137 //
 138 fixed_int32m1_t call_int32_ss(vint32m1_t op1, vint32m1_t op2) {
 139   return __riscv_vadd(op1, op2, __riscv_v_fixed_vlen/32);
 140 }
 141
 142 // CHECK-LABEL: @call_float64_ss(
 143 // CHECK-NEXT:  entry:
 144 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], i64 7, i64 4)
 145 // CHECK-NEXT:    ret <vscale x 1 x double> [[TMP0]]
 146 //
 147 fixed_float64m1_t call_float64_ss(vfloat64m1_t op1, vfloat64m1_t op2) {
 148   return __riscv_vfadd(op1, op2, __riscv_v_fixed_vlen/64);
 149 }
 150
 151 // CHECK-LABEL: @call_bool1_ss(
 152 // CHECK-NEXT:  entry:
 153 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[OP2:%.*]], i64 256)
 154 // CHECK-NEXT:    ret <vscale x 64 x i1> [[TMP0]]
 155 //
 156 fixed_bool1_t call_bool1_ss(vbool1_t op1, vbool1_t op2) {
 157   return __riscv_vmand(op1, op2, __riscv_v_fixed_vlen);
 158 }
 159
 160 // CHECK-LABEL: @call_bool4_ss(
 161 // CHECK-NEXT:  entry:
 162 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP2:%.*]], i64 64)
 163 // CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
 164 //
 165 fixed_bool4_t call_bool4_ss(vbool4_t op1, vbool4_t op2) {
 166   return __riscv_vmand(op1, op2, __riscv_v_fixed_vlen / 4);
 167 }