clang/test/CodeGen/RISCV/builtin-cpu-is.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
   2 // RUN: %clang_cc1 -triple riscv64-unknown-linux-gnu -disable-O0-optnone -emit-llvm %s -o - \
   3 // RUN:   | opt -S -passes=mem2reg | FileCheck %s --check-prefix=CHECK-RV64
   4
   5 // CHECK-RV64-LABEL: define dso_local signext i32 @test_cpu_is_veyron_v1(
   6 // CHECK-RV64-SAME: ) #[[ATTR0:[0-9]+]] {
   7 // CHECK-RV64-NEXT:  [[ENTRY:.*:]]
   8 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = load i32, ptr @__riscv_cpu_model, align 4
   9 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 1567
  10 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = load i64, ptr getelementptr inbounds nuw ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 1), align 8
  11 // CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp eq i64 [[TMP2]], -9223372036854710272
  12 // CHECK-RV64-NEXT:    [[TMP4:%.*]] = and i1 [[TMP1]], [[TMP3]]
  13 // CHECK-RV64-NEXT:    [[TMP5:%.*]] = load i64, ptr getelementptr inbounds nuw ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 2), align 8
  14 // CHECK-RV64-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 273
  15 // CHECK-RV64-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP6]]
  16 // CHECK-RV64-NEXT:    [[CONV:%.*]] = zext i1 [[TMP7]] to i32
  17 // CHECK-RV64-NEXT:    ret i32 [[CONV]]
  18 //
  19 int test_cpu_is_veyron_v1() {
  20   return __builtin_cpu_is("veyron-v1");
  21 }
  22
  23 // CHECK-RV64-LABEL: define dso_local signext i32 @test_cpu_is_spacemit_x60(
  24 // CHECK-RV64-SAME: ) #[[ATTR0]] {
  25 // CHECK-RV64-NEXT:  [[ENTRY:.*:]]
  26 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = load i32, ptr @__riscv_cpu_model, align 4
  27 // CHECK-RV64-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 1808
  28 // CHECK-RV64-NEXT:    [[TMP2:%.*]] = load i64, ptr getelementptr inbounds nuw ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 1), align 8
  29 // CHECK-RV64-NEXT:    [[TMP3:%.*]] = icmp eq i64 [[TMP2]], -9223372035378380799
  30 // CHECK-RV64-NEXT:    [[TMP4:%.*]] = and i1 [[TMP1]], [[TMP3]]
  31 // CHECK-RV64-NEXT:    [[TMP5:%.*]] = load i64, ptr getelementptr inbounds nuw ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 2), align 8
  32 // CHECK-RV64-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 1152921505839391232
  33 // CHECK-RV64-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP6]]
  34 // CHECK-RV64-NEXT:    [[CONV:%.*]] = zext i1 [[TMP7]] to i32
  35 // CHECK-RV64-NEXT:    ret i32 [[CONV]]
  36 //
  37 int test_cpu_is_spacemit_x60() {
  38   return __builtin_cpu_is("spacemit-x60");
  39 }