clang/test/CodeGen/RISCV/riscv32-vararg.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
   2 // RUN: %clang_cc1 -triple riscv32 -emit-llvm %s -o - | FileCheck %s
   3 // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-abi ilp32f -emit-llvm %s -o - \
   4 // RUN:     | FileCheck %s -check-prefixes=CHECK,CHECK-ILP32F
   5 // RUN: %clang_cc1 -triple riscv32 -target-feature +d -target-feature +f -target-abi ilp32d -emit-llvm %s -o - \
   6 // RUN:     | FileCheck %s -check-prefixes=CHECK,CHECK-ILP32D
   7 // RUN: %clang_cc1 -triple riscv32 -target-abi ilp32e -emit-llvm %s -o - \
   8 // RUN:     | FileCheck %s -check-prefixes=CHECK,CHECK-ILP32E
   9
  10 #include <stddef.h>
  11 #include <stdint.h>
  12
  13 struct tiny {
  14   uint8_t a, b, c, d;
  15 };
  16 struct small {
  17   int32_t a, *b;
  18 };
  19 struct small_aligned {
  20   int64_t a;
  21 };
  22 struct large {
  23   int32_t a, b, c, d;
  24 };
  25
  26 // Ensure that ABI lowering happens as expected for vararg calls. For RV32
  27 // with the base integer calling convention there will be no observable
  28 // differences in the lowered IR for a call with varargs vs without.
  29
  30 int f_va_callee(int, ...);
  31
  32 // CHECK-LABEL: define dso_local void @f_va_caller
  33 // CHECK-SAME: () #[[ATTR0:[0-9]+]] {
  34 // CHECK-NEXT:  entry:
  35 // CHECK-NEXT:    [[DOTCOMPOUNDLITERAL:%.*]] = alloca [[STRUCT_TINY:%.*]], align 1
  36 // CHECK-NEXT:    [[DOTCOMPOUNDLITERAL1:%.*]] = alloca [[STRUCT_SMALL:%.*]], align 4
  37 // CHECK-NEXT:    [[DOTCOMPOUNDLITERAL4:%.*]] = alloca [[STRUCT_SMALL_ALIGNED:%.*]], align 8
  38 // CHECK-NEXT:    [[DOTCOMPOUNDLITERAL6:%.*]] = alloca [[STRUCT_LARGE:%.*]], align 4
  39 // CHECK-NEXT:    [[BYVAL_TEMP:%.*]] = alloca [[STRUCT_LARGE]], align 4
  40 // CHECK-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_TINY]], ptr [[DOTCOMPOUNDLITERAL]], i32 0, i32 0
  41 // CHECK-NEXT:    store i8 6, ptr [[A]], align 1
  42 // CHECK-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_TINY]], ptr [[DOTCOMPOUNDLITERAL]], i32 0, i32 1
  43 // CHECK-NEXT:    store i8 7, ptr [[B]], align 1
  44 // CHECK-NEXT:    [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_TINY]], ptr [[DOTCOMPOUNDLITERAL]], i32 0, i32 2
  45 // CHECK-NEXT:    store i8 8, ptr [[C]], align 1
  46 // CHECK-NEXT:    [[D:%.*]] = getelementptr inbounds nuw [[STRUCT_TINY]], ptr [[DOTCOMPOUNDLITERAL]], i32 0, i32 3
  47 // CHECK-NEXT:    store i8 9, ptr [[D]], align 1
  48 // CHECK-NEXT:    [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMALL]], ptr [[DOTCOMPOUNDLITERAL1]], i32 0, i32 0
  49 // CHECK-NEXT:    store i32 10, ptr [[A2]], align 4
  50 // CHECK-NEXT:    [[B3:%.*]] = getelementptr inbounds nuw [[STRUCT_SMALL]], ptr [[DOTCOMPOUNDLITERAL1]], i32 0, i32 1
  51 // CHECK-NEXT:    store ptr null, ptr [[B3]], align 4
  52 // CHECK-NEXT:    [[A5:%.*]] = getelementptr inbounds nuw [[STRUCT_SMALL_ALIGNED]], ptr [[DOTCOMPOUNDLITERAL4]], i32 0, i32 0
  53 // CHECK-NEXT:    store i64 11, ptr [[A5]], align 8
  54 // CHECK-NEXT:    [[A7:%.*]] = getelementptr inbounds nuw [[STRUCT_LARGE]], ptr [[DOTCOMPOUNDLITERAL6]], i32 0, i32 0
  55 // CHECK-NEXT:    store i32 12, ptr [[A7]], align 4
  56 // CHECK-NEXT:    [[B8:%.*]] = getelementptr inbounds nuw [[STRUCT_LARGE]], ptr [[DOTCOMPOUNDLITERAL6]], i32 0, i32 1
  57 // CHECK-NEXT:    store i32 13, ptr [[B8]], align 4
  58 // CHECK-NEXT:    [[C9:%.*]] = getelementptr inbounds nuw [[STRUCT_LARGE]], ptr [[DOTCOMPOUNDLITERAL6]], i32 0, i32 2
  59 // CHECK-NEXT:    store i32 14, ptr [[C9]], align 4
  60 // CHECK-NEXT:    [[D10:%.*]] = getelementptr inbounds nuw [[STRUCT_LARGE]], ptr [[DOTCOMPOUNDLITERAL6]], i32 0, i32 3
  61 // CHECK-NEXT:    store i32 15, ptr [[D10]], align 4
  62 // CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTCOMPOUNDLITERAL]], align 1
  63 // CHECK-NEXT:    [[TMP1:%.*]] = load [2 x i32], ptr [[DOTCOMPOUNDLITERAL1]], align 4
  64 // CHECK-NEXT:    [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[STRUCT_SMALL_ALIGNED]], ptr [[DOTCOMPOUNDLITERAL4]], i32 0, i32 0
  65 // CHECK-NEXT:    [[TMP2:%.*]] = load i64, ptr [[COERCE_DIVE]], align 8
  66 // CHECK-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[BYVAL_TEMP]], ptr align 4 [[DOTCOMPOUNDLITERAL6]], i32 16, i1 false)
  67 // CHECK-NEXT:    [[CALL:%.*]] = call i32 (i32, ...) @f_va_callee(i32 noundef 1, i32 noundef 2, i64 noundef 3, double noundef 4.000000e+00, double noundef 5.000000e+00, i32 [[TMP0]], [2 x i32] [[TMP1]], i64 [[TMP2]], ptr noundef [[BYVAL_TEMP]])
  68 // CHECK-NEXT:    ret void
  69 //
  70 void f_va_caller(void) {
  71   f_va_callee(1, 2, 3LL, 4.0f, 5.0, (struct tiny){6, 7, 8, 9},
  72               (struct small){10, NULL}, (struct small_aligned){11},
  73               (struct large){12, 13, 14, 15});
  74 }
  75
  76 // CHECK-LABEL: define dso_local i32 @f_va_1
  77 // CHECK-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] {
  78 // CHECK-NEXT:  entry:
  79 // CHECK-NEXT:    [[FMT_ADDR:%.*]] = alloca ptr, align 4
  80 // CHECK-NEXT:    [[VA:%.*]] = alloca ptr, align 4
  81 // CHECK-NEXT:    [[V:%.*]] = alloca i32, align 4
  82 // CHECK-NEXT:    store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
  83 // CHECK-NEXT:    call void @llvm.va_start.p0(ptr [[VA]])
  84 // CHECK-NEXT:    [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
  85 // CHECK-NEXT:    [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 4
  86 // CHECK-NEXT:    store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
  87 // CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[ARGP_CUR]], align 4
  88 // CHECK-NEXT:    store i32 [[TMP0]], ptr [[V]], align 4
  89 // CHECK-NEXT:    call void @llvm.va_end.p0(ptr [[VA]])
  90 // CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr [[V]], align 4
  91 // CHECK-NEXT:    ret i32 [[TMP1]]
  92 //
  93 int f_va_1(char *fmt, ...) {
  94   __builtin_va_list va;
  95
  96   __builtin_va_start(va, fmt);
  97   int v = __builtin_va_arg(va, int);
  98   __builtin_va_end(va);
  99
 100   return v;
 101 }
 102
 103 // An "aligned" register pair (where the first register is even-numbered) is
 104 // used to pass varargs with 2x xlen alignment and 2x xlen size. Ensure the
 105 // correct offsets are used.
 106
 107 // CHECK-ILP32F-LABEL: define dso_local double @f_va_2
 108 // CHECK-ILP32F-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] {
 109 // CHECK-ILP32F-NEXT:  entry:
 110 // CHECK-ILP32F-NEXT:    [[FMT_ADDR:%.*]] = alloca ptr, align 4
 111 // CHECK-ILP32F-NEXT:    [[VA:%.*]] = alloca ptr, align 4
 112 // CHECK-ILP32F-NEXT:    [[V:%.*]] = alloca double, align 8
 113 // CHECK-ILP32F-NEXT:    store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
 114 // CHECK-ILP32F-NEXT:    call void @llvm.va_start.p0(ptr [[VA]])
 115 // CHECK-ILP32F-NEXT:    [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
 116 // CHECK-ILP32F-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 7
 117 // CHECK-ILP32F-NEXT:    [[ARGP_CUR_ALIGNED:%.*]] = call ptr @llvm.ptrmask.p0.i32(ptr [[TMP0]], i32 -8)
 118 // CHECK-ILP32F-NEXT:    [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR_ALIGNED]], i32 8
 119 // CHECK-ILP32F-NEXT:    store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
 120 // CHECK-ILP32F-NEXT:    [[TMP1:%.*]] = load double, ptr [[ARGP_CUR_ALIGNED]], align 8
 121 // CHECK-ILP32F-NEXT:    store double [[TMP1]], ptr [[V]], align 8
 122 // CHECK-ILP32F-NEXT:    call void @llvm.va_end.p0(ptr [[VA]])
 123 // CHECK-ILP32F-NEXT:    [[TMP2:%.*]] = load double, ptr [[V]], align 8
 124 // CHECK-ILP32F-NEXT:    ret double [[TMP2]]
 125 //
 126 // CHECK-ILP32D-LABEL: define dso_local double @f_va_2
 127 // CHECK-ILP32D-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] {
 128 // CHECK-ILP32D-NEXT:  entry:
 129 // CHECK-ILP32D-NEXT:    [[FMT_ADDR:%.*]] = alloca ptr, align 4
 130 // CHECK-ILP32D-NEXT:    [[VA:%.*]] = alloca ptr, align 4
 131 // CHECK-ILP32D-NEXT:    [[V:%.*]] = alloca double, align 8
 132 // CHECK-ILP32D-NEXT:    store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
 133 // CHECK-ILP32D-NEXT:    call void @llvm.va_start.p0(ptr [[VA]])
 134 // CHECK-ILP32D-NEXT:    [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
 135 // CHECK-ILP32D-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 7
 136 // CHECK-ILP32D-NEXT:    [[ARGP_CUR_ALIGNED:%.*]] = call ptr @llvm.ptrmask.p0.i32(ptr [[TMP0]], i32 -8)
 137 // CHECK-ILP32D-NEXT:    [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR_ALIGNED]], i32 8
 138 // CHECK-ILP32D-NEXT:    store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
 139 // CHECK-ILP32D-NEXT:    [[TMP1:%.*]] = load double, ptr [[ARGP_CUR_ALIGNED]], align 8
 140 // CHECK-ILP32D-NEXT:    store double [[TMP1]], ptr [[V]], align 8
 141 // CHECK-ILP32D-NEXT:    call void @llvm.va_end.p0(ptr [[VA]])
 142 // CHECK-ILP32D-NEXT:    [[TMP2:%.*]] = load double, ptr [[V]], align 8
 143 // CHECK-ILP32D-NEXT:    ret double [[TMP2]]
 144 //
 145 // CHECK-ILP32E-LABEL: define dso_local double @f_va_2
 146 // CHECK-ILP32E-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] {
 147 // CHECK-ILP32E-NEXT:  entry:
 148 // CHECK-ILP32E-NEXT:    [[FMT_ADDR:%.*]] = alloca ptr, align 4
 149 // CHECK-ILP32E-NEXT:    [[VA:%.*]] = alloca ptr, align 4
 150 // CHECK-ILP32E-NEXT:    [[V:%.*]] = alloca double, align 8
 151 // CHECK-ILP32E-NEXT:    store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
 152 // CHECK-ILP32E-NEXT:    call void @llvm.va_start.p0(ptr [[VA]])
 153 // CHECK-ILP32E-NEXT:    [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
 154 // CHECK-ILP32E-NEXT:    [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 8
 155 // CHECK-ILP32E-NEXT:    store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
 156 // CHECK-ILP32E-NEXT:    [[TMP0:%.*]] = load double, ptr [[ARGP_CUR]], align 4
 157 // CHECK-ILP32E-NEXT:    store double [[TMP0]], ptr [[V]], align 8
 158 // CHECK-ILP32E-NEXT:    call void @llvm.va_end.p0(ptr [[VA]])
 159 // CHECK-ILP32E-NEXT:    [[TMP1:%.*]] = load double, ptr [[V]], align 8
 160 // CHECK-ILP32E-NEXT:    ret double [[TMP1]]
 161 //
 162 double f_va_2(char *fmt, ...) {
 163   __builtin_va_list va;
 164
 165   __builtin_va_start(va, fmt);
 166   double v = __builtin_va_arg(va, double);
 167   __builtin_va_end(va);
 168
 169   return v;
 170 }
 171
 172 // Two "aligned" register pairs.
 173
 174 // CHECK-ILP32F-LABEL: define dso_local double @f_va_3
 175 // CHECK-ILP32F-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] {
 176 // CHECK-ILP32F-NEXT:  entry:
 177 // CHECK-ILP32F-NEXT:    [[FMT_ADDR:%.*]] = alloca ptr, align 4
 178 // CHECK-ILP32F-NEXT:    [[VA:%.*]] = alloca ptr, align 4
 179 // CHECK-ILP32F-NEXT:    [[V:%.*]] = alloca double, align 8
 180 // CHECK-ILP32F-NEXT:    [[W:%.*]] = alloca i32, align 4
 181 // CHECK-ILP32F-NEXT:    [[X:%.*]] = alloca double, align 8
 182 // CHECK-ILP32F-NEXT:    store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
 183 // CHECK-ILP32F-NEXT:    call void @llvm.va_start.p0(ptr [[VA]])
 184 // CHECK-ILP32F-NEXT:    [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
 185 // CHECK-ILP32F-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 7
 186 // CHECK-ILP32F-NEXT:    [[ARGP_CUR_ALIGNED:%.*]] = call ptr @llvm.ptrmask.p0.i32(ptr [[TMP0]], i32 -8)
 187 // CHECK-ILP32F-NEXT:    [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR_ALIGNED]], i32 8
 188 // CHECK-ILP32F-NEXT:    store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
 189 // CHECK-ILP32F-NEXT:    [[TMP1:%.*]] = load double, ptr [[ARGP_CUR_ALIGNED]], align 8
 190 // CHECK-ILP32F-NEXT:    store double [[TMP1]], ptr [[V]], align 8
 191 // CHECK-ILP32F-NEXT:    [[ARGP_CUR1:%.*]] = load ptr, ptr [[VA]], align 4
 192 // CHECK-ILP32F-NEXT:    [[ARGP_NEXT2:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR1]], i32 4
 193 // CHECK-ILP32F-NEXT:    store ptr [[ARGP_NEXT2]], ptr [[VA]], align 4
 194 // CHECK-ILP32F-NEXT:    [[TMP2:%.*]] = load i32, ptr [[ARGP_CUR1]], align 4
 195 // CHECK-ILP32F-NEXT:    store i32 [[TMP2]], ptr [[W]], align 4
 196 // CHECK-ILP32F-NEXT:    [[ARGP_CUR3:%.*]] = load ptr, ptr [[VA]], align 4
 197 // CHECK-ILP32F-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR3]], i32 7
 198 // CHECK-ILP32F-NEXT:    [[ARGP_CUR3_ALIGNED:%.*]] = call ptr @llvm.ptrmask.p0.i32(ptr [[TMP3]], i32 -8)
 199 // CHECK-ILP32F-NEXT:    [[ARGP_NEXT4:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR3_ALIGNED]], i32 8
 200 // CHECK-ILP32F-NEXT:    store ptr [[ARGP_NEXT4]], ptr [[VA]], align 4
 201 // CHECK-ILP32F-NEXT:    [[TMP4:%.*]] = load double, ptr [[ARGP_CUR3_ALIGNED]], align 8
 202 // CHECK-ILP32F-NEXT:    store double [[TMP4]], ptr [[X]], align 8
 203 // CHECK-ILP32F-NEXT:    call void @llvm.va_end.p0(ptr [[VA]])
 204 // CHECK-ILP32F-NEXT:    [[TMP5:%.*]] = load double, ptr [[V]], align 8
 205 // CHECK-ILP32F-NEXT:    [[TMP6:%.*]] = load double, ptr [[X]], align 8
 206 // CHECK-ILP32F-NEXT:    [[ADD:%.*]] = fadd double [[TMP5]], [[TMP6]]
 207 // CHECK-ILP32F-NEXT:    ret double [[ADD]]
 208 //
 209 // CHECK-ILP32D-LABEL: define dso_local double @f_va_3
 210 // CHECK-ILP32D-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] {
 211 // CHECK-ILP32D-NEXT:  entry:
 212 // CHECK-ILP32D-NEXT:    [[FMT_ADDR:%.*]] = alloca ptr, align 4
 213 // CHECK-ILP32D-NEXT:    [[VA:%.*]] = alloca ptr, align 4
 214 // CHECK-ILP32D-NEXT:    [[V:%.*]] = alloca double, align 8
 215 // CHECK-ILP32D-NEXT:    [[W:%.*]] = alloca i32, align 4
 216 // CHECK-ILP32D-NEXT:    [[X:%.*]] = alloca double, align 8
 217 // CHECK-ILP32D-NEXT:    store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
 218 // CHECK-ILP32D-NEXT:    call void @llvm.va_start.p0(ptr [[VA]])
 219 // CHECK-ILP32D-NEXT:    [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
 220 // CHECK-ILP32D-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 7
 221 // CHECK-ILP32D-NEXT:    [[ARGP_CUR_ALIGNED:%.*]] = call ptr @llvm.ptrmask.p0.i32(ptr [[TMP0]], i32 -8)
 222 // CHECK-ILP32D-NEXT:    [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR_ALIGNED]], i32 8
 223 // CHECK-ILP32D-NEXT:    store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
 224 // CHECK-ILP32D-NEXT:    [[TMP1:%.*]] = load double, ptr [[ARGP_CUR_ALIGNED]], align 8
 225 // CHECK-ILP32D-NEXT:    store double [[TMP1]], ptr [[V]], align 8
 226 // CHECK-ILP32D-NEXT:    [[ARGP_CUR1:%.*]] = load ptr, ptr [[VA]], align 4
 227 // CHECK-ILP32D-NEXT:    [[ARGP_NEXT2:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR1]], i32 4
 228 // CHECK-ILP32D-NEXT:    store ptr [[ARGP_NEXT2]], ptr [[VA]], align 4
 229 // CHECK-ILP32D-NEXT:    [[TMP2:%.*]] = load i32, ptr [[ARGP_CUR1]], align 4
 230 // CHECK-ILP32D-NEXT:    store i32 [[TMP2]], ptr [[W]], align 4
 231 // CHECK-ILP32D-NEXT:    [[ARGP_CUR3:%.*]] = load ptr, ptr [[VA]], align 4
 232 // CHECK-ILP32D-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR3]], i32 7
 233 // CHECK-ILP32D-NEXT:    [[ARGP_CUR3_ALIGNED:%.*]] = call ptr @llvm.ptrmask.p0.i32(ptr [[TMP3]], i32 -8)
 234 // CHECK-ILP32D-NEXT:    [[ARGP_NEXT4:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR3_ALIGNED]], i32 8
 235 // CHECK-ILP32D-NEXT:    store ptr [[ARGP_NEXT4]], ptr [[VA]], align 4
 236 // CHECK-ILP32D-NEXT:    [[TMP4:%.*]] = load double, ptr [[ARGP_CUR3_ALIGNED]], align 8
 237 // CHECK-ILP32D-NEXT:    store double [[TMP4]], ptr [[X]], align 8
 238 // CHECK-ILP32D-NEXT:    call void @llvm.va_end.p0(ptr [[VA]])
 239 // CHECK-ILP32D-NEXT:    [[TMP5:%.*]] = load double, ptr [[V]], align 8
 240 // CHECK-ILP32D-NEXT:    [[TMP6:%.*]] = load double, ptr [[X]], align 8
 241 // CHECK-ILP32D-NEXT:    [[ADD:%.*]] = fadd double [[TMP5]], [[TMP6]]
 242 // CHECK-ILP32D-NEXT:    ret double [[ADD]]
 243 //
 244 // CHECK-ILP32E-LABEL: define dso_local double @f_va_3
 245 // CHECK-ILP32E-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] {
 246 // CHECK-ILP32E-NEXT:  entry:
 247 // CHECK-ILP32E-NEXT:    [[FMT_ADDR:%.*]] = alloca ptr, align 4
 248 // CHECK-ILP32E-NEXT:    [[VA:%.*]] = alloca ptr, align 4
 249 // CHECK-ILP32E-NEXT:    [[V:%.*]] = alloca double, align 8
 250 // CHECK-ILP32E-NEXT:    [[W:%.*]] = alloca i32, align 4
 251 // CHECK-ILP32E-NEXT:    [[X:%.*]] = alloca double, align 8
 252 // CHECK-ILP32E-NEXT:    store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
 253 // CHECK-ILP32E-NEXT:    call void @llvm.va_start.p0(ptr [[VA]])
 254 // CHECK-ILP32E-NEXT:    [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
 255 // CHECK-ILP32E-NEXT:    [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 8
 256 // CHECK-ILP32E-NEXT:    store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
 257 // CHECK-ILP32E-NEXT:    [[TMP0:%.*]] = load double, ptr [[ARGP_CUR]], align 4
 258 // CHECK-ILP32E-NEXT:    store double [[TMP0]], ptr [[V]], align 8
 259 // CHECK-ILP32E-NEXT:    [[ARGP_CUR1:%.*]] = load ptr, ptr [[VA]], align 4
 260 // CHECK-ILP32E-NEXT:    [[ARGP_NEXT2:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR1]], i32 4
 261 // CHECK-ILP32E-NEXT:    store ptr [[ARGP_NEXT2]], ptr [[VA]], align 4
 262 // CHECK-ILP32E-NEXT:    [[TMP1:%.*]] = load i32, ptr [[ARGP_CUR1]], align 4
 263 // CHECK-ILP32E-NEXT:    store i32 [[TMP1]], ptr [[W]], align 4
 264 // CHECK-ILP32E-NEXT:    [[ARGP_CUR3:%.*]] = load ptr, ptr [[VA]], align 4
 265 // CHECK-ILP32E-NEXT:    [[ARGP_NEXT4:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR3]], i32 8
 266 // CHECK-ILP32E-NEXT:    store ptr [[ARGP_NEXT4]], ptr [[VA]], align 4
 267 // CHECK-ILP32E-NEXT:    [[TMP2:%.*]] = load double, ptr [[ARGP_CUR3]], align 4
 268 // CHECK-ILP32E-NEXT:    store double [[TMP2]], ptr [[X]], align 8
 269 // CHECK-ILP32E-NEXT:    call void @llvm.va_end.p0(ptr [[VA]])
 270 // CHECK-ILP32E-NEXT:    [[TMP3:%.*]] = load double, ptr [[V]], align 8
 271 // CHECK-ILP32E-NEXT:    [[TMP4:%.*]] = load double, ptr [[X]], align 8
 272 // CHECK-ILP32E-NEXT:    [[ADD:%.*]] = fadd double [[TMP3]], [[TMP4]]
 273 // CHECK-ILP32E-NEXT:    ret double [[ADD]]
 274 //
 275 double f_va_3(char *fmt, ...) {
 276   __builtin_va_list va;
 277
 278   __builtin_va_start(va, fmt);
 279   double v = __builtin_va_arg(va, double);
 280   int w = __builtin_va_arg(va, int);
 281   double x = __builtin_va_arg(va, double);
 282   __builtin_va_end(va);
 283
 284   return v + x;
 285 }
 286
 287 // CHECK-ILP32F-LABEL: define dso_local i32 @f_va_4
 288 // CHECK-ILP32F-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] {
 289 // CHECK-ILP32F-NEXT:  entry:
 290 // CHECK-ILP32F-NEXT:    [[FMT_ADDR:%.*]] = alloca ptr, align 4
 291 // CHECK-ILP32F-NEXT:    [[VA:%.*]] = alloca ptr, align 4
 292 // CHECK-ILP32F-NEXT:    [[V:%.*]] = alloca i32, align 4
 293 // CHECK-ILP32F-NEXT:    [[LD:%.*]] = alloca fp128, align 16
 294 // CHECK-ILP32F-NEXT:    [[TS:%.*]] = alloca [[STRUCT_TINY:%.*]], align 1
 295 // CHECK-ILP32F-NEXT:    [[SS:%.*]] = alloca [[STRUCT_SMALL:%.*]], align 4
 296 // CHECK-ILP32F-NEXT:    [[LS:%.*]] = alloca [[STRUCT_LARGE:%.*]], align 4
 297 // CHECK-ILP32F-NEXT:    [[RET:%.*]] = alloca i32, align 4
 298 // CHECK-ILP32F-NEXT:    store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
 299 // CHECK-ILP32F-NEXT:    call void @llvm.va_start.p0(ptr [[VA]])
 300 // CHECK-ILP32F-NEXT:    [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
 301 // CHECK-ILP32F-NEXT:    [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 4
 302 // CHECK-ILP32F-NEXT:    store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
 303 // CHECK-ILP32F-NEXT:    [[TMP0:%.*]] = load i32, ptr [[ARGP_CUR]], align 4
 304 // CHECK-ILP32F-NEXT:    store i32 [[TMP0]], ptr [[V]], align 4
 305 // CHECK-ILP32F-NEXT:    [[ARGP_CUR1:%.*]] = load ptr, ptr [[VA]], align 4
 306 // CHECK-ILP32F-NEXT:    [[ARGP_NEXT2:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR1]], i32 4
 307 // CHECK-ILP32F-NEXT:    store ptr [[ARGP_NEXT2]], ptr [[VA]], align 4
 308 // CHECK-ILP32F-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[ARGP_CUR1]], align 4
 309 // CHECK-ILP32F-NEXT:    [[TMP2:%.*]] = load fp128, ptr [[TMP1]], align 16
 310 // CHECK-ILP32F-NEXT:    store fp128 [[TMP2]], ptr [[LD]], align 16
 311 // CHECK-ILP32F-NEXT:    [[ARGP_CUR3:%.*]] = load ptr, ptr [[VA]], align 4
 312 // CHECK-ILP32F-NEXT:    [[ARGP_NEXT4:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR3]], i32 4
 313 // CHECK-ILP32F-NEXT:    store ptr [[ARGP_NEXT4]], ptr [[VA]], align 4
 314 // CHECK-ILP32F-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[TS]], ptr align 4 [[ARGP_CUR3]], i32 4, i1 false)
 315 // CHECK-ILP32F-NEXT:    [[ARGP_CUR5:%.*]] = load ptr, ptr [[VA]], align 4
 316 // CHECK-ILP32F-NEXT:    [[ARGP_NEXT6:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR5]], i32 8
 317 // CHECK-ILP32F-NEXT:    store ptr [[ARGP_NEXT6]], ptr [[VA]], align 4
 318 // CHECK-ILP32F-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[SS]], ptr align 4 [[ARGP_CUR5]], i32 8, i1 false)
 319 // CHECK-ILP32F-NEXT:    [[ARGP_CUR7:%.*]] = load ptr, ptr [[VA]], align 4
 320 // CHECK-ILP32F-NEXT:    [[ARGP_NEXT8:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR7]], i32 4
 321 // CHECK-ILP32F-NEXT:    store ptr [[ARGP_NEXT8]], ptr [[VA]], align 4
 322 // CHECK-ILP32F-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[ARGP_CUR7]], align 4
 323 // CHECK-ILP32F-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[LS]], ptr align 4 [[TMP3]], i32 16, i1 false)
 324 // CHECK-ILP32F-NEXT:    call void @llvm.va_end.p0(ptr [[VA]])
 325 // CHECK-ILP32F-NEXT:    [[TMP4:%.*]] = load i32, ptr [[V]], align 4
 326 // CHECK-ILP32F-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to fp128
 327 // CHECK-ILP32F-NEXT:    [[TMP5:%.*]] = load fp128, ptr [[LD]], align 16
 328 // CHECK-ILP32F-NEXT:    [[ADD:%.*]] = fadd fp128 [[CONV]], [[TMP5]]
 329 // CHECK-ILP32F-NEXT:    [[CONV9:%.*]] = fptosi fp128 [[ADD]] to i32
 330 // CHECK-ILP32F-NEXT:    store i32 [[CONV9]], ptr [[RET]], align 4
 331 // CHECK-ILP32F-NEXT:    [[TMP6:%.*]] = load i32, ptr [[RET]], align 4
 332 // CHECK-ILP32F-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 0
 333 // CHECK-ILP32F-NEXT:    [[TMP7:%.*]] = load i8, ptr [[A]], align 1
 334 // CHECK-ILP32F-NEXT:    [[CONV10:%.*]] = zext i8 [[TMP7]] to i32
 335 // CHECK-ILP32F-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP6]], [[CONV10]]
 336 // CHECK-ILP32F-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 1
 337 // CHECK-ILP32F-NEXT:    [[TMP8:%.*]] = load i8, ptr [[B]], align 1
 338 // CHECK-ILP32F-NEXT:    [[CONV12:%.*]] = zext i8 [[TMP8]] to i32
 339 // CHECK-ILP32F-NEXT:    [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]]
 340 // CHECK-ILP32F-NEXT:    [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 2
 341 // CHECK-ILP32F-NEXT:    [[TMP9:%.*]] = load i8, ptr [[C]], align 1
 342 // CHECK-ILP32F-NEXT:    [[CONV14:%.*]] = zext i8 [[TMP9]] to i32
 343 // CHECK-ILP32F-NEXT:    [[ADD15:%.*]] = add nsw i32 [[ADD13]], [[CONV14]]
 344 // CHECK-ILP32F-NEXT:    [[D:%.*]] = getelementptr inbounds nuw [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 3
 345 // CHECK-ILP32F-NEXT:    [[TMP10:%.*]] = load i8, ptr [[D]], align 1
 346 // CHECK-ILP32F-NEXT:    [[CONV16:%.*]] = zext i8 [[TMP10]] to i32
 347 // CHECK-ILP32F-NEXT:    [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]]
 348 // CHECK-ILP32F-NEXT:    store i32 [[ADD17]], ptr [[RET]], align 4
 349 // CHECK-ILP32F-NEXT:    [[TMP11:%.*]] = load i32, ptr [[RET]], align 4
 350 // CHECK-ILP32F-NEXT:    [[A18:%.*]] = getelementptr inbounds nuw [[STRUCT_SMALL]], ptr [[SS]], i32 0, i32 0
 351 // CHECK-ILP32F-NEXT:    [[TMP12:%.*]] = load i32, ptr [[A18]], align 4
 352 // CHECK-ILP32F-NEXT:    [[ADD19:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
 353 // CHECK-ILP32F-NEXT:    [[B20:%.*]] = getelementptr inbounds nuw [[STRUCT_SMALL]], ptr [[SS]], i32 0, i32 1
 354 // CHECK-ILP32F-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[B20]], align 4
 355 // CHECK-ILP32F-NEXT:    [[TMP14:%.*]] = ptrtoint ptr [[TMP13]] to i32
 356 // CHECK-ILP32F-NEXT:    [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[TMP14]]
 357 // CHECK-ILP32F-NEXT:    store i32 [[ADD21]], ptr [[RET]], align 4
 358 // CHECK-ILP32F-NEXT:    [[TMP15:%.*]] = load i32, ptr [[RET]], align 4
 359 // CHECK-ILP32F-NEXT:    [[A22:%.*]] = getelementptr inbounds nuw [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 0
 360 // CHECK-ILP32F-NEXT:    [[TMP16:%.*]] = load i32, ptr [[A22]], align 4
 361 // CHECK-ILP32F-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
 362 // CHECK-ILP32F-NEXT:    [[B24:%.*]] = getelementptr inbounds nuw [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 1
 363 // CHECK-ILP32F-NEXT:    [[TMP17:%.*]] = load i32, ptr [[B24]], align 4
 364 // CHECK-ILP32F-NEXT:    [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[TMP17]]
 365 // CHECK-ILP32F-NEXT:    [[C26:%.*]] = getelementptr inbounds nuw [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 2
 366 // CHECK-ILP32F-NEXT:    [[TMP18:%.*]] = load i32, ptr [[C26]], align 4
 367 // CHECK-ILP32F-NEXT:    [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[TMP18]]
 368 // CHECK-ILP32F-NEXT:    [[D28:%.*]] = getelementptr inbounds nuw [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 3
 369 // CHECK-ILP32F-NEXT:    [[TMP19:%.*]] = load i32, ptr [[D28]], align 4
 370 // CHECK-ILP32F-NEXT:    [[ADD29:%.*]] = add nsw i32 [[ADD27]], [[TMP19]]
 371 // CHECK-ILP32F-NEXT:    store i32 [[ADD29]], ptr [[RET]], align 4
 372 // CHECK-ILP32F-NEXT:    [[TMP20:%.*]] = load i32, ptr [[RET]], align 4
 373 // CHECK-ILP32F-NEXT:    ret i32 [[TMP20]]
 374 //
 375 // CHECK-ILP32D-LABEL: define dso_local i32 @f_va_4
 376 // CHECK-ILP32D-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] {
 377 // CHECK-ILP32D-NEXT:  entry:
 378 // CHECK-ILP32D-NEXT:    [[FMT_ADDR:%.*]] = alloca ptr, align 4
 379 // CHECK-ILP32D-NEXT:    [[VA:%.*]] = alloca ptr, align 4
 380 // CHECK-ILP32D-NEXT:    [[V:%.*]] = alloca i32, align 4
 381 // CHECK-ILP32D-NEXT:    [[LD:%.*]] = alloca fp128, align 16
 382 // CHECK-ILP32D-NEXT:    [[TS:%.*]] = alloca [[STRUCT_TINY:%.*]], align 1
 383 // CHECK-ILP32D-NEXT:    [[SS:%.*]] = alloca [[STRUCT_SMALL:%.*]], align 4
 384 // CHECK-ILP32D-NEXT:    [[LS:%.*]] = alloca [[STRUCT_LARGE:%.*]], align 4
 385 // CHECK-ILP32D-NEXT:    [[RET:%.*]] = alloca i32, align 4
 386 // CHECK-ILP32D-NEXT:    store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
 387 // CHECK-ILP32D-NEXT:    call void @llvm.va_start.p0(ptr [[VA]])
 388 // CHECK-ILP32D-NEXT:    [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
 389 // CHECK-ILP32D-NEXT:    [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 4
 390 // CHECK-ILP32D-NEXT:    store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
 391 // CHECK-ILP32D-NEXT:    [[TMP0:%.*]] = load i32, ptr [[ARGP_CUR]], align 4
 392 // CHECK-ILP32D-NEXT:    store i32 [[TMP0]], ptr [[V]], align 4
 393 // CHECK-ILP32D-NEXT:    [[ARGP_CUR1:%.*]] = load ptr, ptr [[VA]], align 4
 394 // CHECK-ILP32D-NEXT:    [[ARGP_NEXT2:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR1]], i32 4
 395 // CHECK-ILP32D-NEXT:    store ptr [[ARGP_NEXT2]], ptr [[VA]], align 4
 396 // CHECK-ILP32D-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[ARGP_CUR1]], align 4
 397 // CHECK-ILP32D-NEXT:    [[TMP2:%.*]] = load fp128, ptr [[TMP1]], align 16
 398 // CHECK-ILP32D-NEXT:    store fp128 [[TMP2]], ptr [[LD]], align 16
 399 // CHECK-ILP32D-NEXT:    [[ARGP_CUR3:%.*]] = load ptr, ptr [[VA]], align 4
 400 // CHECK-ILP32D-NEXT:    [[ARGP_NEXT4:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR3]], i32 4
 401 // CHECK-ILP32D-NEXT:    store ptr [[ARGP_NEXT4]], ptr [[VA]], align 4
 402 // CHECK-ILP32D-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[TS]], ptr align 4 [[ARGP_CUR3]], i32 4, i1 false)
 403 // CHECK-ILP32D-NEXT:    [[ARGP_CUR5:%.*]] = load ptr, ptr [[VA]], align 4
 404 // CHECK-ILP32D-NEXT:    [[ARGP_NEXT6:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR5]], i32 8
 405 // CHECK-ILP32D-NEXT:    store ptr [[ARGP_NEXT6]], ptr [[VA]], align 4
 406 // CHECK-ILP32D-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[SS]], ptr align 4 [[ARGP_CUR5]], i32 8, i1 false)
 407 // CHECK-ILP32D-NEXT:    [[ARGP_CUR7:%.*]] = load ptr, ptr [[VA]], align 4
 408 // CHECK-ILP32D-NEXT:    [[ARGP_NEXT8:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR7]], i32 4
 409 // CHECK-ILP32D-NEXT:    store ptr [[ARGP_NEXT8]], ptr [[VA]], align 4
 410 // CHECK-ILP32D-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[ARGP_CUR7]], align 4
 411 // CHECK-ILP32D-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[LS]], ptr align 4 [[TMP3]], i32 16, i1 false)
 412 // CHECK-ILP32D-NEXT:    call void @llvm.va_end.p0(ptr [[VA]])
 413 // CHECK-ILP32D-NEXT:    [[TMP4:%.*]] = load i32, ptr [[V]], align 4
 414 // CHECK-ILP32D-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to fp128
 415 // CHECK-ILP32D-NEXT:    [[TMP5:%.*]] = load fp128, ptr [[LD]], align 16
 416 // CHECK-ILP32D-NEXT:    [[ADD:%.*]] = fadd fp128 [[CONV]], [[TMP5]]
 417 // CHECK-ILP32D-NEXT:    [[CONV9:%.*]] = fptosi fp128 [[ADD]] to i32
 418 // CHECK-ILP32D-NEXT:    store i32 [[CONV9]], ptr [[RET]], align 4
 419 // CHECK-ILP32D-NEXT:    [[TMP6:%.*]] = load i32, ptr [[RET]], align 4
 420 // CHECK-ILP32D-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 0
 421 // CHECK-ILP32D-NEXT:    [[TMP7:%.*]] = load i8, ptr [[A]], align 1
 422 // CHECK-ILP32D-NEXT:    [[CONV10:%.*]] = zext i8 [[TMP7]] to i32
 423 // CHECK-ILP32D-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP6]], [[CONV10]]
 424 // CHECK-ILP32D-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 1
 425 // CHECK-ILP32D-NEXT:    [[TMP8:%.*]] = load i8, ptr [[B]], align 1
 426 // CHECK-ILP32D-NEXT:    [[CONV12:%.*]] = zext i8 [[TMP8]] to i32
 427 // CHECK-ILP32D-NEXT:    [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]]
 428 // CHECK-ILP32D-NEXT:    [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 2
 429 // CHECK-ILP32D-NEXT:    [[TMP9:%.*]] = load i8, ptr [[C]], align 1
 430 // CHECK-ILP32D-NEXT:    [[CONV14:%.*]] = zext i8 [[TMP9]] to i32
 431 // CHECK-ILP32D-NEXT:    [[ADD15:%.*]] = add nsw i32 [[ADD13]], [[CONV14]]
 432 // CHECK-ILP32D-NEXT:    [[D:%.*]] = getelementptr inbounds nuw [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 3
 433 // CHECK-ILP32D-NEXT:    [[TMP10:%.*]] = load i8, ptr [[D]], align 1
 434 // CHECK-ILP32D-NEXT:    [[CONV16:%.*]] = zext i8 [[TMP10]] to i32
 435 // CHECK-ILP32D-NEXT:    [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]]
 436 // CHECK-ILP32D-NEXT:    store i32 [[ADD17]], ptr [[RET]], align 4
 437 // CHECK-ILP32D-NEXT:    [[TMP11:%.*]] = load i32, ptr [[RET]], align 4
 438 // CHECK-ILP32D-NEXT:    [[A18:%.*]] = getelementptr inbounds nuw [[STRUCT_SMALL]], ptr [[SS]], i32 0, i32 0
 439 // CHECK-ILP32D-NEXT:    [[TMP12:%.*]] = load i32, ptr [[A18]], align 4
 440 // CHECK-ILP32D-NEXT:    [[ADD19:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
 441 // CHECK-ILP32D-NEXT:    [[B20:%.*]] = getelementptr inbounds nuw [[STRUCT_SMALL]], ptr [[SS]], i32 0, i32 1
 442 // CHECK-ILP32D-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[B20]], align 4
 443 // CHECK-ILP32D-NEXT:    [[TMP14:%.*]] = ptrtoint ptr [[TMP13]] to i32
 444 // CHECK-ILP32D-NEXT:    [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[TMP14]]
 445 // CHECK-ILP32D-NEXT:    store i32 [[ADD21]], ptr [[RET]], align 4
 446 // CHECK-ILP32D-NEXT:    [[TMP15:%.*]] = load i32, ptr [[RET]], align 4
 447 // CHECK-ILP32D-NEXT:    [[A22:%.*]] = getelementptr inbounds nuw [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 0
 448 // CHECK-ILP32D-NEXT:    [[TMP16:%.*]] = load i32, ptr [[A22]], align 4
 449 // CHECK-ILP32D-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
 450 // CHECK-ILP32D-NEXT:    [[B24:%.*]] = getelementptr inbounds nuw [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 1
 451 // CHECK-ILP32D-NEXT:    [[TMP17:%.*]] = load i32, ptr [[B24]], align 4
 452 // CHECK-ILP32D-NEXT:    [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[TMP17]]
 453 // CHECK-ILP32D-NEXT:    [[C26:%.*]] = getelementptr inbounds nuw [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 2
 454 // CHECK-ILP32D-NEXT:    [[TMP18:%.*]] = load i32, ptr [[C26]], align 4
 455 // CHECK-ILP32D-NEXT:    [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[TMP18]]
 456 // CHECK-ILP32D-NEXT:    [[D28:%.*]] = getelementptr inbounds nuw [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 3
 457 // CHECK-ILP32D-NEXT:    [[TMP19:%.*]] = load i32, ptr [[D28]], align 4
 458 // CHECK-ILP32D-NEXT:    [[ADD29:%.*]] = add nsw i32 [[ADD27]], [[TMP19]]
 459 // CHECK-ILP32D-NEXT:    store i32 [[ADD29]], ptr [[RET]], align 4
 460 // CHECK-ILP32D-NEXT:    [[TMP20:%.*]] = load i32, ptr [[RET]], align 4
 461 // CHECK-ILP32D-NEXT:    ret i32 [[TMP20]]
 462 //
 463 // CHECK-ILP32E-LABEL: define dso_local i32 @f_va_4
 464 // CHECK-ILP32E-SAME: (ptr noundef [[FMT:%.*]], ...) #[[ATTR0]] {
 465 // CHECK-ILP32E-NEXT:  entry:
 466 // CHECK-ILP32E-NEXT:    [[FMT_ADDR:%.*]] = alloca ptr, align 4
 467 // CHECK-ILP32E-NEXT:    [[VA:%.*]] = alloca ptr, align 4
 468 // CHECK-ILP32E-NEXT:    [[V:%.*]] = alloca i32, align 4
 469 // CHECK-ILP32E-NEXT:    [[LD:%.*]] = alloca fp128, align 16
 470 // CHECK-ILP32E-NEXT:    [[TS:%.*]] = alloca [[STRUCT_TINY:%.*]], align 1
 471 // CHECK-ILP32E-NEXT:    [[SS:%.*]] = alloca [[STRUCT_SMALL:%.*]], align 4
 472 // CHECK-ILP32E-NEXT:    [[LS:%.*]] = alloca [[STRUCT_LARGE:%.*]], align 4
 473 // CHECK-ILP32E-NEXT:    [[RET:%.*]] = alloca i32, align 4
 474 // CHECK-ILP32E-NEXT:    store ptr [[FMT]], ptr [[FMT_ADDR]], align 4
 475 // CHECK-ILP32E-NEXT:    call void @llvm.va_start.p0(ptr [[VA]])
 476 // CHECK-ILP32E-NEXT:    [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 4
 477 // CHECK-ILP32E-NEXT:    [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i32 4
 478 // CHECK-ILP32E-NEXT:    store ptr [[ARGP_NEXT]], ptr [[VA]], align 4
 479 // CHECK-ILP32E-NEXT:    [[TMP0:%.*]] = load i32, ptr [[ARGP_CUR]], align 4
 480 // CHECK-ILP32E-NEXT:    store i32 [[TMP0]], ptr [[V]], align 4
 481 // CHECK-ILP32E-NEXT:    [[ARGP_CUR1:%.*]] = load ptr, ptr [[VA]], align 4
 482 // CHECK-ILP32E-NEXT:    [[ARGP_NEXT2:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR1]], i32 4
 483 // CHECK-ILP32E-NEXT:    store ptr [[ARGP_NEXT2]], ptr [[VA]], align 4
 484 // CHECK-ILP32E-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[ARGP_CUR1]], align 4
 485 // CHECK-ILP32E-NEXT:    [[TMP2:%.*]] = load fp128, ptr [[TMP1]], align 4
 486 // CHECK-ILP32E-NEXT:    store fp128 [[TMP2]], ptr [[LD]], align 16
 487 // CHECK-ILP32E-NEXT:    [[ARGP_CUR3:%.*]] = load ptr, ptr [[VA]], align 4
 488 // CHECK-ILP32E-NEXT:    [[ARGP_NEXT4:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR3]], i32 4
 489 // CHECK-ILP32E-NEXT:    store ptr [[ARGP_NEXT4]], ptr [[VA]], align 4
 490 // CHECK-ILP32E-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[TS]], ptr align 4 [[ARGP_CUR3]], i32 4, i1 false)
 491 // CHECK-ILP32E-NEXT:    [[ARGP_CUR5:%.*]] = load ptr, ptr [[VA]], align 4
 492 // CHECK-ILP32E-NEXT:    [[ARGP_NEXT6:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR5]], i32 8
 493 // CHECK-ILP32E-NEXT:    store ptr [[ARGP_NEXT6]], ptr [[VA]], align 4
 494 // CHECK-ILP32E-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[SS]], ptr align 4 [[ARGP_CUR5]], i32 8, i1 false)
 495 // CHECK-ILP32E-NEXT:    [[ARGP_CUR7:%.*]] = load ptr, ptr [[VA]], align 4
 496 // CHECK-ILP32E-NEXT:    [[ARGP_NEXT8:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR7]], i32 4
 497 // CHECK-ILP32E-NEXT:    store ptr [[ARGP_NEXT8]], ptr [[VA]], align 4
 498 // CHECK-ILP32E-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[ARGP_CUR7]], align 4
 499 // CHECK-ILP32E-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[LS]], ptr align 4 [[TMP3]], i32 16, i1 false)
 500 // CHECK-ILP32E-NEXT:    call void @llvm.va_end.p0(ptr [[VA]])
 501 // CHECK-ILP32E-NEXT:    [[TMP4:%.*]] = load i32, ptr [[V]], align 4
 502 // CHECK-ILP32E-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to fp128
 503 // CHECK-ILP32E-NEXT:    [[TMP5:%.*]] = load fp128, ptr [[LD]], align 16
 504 // CHECK-ILP32E-NEXT:    [[ADD:%.*]] = fadd fp128 [[CONV]], [[TMP5]]
 505 // CHECK-ILP32E-NEXT:    [[CONV9:%.*]] = fptosi fp128 [[ADD]] to i32
 506 // CHECK-ILP32E-NEXT:    store i32 [[CONV9]], ptr [[RET]], align 4
 507 // CHECK-ILP32E-NEXT:    [[TMP6:%.*]] = load i32, ptr [[RET]], align 4
 508 // CHECK-ILP32E-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 0
 509 // CHECK-ILP32E-NEXT:    [[TMP7:%.*]] = load i8, ptr [[A]], align 1
 510 // CHECK-ILP32E-NEXT:    [[CONV10:%.*]] = zext i8 [[TMP7]] to i32
 511 // CHECK-ILP32E-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP6]], [[CONV10]]
 512 // CHECK-ILP32E-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 1
 513 // CHECK-ILP32E-NEXT:    [[TMP8:%.*]] = load i8, ptr [[B]], align 1
 514 // CHECK-ILP32E-NEXT:    [[CONV12:%.*]] = zext i8 [[TMP8]] to i32
 515 // CHECK-ILP32E-NEXT:    [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]]
 516 // CHECK-ILP32E-NEXT:    [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 2
 517 // CHECK-ILP32E-NEXT:    [[TMP9:%.*]] = load i8, ptr [[C]], align 1
 518 // CHECK-ILP32E-NEXT:    [[CONV14:%.*]] = zext i8 [[TMP9]] to i32
 519 // CHECK-ILP32E-NEXT:    [[ADD15:%.*]] = add nsw i32 [[ADD13]], [[CONV14]]
 520 // CHECK-ILP32E-NEXT:    [[D:%.*]] = getelementptr inbounds nuw [[STRUCT_TINY]], ptr [[TS]], i32 0, i32 3
 521 // CHECK-ILP32E-NEXT:    [[TMP10:%.*]] = load i8, ptr [[D]], align 1
 522 // CHECK-ILP32E-NEXT:    [[CONV16:%.*]] = zext i8 [[TMP10]] to i32
 523 // CHECK-ILP32E-NEXT:    [[ADD17:%.*]] = add nsw i32 [[ADD15]], [[CONV16]]
 524 // CHECK-ILP32E-NEXT:    store i32 [[ADD17]], ptr [[RET]], align 4
 525 // CHECK-ILP32E-NEXT:    [[TMP11:%.*]] = load i32, ptr [[RET]], align 4
 526 // CHECK-ILP32E-NEXT:    [[A18:%.*]] = getelementptr inbounds nuw [[STRUCT_SMALL]], ptr [[SS]], i32 0, i32 0
 527 // CHECK-ILP32E-NEXT:    [[TMP12:%.*]] = load i32, ptr [[A18]], align 4
 528 // CHECK-ILP32E-NEXT:    [[ADD19:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
 529 // CHECK-ILP32E-NEXT:    [[B20:%.*]] = getelementptr inbounds nuw [[STRUCT_SMALL]], ptr [[SS]], i32 0, i32 1
 530 // CHECK-ILP32E-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[B20]], align 4
 531 // CHECK-ILP32E-NEXT:    [[TMP14:%.*]] = ptrtoint ptr [[TMP13]] to i32
 532 // CHECK-ILP32E-NEXT:    [[ADD21:%.*]] = add nsw i32 [[ADD19]], [[TMP14]]
 533 // CHECK-ILP32E-NEXT:    store i32 [[ADD21]], ptr [[RET]], align 4
 534 // CHECK-ILP32E-NEXT:    [[TMP15:%.*]] = load i32, ptr [[RET]], align 4
 535 // CHECK-ILP32E-NEXT:    [[A22:%.*]] = getelementptr inbounds nuw [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 0
 536 // CHECK-ILP32E-NEXT:    [[TMP16:%.*]] = load i32, ptr [[A22]], align 4
 537 // CHECK-ILP32E-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
 538 // CHECK-ILP32E-NEXT:    [[B24:%.*]] = getelementptr inbounds nuw [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 1
 539 // CHECK-ILP32E-NEXT:    [[TMP17:%.*]] = load i32, ptr [[B24]], align 4
 540 // CHECK-ILP32E-NEXT:    [[ADD25:%.*]] = add nsw i32 [[ADD23]], [[TMP17]]
 541 // CHECK-ILP32E-NEXT:    [[C26:%.*]] = getelementptr inbounds nuw [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 2
 542 // CHECK-ILP32E-NEXT:    [[TMP18:%.*]] = load i32, ptr [[C26]], align 4
 543 // CHECK-ILP32E-NEXT:    [[ADD27:%.*]] = add nsw i32 [[ADD25]], [[TMP18]]
 544 // CHECK-ILP32E-NEXT:    [[D28:%.*]] = getelementptr inbounds nuw [[STRUCT_LARGE]], ptr [[LS]], i32 0, i32 3
 545 // CHECK-ILP32E-NEXT:    [[TMP19:%.*]] = load i32, ptr [[D28]], align 4
 546 // CHECK-ILP32E-NEXT:    [[ADD29:%.*]] = add nsw i32 [[ADD27]], [[TMP19]]
 547 // CHECK-ILP32E-NEXT:    store i32 [[ADD29]], ptr [[RET]], align 4
 548 // CHECK-ILP32E-NEXT:    [[TMP20:%.*]] = load i32, ptr [[RET]], align 4
 549 // CHECK-ILP32E-NEXT:    ret i32 [[TMP20]]
 550 //
 551 int f_va_4(char *fmt, ...) {
 552   __builtin_va_list va;
 553
 554   __builtin_va_start(va, fmt);
 555   int v = __builtin_va_arg(va, int);
 556   long double ld = __builtin_va_arg(va, long double);
 557   struct tiny ts = __builtin_va_arg(va, struct tiny);
 558   struct small ss = __builtin_va_arg(va, struct small);
 559   struct large ls = __builtin_va_arg(va, struct large);
 560   __builtin_va_end(va);
 561
 562   int ret = (int)((long double)v + ld);
 563   ret = ret + ts.a + ts.b + ts.c + ts.d;
 564   ret = ret + ss.a + (int)ss.b;
 565   ret = ret + ls.a + ls.b + ls.c + ls.d;
 566
 567   return ret;
 568 }