clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // RUN: %clang_cc1 -triple riscv32 -target-feature +zknh -emit-llvm %s -o - \
   3 // RUN:     -disable-O0-optnone | opt -S -passes=mem2reg \
   4 // RUN:     | FileCheck %s  -check-prefix=RV32ZKNH
   5
   6 #include <riscv_crypto.h>
   7
   8 // RV32ZKNH-LABEL: @sha256sig0(
   9 // RV32ZKNH-NEXT:  entry:
  10 // RV32ZKNH-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.sha256sig0(i32 [[RS1:%.*]])
  11 // RV32ZKNH-NEXT:    ret i32 [[TMP0]]
  12 //
  13 uint32_t sha256sig0(uint32_t rs1) {
  14   return __riscv_sha256sig0(rs1);
  15 }
  16
  17 // RV32ZKNH-LABEL: @sha256sig1(
  18 // RV32ZKNH-NEXT:  entry:
  19 // RV32ZKNH-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.sha256sig1(i32 [[RS1:%.*]])
  20 // RV32ZKNH-NEXT:    ret i32 [[TMP0]]
  21 //
  22 uint32_t sha256sig1(uint32_t rs1) {
  23   return __riscv_sha256sig1(rs1);
  24 }
  25
  26 // RV32ZKNH-LABEL: @sha256sum0(
  27 // RV32ZKNH-NEXT:  entry:
  28 // RV32ZKNH-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.sha256sum0(i32 [[RS1:%.*]])
  29 // RV32ZKNH-NEXT:    ret i32 [[TMP0]]
  30 //
  31 uint32_t sha256sum0(uint32_t rs1) {
  32   return __riscv_sha256sum0(rs1);
  33 }
  34
  35 // RV32ZKNH-LABEL: @sha256sum1(
  36 // RV32ZKNH-NEXT:  entry:
  37 // RV32ZKNH-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.sha256sum1(i32 [[RS1:%.*]])
  38 // RV32ZKNH-NEXT:    ret i32 [[TMP0]]
  39 //
  40 uint32_t sha256sum1(uint32_t rs1) {
  41   return __riscv_sha256sum1(rs1);
  42 }
  43
  44 // RV32ZKNH-LABEL: @sha512sig0h(
  45 // RV32ZKNH-NEXT:  entry:
  46 // RV32ZKNH-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.sha512sig0h(i32 [[RS1:%.*]], i32 [[RS2:%.*]])
  47 // RV32ZKNH-NEXT:    ret i32 [[TMP0]]
  48 //
  49 uint32_t sha512sig0h(uint32_t rs1, uint32_t rs2) {
  50   return __riscv_sha512sig0h(rs1, rs2);
  51 }
  52
  53 // RV32ZKNH-LABEL: @sha512sig0l(
  54 // RV32ZKNH-NEXT:  entry:
  55 // RV32ZKNH-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.sha512sig0l(i32 [[RS1:%.*]], i32 [[RS2:%.*]])
  56 // RV32ZKNH-NEXT:    ret i32 [[TMP0]]
  57 //
  58 uint32_t sha512sig0l(uint32_t rs1, uint32_t rs2) {
  59   return __riscv_sha512sig0l(rs1, rs2);
  60 }
  61
  62 // RV32ZKNH-LABEL: @sha512sig1h(
  63 // RV32ZKNH-NEXT:  entry:
  64 // RV32ZKNH-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.sha512sig1h(i32 [[RS1:%.*]], i32 [[RS2:%.*]])
  65 // RV32ZKNH-NEXT:    ret i32 [[TMP0]]
  66 //
  67 uint32_t sha512sig1h(uint32_t rs1, uint32_t rs2) {
  68   return __riscv_sha512sig1h(rs1, rs2);
  69 }
  70
  71 // RV32ZKNH-LABEL: @sha512sig1l(
  72 // RV32ZKNH-NEXT:  entry:
  73 // RV32ZKNH-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.sha512sig1l(i32 [[RS1:%.*]], i32 [[RS2:%.*]])
  74 // RV32ZKNH-NEXT:    ret i32 [[TMP0]]
  75 //
  76 uint32_t sha512sig1l(uint32_t rs1, uint32_t rs2) {
  77   return __riscv_sha512sig1l(rs1, rs2);
  78 }
  79
  80 // RV32ZKNH-LABEL: @sha512sum0r(
  81 // RV32ZKNH-NEXT:  entry:
  82 // RV32ZKNH-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.sha512sum0r(i32 [[RS1:%.*]], i32 [[RS2:%.*]])
  83 // RV32ZKNH-NEXT:    ret i32 [[TMP0]]
  84 //
  85 uint32_t sha512sum0r(uint32_t rs1, uint32_t rs2) {
  86   return __riscv_sha512sum0r(rs1, rs2);
  87 }
  88
  89 // RV32ZKNH-LABEL: @sha512sum1r(
  90 // RV32ZKNH-NEXT:  entry:
  91 // RV32ZKNH-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.sha512sum1r(i32 [[RS1:%.*]], i32 [[RS2:%.*]])
  92 // RV32ZKNH-NEXT:    ret i32 [[TMP0]]
  93 //
  94 uint32_t sha512sum1r(uint32_t rs1, uint32_t rs2) {
  95   return __riscv_sha512sum1r(rs1, rs2);
  96 }