[LLVM][NVPTX] Add support for griddepcontrol instruction (#123511)
[llvm-project.git] / clang / test / CodeGen / RISCV / rvk-intrinsics / riscv64-zknd-zkne.c
blob7f18e732ee41c92398a885b73b2f2c4041af1fd0
1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // RUN: %clang_cc1 -triple riscv64 -target-feature +zknd -emit-llvm %s -o - \
3 // RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
4 // RUN: | FileCheck %s -check-prefix=RV64ZKND-ZKNE
5 // RUN: %clang_cc1 -triple riscv64 -target-feature +zkne -emit-llvm %s -o - \
6 // RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
7 // RUN: | FileCheck %s -check-prefix=RV64ZKND-ZKNE
9 #include <riscv_crypto.h>
11 // RV64ZKND-ZKNE-LABEL: @aes64ks1i(
12 // RV64ZKND-ZKNE-NEXT: entry:
13 // RV64ZKND-ZKNE-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.aes64ks1i(i64 [[RS1:%.*]], i32 0)
14 // RV64ZKND-ZKNE-NEXT: ret i64 [[TMP0]]
16 uint64_t aes64ks1i(uint64_t rs1) {
17 return __riscv_aes64ks1i(rs1, 0);
20 // RV64ZKND-ZKNE-LABEL: @aes64ks2(
21 // RV64ZKND-ZKNE-NEXT: entry:
22 // RV64ZKND-ZKNE-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.aes64ks2(i64 [[RS1:%.*]], i64 [[RS2:%.*]])
23 // RV64ZKND-ZKNE-NEXT: ret i64 [[TMP0]]
25 uint64_t aes64ks2(uint64_t rs1, uint64_t rs2) {
26 return __riscv_aes64ks2(rs1, rs2);