[LLVM][NVPTX] Add support for griddepcontrol instruction (#123511)
[llvm-project.git] / clang / test / CodeGen / RISCV / rvk-intrinsics / riscv64-zkne.c
blob096b2b759aac7ee5e5ffb8aba9643ef384b95fdd
1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // RUN: %clang_cc1 -triple riscv64 -target-feature +zkne -emit-llvm %s -o - \
3 // RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
4 // RUN: | FileCheck %s -check-prefix=RV64ZKNE
6 #include <riscv_crypto.h>
8 // RV64ZKNE-LABEL: @aes64es(
9 // RV64ZKNE-NEXT: entry:
10 // RV64ZKNE-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.aes64es(i64 [[RS1:%.*]], i64 [[RS2:%.*]])
11 // RV64ZKNE-NEXT: ret i64 [[TMP0]]
13 uint64_t aes64es(uint64_t rs1, uint64_t rs2) {
14 return __riscv_aes64es(rs1, rs2);
18 // RV64ZKNE-LABEL: @aes64esm(
19 // RV64ZKNE-NEXT: entry:
20 // RV64ZKNE-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.aes64esm(i64 [[RS1:%.*]], i64 [[RS2:%.*]])
21 // RV64ZKNE-NEXT: ret i64 [[TMP0]]
23 uint64_t aes64esm(uint64_t rs1, uint64_t rs2) {
24 return __riscv_aes64esm(rs1, rs2);