clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlmul_ext_v.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
   2 // REQUIRES: riscv-registered-target
   3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v \
   4 // RUN:   -target-feature +zvfbfmin \
   5 // RUN:   -target-feature +zvfbfwma -disable-O0-optnone \
   6 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
   7 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
   8
   9 #include <riscv_vector.h>
  10
  11 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16mf2(
  12 // CHECK-RV64-SAME: <vscale x 1 x bfloat> [[VALUE:%.*]]) #[[ATTR0:[0-9]+]] {
  13 // CHECK-RV64-NEXT:  entry:
  14 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.vector.insert.nxv2bf16.nxv1bf16(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> [[VALUE]], i64 0)
  15 // CHECK-RV64-NEXT:    ret <vscale x 2 x bfloat> [[TMP0]]
  16 //
  17 vbfloat16mf2_t test_vlmul_ext_v_bf16mf4_bf16mf2(vbfloat16mf4_t value) {
  18   return __riscv_vlmul_ext_v_bf16mf4_bf16mf2(value);
  19 }
  20
  21 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m1(
  22 // CHECK-RV64-SAME: <vscale x 1 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] {
  23 // CHECK-RV64-NEXT:  entry:
  24 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv1bf16(<vscale x 4 x bfloat> poison, <vscale x 1 x bfloat> [[VALUE]], i64 0)
  25 // CHECK-RV64-NEXT:    ret <vscale x 4 x bfloat> [[TMP0]]
  26 //
  27 vbfloat16m1_t test_vlmul_ext_v_bf16mf4_bf16m1(vbfloat16mf4_t value) {
  28   return __riscv_vlmul_ext_v_bf16mf4_bf16m1(value);
  29 }
  30
  31 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m2(
  32 // CHECK-RV64-SAME: <vscale x 1 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] {
  33 // CHECK-RV64-NEXT:  entry:
  34 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv1bf16(<vscale x 8 x bfloat> poison, <vscale x 1 x bfloat> [[VALUE]], i64 0)
  35 // CHECK-RV64-NEXT:    ret <vscale x 8 x bfloat> [[TMP0]]
  36 //
  37 vbfloat16m2_t test_vlmul_ext_v_bf16mf4_bf16m2(vbfloat16mf4_t value) {
  38   return __riscv_vlmul_ext_v_bf16mf4_bf16m2(value);
  39 }
  40
  41 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m4(
  42 // CHECK-RV64-SAME: <vscale x 1 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] {
  43 // CHECK-RV64-NEXT:  entry:
  44 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv1bf16(<vscale x 16 x bfloat> poison, <vscale x 1 x bfloat> [[VALUE]], i64 0)
  45 // CHECK-RV64-NEXT:    ret <vscale x 16 x bfloat> [[TMP0]]
  46 //
  47 vbfloat16m4_t test_vlmul_ext_v_bf16mf4_bf16m4(vbfloat16mf4_t value) {
  48   return __riscv_vlmul_ext_v_bf16mf4_bf16m4(value);
  49 }
  50
  51 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16mf4_bf16m8(
  52 // CHECK-RV64-SAME: <vscale x 1 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] {
  53 // CHECK-RV64-NEXT:  entry:
  54 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv1bf16(<vscale x 32 x bfloat> poison, <vscale x 1 x bfloat> [[VALUE]], i64 0)
  55 // CHECK-RV64-NEXT:    ret <vscale x 32 x bfloat> [[TMP0]]
  56 //
  57 vbfloat16m8_t test_vlmul_ext_v_bf16mf4_bf16m8(vbfloat16mf4_t value) {
  58   return __riscv_vlmul_ext_v_bf16mf4_bf16m8(value);
  59 }
  60
  61 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m1(
  62 // CHECK-RV64-SAME: <vscale x 2 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] {
  63 // CHECK-RV64-NEXT:  entry:
  64 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.vector.insert.nxv4bf16.nxv2bf16(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> [[VALUE]], i64 0)
  65 // CHECK-RV64-NEXT:    ret <vscale x 4 x bfloat> [[TMP0]]
  66 //
  67 vbfloat16m1_t test_vlmul_ext_v_bf16mf2_bf16m1(vbfloat16mf2_t value) {
  68   return __riscv_vlmul_ext_v_bf16mf2_bf16m1(value);
  69 }
  70
  71 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m2(
  72 // CHECK-RV64-SAME: <vscale x 2 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] {
  73 // CHECK-RV64-NEXT:  entry:
  74 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv2bf16(<vscale x 8 x bfloat> poison, <vscale x 2 x bfloat> [[VALUE]], i64 0)
  75 // CHECK-RV64-NEXT:    ret <vscale x 8 x bfloat> [[TMP0]]
  76 //
  77 vbfloat16m2_t test_vlmul_ext_v_bf16mf2_bf16m2(vbfloat16mf2_t value) {
  78   return __riscv_vlmul_ext_v_bf16mf2_bf16m2(value);
  79 }
  80
  81 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m4(
  82 // CHECK-RV64-SAME: <vscale x 2 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] {
  83 // CHECK-RV64-NEXT:  entry:
  84 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv2bf16(<vscale x 16 x bfloat> poison, <vscale x 2 x bfloat> [[VALUE]], i64 0)
  85 // CHECK-RV64-NEXT:    ret <vscale x 16 x bfloat> [[TMP0]]
  86 //
  87 vbfloat16m4_t test_vlmul_ext_v_bf16mf2_bf16m4(vbfloat16mf2_t value) {
  88   return __riscv_vlmul_ext_v_bf16mf2_bf16m4(value);
  89 }
  90
  91 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16mf2_bf16m8(
  92 // CHECK-RV64-SAME: <vscale x 2 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] {
  93 // CHECK-RV64-NEXT:  entry:
  94 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv2bf16(<vscale x 32 x bfloat> poison, <vscale x 2 x bfloat> [[VALUE]], i64 0)
  95 // CHECK-RV64-NEXT:    ret <vscale x 32 x bfloat> [[TMP0]]
  96 //
  97 vbfloat16m8_t test_vlmul_ext_v_bf16mf2_bf16m8(vbfloat16mf2_t value) {
  98   return __riscv_vlmul_ext_v_bf16mf2_bf16m8(value);
  99 }
 100
 101 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m2(
 102 // CHECK-RV64-SAME: <vscale x 4 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] {
 103 // CHECK-RV64-NEXT:  entry:
 104 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.vector.insert.nxv8bf16.nxv4bf16(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> [[VALUE]], i64 0)
 105 // CHECK-RV64-NEXT:    ret <vscale x 8 x bfloat> [[TMP0]]
 106 //
 107 vbfloat16m2_t test_vlmul_ext_v_bf16m1_bf16m2(vbfloat16m1_t value) {
 108   return __riscv_vlmul_ext_v_bf16m1_bf16m2(value);
 109 }
 110
 111 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m4(
 112 // CHECK-RV64-SAME: <vscale x 4 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] {
 113 // CHECK-RV64-NEXT:  entry:
 114 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv4bf16(<vscale x 16 x bfloat> poison, <vscale x 4 x bfloat> [[VALUE]], i64 0)
 115 // CHECK-RV64-NEXT:    ret <vscale x 16 x bfloat> [[TMP0]]
 116 //
 117 vbfloat16m4_t test_vlmul_ext_v_bf16m1_bf16m4(vbfloat16m1_t value) {
 118   return __riscv_vlmul_ext_v_bf16m1_bf16m4(value);
 119 }
 120
 121 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m1_bf16m8(
 122 // CHECK-RV64-SAME: <vscale x 4 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] {
 123 // CHECK-RV64-NEXT:  entry:
 124 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv4bf16(<vscale x 32 x bfloat> poison, <vscale x 4 x bfloat> [[VALUE]], i64 0)
 125 // CHECK-RV64-NEXT:    ret <vscale x 32 x bfloat> [[TMP0]]
 126 //
 127 vbfloat16m8_t test_vlmul_ext_v_bf16m1_bf16m8(vbfloat16m1_t value) {
 128   return __riscv_vlmul_ext_v_bf16m1_bf16m8(value);
 129 }
 130
 131 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vlmul_ext_v_bf16m2_bf16m4(
 132 // CHECK-RV64-SAME: <vscale x 8 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] {
 133 // CHECK-RV64-NEXT:  entry:
 134 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> [[VALUE]], i64 0)
 135 // CHECK-RV64-NEXT:    ret <vscale x 16 x bfloat> [[TMP0]]
 136 //
 137 vbfloat16m4_t test_vlmul_ext_v_bf16m2_bf16m4(vbfloat16m2_t value) {
 138   return __riscv_vlmul_ext_v_bf16m2_bf16m4(value);
 139 }
 140
 141 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m2_bf16m8(
 142 // CHECK-RV64-SAME: <vscale x 8 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] {
 143 // CHECK-RV64-NEXT:  entry:
 144 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv8bf16(<vscale x 32 x bfloat> poison, <vscale x 8 x bfloat> [[VALUE]], i64 0)
 145 // CHECK-RV64-NEXT:    ret <vscale x 32 x bfloat> [[TMP0]]
 146 //
 147 vbfloat16m8_t test_vlmul_ext_v_bf16m2_bf16m8(vbfloat16m2_t value) {
 148   return __riscv_vlmul_ext_v_bf16m2_bf16m8(value);
 149 }
 150
 151 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vlmul_ext_v_bf16m4_bf16m8(
 152 // CHECK-RV64-SAME: <vscale x 16 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] {
 153 // CHECK-RV64-NEXT:  entry:
 154 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.vector.insert.nxv32bf16.nxv16bf16(<vscale x 32 x bfloat> poison, <vscale x 16 x bfloat> [[VALUE]], i64 0)
 155 // CHECK-RV64-NEXT:    ret <vscale x 32 x bfloat> [[TMP0]]
 156 //
 157 vbfloat16m8_t test_vlmul_ext_v_bf16m4_bf16m8(vbfloat16m4_t value) {
 158   return __riscv_vlmul_ext_v_bf16m4_bf16m8(value);
 159 }