clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg5e16.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
   2 // REQUIRES: riscv-registered-target
   3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v \
   4 // RUN:   -target-feature +zvfbfmin \
   5 // RUN:   -target-feature +zvfbfwma -disable-O0-optnone \
   6 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
   7 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
   8
   9 #include <riscv_vector.h>
  10
  11 // CHECK-RV64-LABEL: define dso_local void @test_vsseg5e16_v_bf16mf4x5(
  12 // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
  13 // CHECK-RV64-NEXT:  entry:
  14 // CHECK-RV64-NEXT:    call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[VS3]], ptr [[RS1]], i64 [[VL]], i64 4)
  15 // CHECK-RV64-NEXT:    ret void
  16 //
  17 void test_vsseg5e16_v_bf16mf4x5(__bf16 *rs1, vbfloat16mf4x5_t vs3, size_t vl) {
  18   return __riscv_vsseg5e16_v_bf16mf4x5(rs1, vs3, vl);
  19 }
  20
  21 // CHECK-RV64-LABEL: define dso_local void @test_vsseg5e16_v_bf16mf2x5(
  22 // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  23 // CHECK-RV64-NEXT:  entry:
  24 // CHECK-RV64-NEXT:    call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VS3]], ptr [[RS1]], i64 [[VL]], i64 4)
  25 // CHECK-RV64-NEXT:    ret void
  26 //
  27 void test_vsseg5e16_v_bf16mf2x5(__bf16 *rs1, vbfloat16mf2x5_t vs3, size_t vl) {
  28   return __riscv_vsseg5e16_v_bf16mf2x5(rs1, vs3, vl);
  29 }
  30
  31 // CHECK-RV64-LABEL: define dso_local void @test_vsseg5e16_v_bf16m1x5(
  32 // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  33 // CHECK-RV64-NEXT:  entry:
  34 // CHECK-RV64-NEXT:    call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[VS3]], ptr [[RS1]], i64 [[VL]], i64 4)
  35 // CHECK-RV64-NEXT:    ret void
  36 //
  37 void test_vsseg5e16_v_bf16m1x5(__bf16 *rs1, vbfloat16m1x5_t vs3, size_t vl) {
  38   return __riscv_vsseg5e16_v_bf16m1x5(rs1, vs3, vl);
  39 }
  40
  41 // CHECK-RV64-LABEL: define dso_local void @test_vsseg5e16_v_bf16mf4x5_m(
  42 // CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  43 // CHECK-RV64-NEXT:  entry:
  44 // CHECK-RV64-NEXT:    call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) [[VS3]], ptr [[RS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 4)
  45 // CHECK-RV64-NEXT:    ret void
  46 //
  47 void test_vsseg5e16_v_bf16mf4x5_m(vbool64_t vm, __bf16 *rs1,
  48                                   vbfloat16mf4x5_t vs3, size_t vl) {
  49   return __riscv_vsseg5e16_v_bf16mf4x5_m(vm, rs1, vs3, vl);
  50 }
  51
  52 // CHECK-RV64-LABEL: define dso_local void @test_vsseg5e16_v_bf16mf2x5_m(
  53 // CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  54 // CHECK-RV64-NEXT:  entry:
  55 // CHECK-RV64-NEXT:    call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv2i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VS3]], ptr [[RS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 4)
  56 // CHECK-RV64-NEXT:    ret void
  57 //
  58 void test_vsseg5e16_v_bf16mf2x5_m(vbool32_t vm, __bf16 *rs1,
  59                                   vbfloat16mf2x5_t vs3, size_t vl) {
  60   return __riscv_vsseg5e16_v_bf16mf2x5_m(vm, rs1, vs3, vl);
  61 }
  62
  63 // CHECK-RV64-LABEL: define dso_local void @test_vsseg5e16_v_bf16m1x5_m(
  64 // CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  65 // CHECK-RV64-NEXT:  entry:
  66 // CHECK-RV64-NEXT:    call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv4i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) [[VS3]], ptr [[RS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 4)
  67 // CHECK-RV64-NEXT:    ret void
  68 //
  69 void test_vsseg5e16_v_bf16m1x5_m(vbool16_t vm, __bf16 *rs1, vbfloat16m1x5_t vs3,
  70                                  size_t vl) {
  71   return __riscv_vsseg5e16_v_bf16m1x5_m(vm, rs1, vs3, vl);
  72 }