clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg7e16.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
   2 // REQUIRES: riscv-registered-target
   3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v \
   4 // RUN:   -target-feature +zvfbfmin \
   5 // RUN:   -target-feature +zvfbfwma -disable-O0-optnone \
   6 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
   7 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
   8
   9 #include <riscv_vector.h>
  10
  11 // CHECK-RV64-LABEL: define dso_local void @test_vssseg7e16_v_bf16mf4x7(
  12 // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], target("riscv.vector.tuple", <vscale x 2 x i8>, 7) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
  13 // CHECK-RV64-NEXT:  entry:
  14 // CHECK-RV64-NEXT:    call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) [[VS3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]], i64 4)
  15 // CHECK-RV64-NEXT:    ret void
  16 //
  17 void test_vssseg7e16_v_bf16mf4x7(__bf16 *rs1, ptrdiff_t rs2,
  18                                  vbfloat16mf4x7_t vs3, size_t vl) {
  19   return __riscv_vssseg7e16_v_bf16mf4x7(rs1, rs2, vs3, vl);
  20 }
  21
  22 // CHECK-RV64-LABEL: define dso_local void @test_vssseg7e16_v_bf16mf2x7(
  23 // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  24 // CHECK-RV64-NEXT:  entry:
  25 // CHECK-RV64-NEXT:    call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[VS3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]], i64 4)
  26 // CHECK-RV64-NEXT:    ret void
  27 //
  28 void test_vssseg7e16_v_bf16mf2x7(__bf16 *rs1, ptrdiff_t rs2,
  29                                  vbfloat16mf2x7_t vs3, size_t vl) {
  30   return __riscv_vssseg7e16_v_bf16mf2x7(rs1, rs2, vs3, vl);
  31 }
  32
  33 // CHECK-RV64-LABEL: define dso_local void @test_vssseg7e16_v_bf16m1x7(
  34 // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  35 // CHECK-RV64-NEXT:  entry:
  36 // CHECK-RV64-NEXT:    call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[VS3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]], i64 4)
  37 // CHECK-RV64-NEXT:    ret void
  38 //
  39 void test_vssseg7e16_v_bf16m1x7(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m1x7_t vs3,
  40                                 size_t vl) {
  41   return __riscv_vssseg7e16_v_bf16m1x7(rs1, rs2, vs3, vl);
  42 }
  43
  44 // CHECK-RV64-LABEL: define dso_local void @test_vssseg7e16_v_bf16mf4x7_m(
  45 // CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], target("riscv.vector.tuple", <vscale x 2 x i8>, 7) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  46 // CHECK-RV64-NEXT:  entry:
  47 // CHECK-RV64-NEXT:    call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) [[VS3]], ptr [[RS1]], i64 [[RS2]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 4)
  48 // CHECK-RV64-NEXT:    ret void
  49 //
  50 void test_vssseg7e16_v_bf16mf4x7_m(vbool64_t vm, __bf16 *rs1, ptrdiff_t rs2,
  51                                    vbfloat16mf4x7_t vs3, size_t vl) {
  52   return __riscv_vssseg7e16_v_bf16mf4x7_m(vm, rs1, rs2, vs3, vl);
  53 }
  54
  55 // CHECK-RV64-LABEL: define dso_local void @test_vssseg7e16_v_bf16mf2x7_m(
  56 // CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  57 // CHECK-RV64-NEXT:  entry:
  58 // CHECK-RV64-NEXT:    call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[VS3]], ptr [[RS1]], i64 [[RS2]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 4)
  59 // CHECK-RV64-NEXT:    ret void
  60 //
  61 void test_vssseg7e16_v_bf16mf2x7_m(vbool32_t vm, __bf16 *rs1, ptrdiff_t rs2,
  62                                    vbfloat16mf2x7_t vs3, size_t vl) {
  63   return __riscv_vssseg7e16_v_bf16mf2x7_m(vm, rs1, rs2, vs3, vl);
  64 }
  65
  66 // CHECK-RV64-LABEL: define dso_local void @test_vssseg7e16_v_bf16m1x7_m(
  67 // CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  68 // CHECK-RV64-NEXT:  entry:
  69 // CHECK-RV64-NEXT:    call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[VS3]], ptr [[RS1]], i64 [[RS2]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 4)
  70 // CHECK-RV64-NEXT:    ret void
  71 //
  72 void test_vssseg7e16_v_bf16m1x7_m(vbool16_t vm, __bf16 *rs1, ptrdiff_t rs2,
  73                                   vbfloat16m1x7_t vs3, size_t vl) {
  74   return __riscv_vssseg7e16_v_bf16m1x7_m(vm, rs1, rs2, vs3, vl);
  75 }