clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxei16.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
   2 // REQUIRES: riscv-registered-target
   3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v \
   4 // RUN:   -target-feature +zvfbfmin \
   5 // RUN:   -target-feature +zvfbfwma -disable-O0-optnone \
   6 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
   7 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
   8
   9 #include <riscv_vector.h>
  10
  11 // CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16mf4(
  12 // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 1 x i16> [[RS2:%.*]], <vscale x 1 x bfloat> [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
  13 // CHECK-RV64-NEXT:  entry:
  14 // CHECK-RV64-NEXT:    call void @llvm.riscv.vsuxei.nxv1bf16.nxv1i16.i64(<vscale x 1 x bfloat> [[VS3]], ptr [[RS1]], <vscale x 1 x i16> [[RS2]], i64 [[VL]])
  15 // CHECK-RV64-NEXT:    ret void
  16 //
  17 void test_vsuxei16_v_bf16mf4(__bf16 *rs1, vuint16mf4_t rs2, vbfloat16mf4_t vs3,
  18                              size_t vl) {
  19   return __riscv_vsuxei16_v_bf16mf4(rs1, rs2, vs3, vl);
  20 }
  21
  22 // CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16mf2(
  23 // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 2 x i16> [[RS2:%.*]], <vscale x 2 x bfloat> [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  24 // CHECK-RV64-NEXT:  entry:
  25 // CHECK-RV64-NEXT:    call void @llvm.riscv.vsuxei.nxv2bf16.nxv2i16.i64(<vscale x 2 x bfloat> [[VS3]], ptr [[RS1]], <vscale x 2 x i16> [[RS2]], i64 [[VL]])
  26 // CHECK-RV64-NEXT:    ret void
  27 //
  28 void test_vsuxei16_v_bf16mf2(__bf16 *rs1, vuint16mf2_t rs2, vbfloat16mf2_t vs3,
  29                              size_t vl) {
  30   return __riscv_vsuxei16_v_bf16mf2(rs1, rs2, vs3, vl);
  31 }
  32
  33 // CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16m1(
  34 // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 4 x i16> [[RS2:%.*]], <vscale x 4 x bfloat> [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  35 // CHECK-RV64-NEXT:  entry:
  36 // CHECK-RV64-NEXT:    call void @llvm.riscv.vsuxei.nxv4bf16.nxv4i16.i64(<vscale x 4 x bfloat> [[VS3]], ptr [[RS1]], <vscale x 4 x i16> [[RS2]], i64 [[VL]])
  37 // CHECK-RV64-NEXT:    ret void
  38 //
  39 void test_vsuxei16_v_bf16m1(__bf16 *rs1, vuint16m1_t rs2, vbfloat16m1_t vs3,
  40                             size_t vl) {
  41   return __riscv_vsuxei16_v_bf16m1(rs1, rs2, vs3, vl);
  42 }
  43
  44 // CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16m2(
  45 // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 8 x i16> [[RS2:%.*]], <vscale x 8 x bfloat> [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  46 // CHECK-RV64-NEXT:  entry:
  47 // CHECK-RV64-NEXT:    call void @llvm.riscv.vsuxei.nxv8bf16.nxv8i16.i64(<vscale x 8 x bfloat> [[VS3]], ptr [[RS1]], <vscale x 8 x i16> [[RS2]], i64 [[VL]])
  48 // CHECK-RV64-NEXT:    ret void
  49 //
  50 void test_vsuxei16_v_bf16m2(__bf16 *rs1, vuint16m2_t rs2, vbfloat16m2_t vs3,
  51                             size_t vl) {
  52   return __riscv_vsuxei16_v_bf16m2(rs1, rs2, vs3, vl);
  53 }
  54
  55 // CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16m4(
  56 // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 16 x i16> [[RS2:%.*]], <vscale x 16 x bfloat> [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  57 // CHECK-RV64-NEXT:  entry:
  58 // CHECK-RV64-NEXT:    call void @llvm.riscv.vsuxei.nxv16bf16.nxv16i16.i64(<vscale x 16 x bfloat> [[VS3]], ptr [[RS1]], <vscale x 16 x i16> [[RS2]], i64 [[VL]])
  59 // CHECK-RV64-NEXT:    ret void
  60 //
  61 void test_vsuxei16_v_bf16m4(__bf16 *rs1, vuint16m4_t rs2, vbfloat16m4_t vs3,
  62                             size_t vl) {
  63   return __riscv_vsuxei16_v_bf16m4(rs1, rs2, vs3, vl);
  64 }
  65
  66 // CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16m8(
  67 // CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], <vscale x 32 x i16> [[RS2:%.*]], <vscale x 32 x bfloat> [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  68 // CHECK-RV64-NEXT:  entry:
  69 // CHECK-RV64-NEXT:    call void @llvm.riscv.vsuxei.nxv32bf16.nxv32i16.i64(<vscale x 32 x bfloat> [[VS3]], ptr [[RS1]], <vscale x 32 x i16> [[RS2]], i64 [[VL]])
  70 // CHECK-RV64-NEXT:    ret void
  71 //
  72 void test_vsuxei16_v_bf16m8(__bf16 *rs1, vuint16m8_t rs2, vbfloat16m8_t vs3,
  73                             size_t vl) {
  74   return __riscv_vsuxei16_v_bf16m8(rs1, rs2, vs3, vl);
  75 }
  76
  77 // CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16mf4_m(
  78 // CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 1 x i16> [[RS2:%.*]], <vscale x 1 x bfloat> [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  79 // CHECK-RV64-NEXT:  entry:
  80 // CHECK-RV64-NEXT:    call void @llvm.riscv.vsuxei.mask.nxv1bf16.nxv1i16.i64(<vscale x 1 x bfloat> [[VS3]], ptr [[RS1]], <vscale x 1 x i16> [[RS2]], <vscale x 1 x i1> [[VM]], i64 [[VL]])
  81 // CHECK-RV64-NEXT:    ret void
  82 //
  83 void test_vsuxei16_v_bf16mf4_m(vbool64_t vm, __bf16 *rs1, vuint16mf4_t rs2,
  84                                vbfloat16mf4_t vs3, size_t vl) {
  85   return __riscv_vsuxei16_v_bf16mf4_m(vm, rs1, rs2, vs3, vl);
  86 }
  87
  88 // CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16mf2_m(
  89 // CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 2 x i16> [[RS2:%.*]], <vscale x 2 x bfloat> [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  90 // CHECK-RV64-NEXT:  entry:
  91 // CHECK-RV64-NEXT:    call void @llvm.riscv.vsuxei.mask.nxv2bf16.nxv2i16.i64(<vscale x 2 x bfloat> [[VS3]], ptr [[RS1]], <vscale x 2 x i16> [[RS2]], <vscale x 2 x i1> [[VM]], i64 [[VL]])
  92 // CHECK-RV64-NEXT:    ret void
  93 //
  94 void test_vsuxei16_v_bf16mf2_m(vbool32_t vm, __bf16 *rs1, vuint16mf2_t rs2,
  95                                vbfloat16mf2_t vs3, size_t vl) {
  96   return __riscv_vsuxei16_v_bf16mf2_m(vm, rs1, rs2, vs3, vl);
  97 }
  98
  99 // CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16m1_m(
 100 // CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 4 x i16> [[RS2:%.*]], <vscale x 4 x bfloat> [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 101 // CHECK-RV64-NEXT:  entry:
 102 // CHECK-RV64-NEXT:    call void @llvm.riscv.vsuxei.mask.nxv4bf16.nxv4i16.i64(<vscale x 4 x bfloat> [[VS3]], ptr [[RS1]], <vscale x 4 x i16> [[RS2]], <vscale x 4 x i1> [[VM]], i64 [[VL]])
 103 // CHECK-RV64-NEXT:    ret void
 104 //
 105 void test_vsuxei16_v_bf16m1_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t rs2,
 106                               vbfloat16m1_t vs3, size_t vl) {
 107   return __riscv_vsuxei16_v_bf16m1_m(vm, rs1, rs2, vs3, vl);
 108 }
 109
 110 // CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16m2_m(
 111 // CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 8 x i16> [[RS2:%.*]], <vscale x 8 x bfloat> [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 112 // CHECK-RV64-NEXT:  entry:
 113 // CHECK-RV64-NEXT:    call void @llvm.riscv.vsuxei.mask.nxv8bf16.nxv8i16.i64(<vscale x 8 x bfloat> [[VS3]], ptr [[RS1]], <vscale x 8 x i16> [[RS2]], <vscale x 8 x i1> [[VM]], i64 [[VL]])
 114 // CHECK-RV64-NEXT:    ret void
 115 //
 116 void test_vsuxei16_v_bf16m2_m(vbool8_t vm, __bf16 *rs1, vuint16m2_t rs2,
 117                               vbfloat16m2_t vs3, size_t vl) {
 118   return __riscv_vsuxei16_v_bf16m2_m(vm, rs1, rs2, vs3, vl);
 119 }
 120
 121 // CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16m4_m(
 122 // CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 16 x i16> [[RS2:%.*]], <vscale x 16 x bfloat> [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 123 // CHECK-RV64-NEXT:  entry:
 124 // CHECK-RV64-NEXT:    call void @llvm.riscv.vsuxei.mask.nxv16bf16.nxv16i16.i64(<vscale x 16 x bfloat> [[VS3]], ptr [[RS1]], <vscale x 16 x i16> [[RS2]], <vscale x 16 x i1> [[VM]], i64 [[VL]])
 125 // CHECK-RV64-NEXT:    ret void
 126 //
 127 void test_vsuxei16_v_bf16m4_m(vbool4_t vm, __bf16 *rs1, vuint16m4_t rs2,
 128                               vbfloat16m4_t vs3, size_t vl) {
 129   return __riscv_vsuxei16_v_bf16m4_m(vm, rs1, rs2, vs3, vl);
 130 }
 131
 132 // CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16m8_m(
 133 // CHECK-RV64-SAME: <vscale x 32 x i1> [[VM:%.*]], ptr noundef [[RS1:%.*]], <vscale x 32 x i16> [[RS2:%.*]], <vscale x 32 x bfloat> [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
 134 // CHECK-RV64-NEXT:  entry:
 135 // CHECK-RV64-NEXT:    call void @llvm.riscv.vsuxei.mask.nxv32bf16.nxv32i16.i64(<vscale x 32 x bfloat> [[VS3]], ptr [[RS1]], <vscale x 32 x i16> [[RS2]], <vscale x 32 x i1> [[VM]], i64 [[VL]])
 136 // CHECK-RV64-NEXT:    ret void
 137 //
 138 void test_vsuxei16_v_bf16m8_m(vbool2_t vm, __bf16 *rs1, vuint16m8_t rs2,
 139                               vbfloat16m8_t vs3, size_t vl) {
 140   return __riscv_vsuxei16_v_bf16m8_m(vm, rs1, rs2, vs3, vl);
 141 }