clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
   2 // REQUIRES: riscv-registered-target
   3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
   4 // RUN:   -target-feature +zvfh -disable-O0-optnone  \
   5 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
   6 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
   7
   8 #include <riscv_vector.h>
   9
  10 // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vmmv_m_b1
  11 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
  12 // CHECK-RV64-NEXT:  entry:
  13 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> [[OP1]], <vscale x 64 x i1> [[OP1]], i64 [[VL]])
  14 // CHECK-RV64-NEXT:    ret <vscale x 64 x i1> [[TMP0]]
  15 //
  16 vbool1_t test_vmmv_m_b1(vbool1_t op1, size_t vl) {
  17   return __riscv_vmmv_m_b1(op1, vl);
  18 }
  19
  20 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vmmv_m_b2
  21 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  22 // CHECK-RV64-NEXT:  entry:
  23 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> [[OP1]], <vscale x 32 x i1> [[OP1]], i64 [[VL]])
  24 // CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]
  25 //
  26 vbool2_t test_vmmv_m_b2(vbool2_t op1, size_t vl) {
  27   return __riscv_vmmv_m_b2(op1, vl);
  28 }
  29
  30 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vmmv_m_b4
  31 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  32 // CHECK-RV64-NEXT:  entry:
  33 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> [[OP1]], <vscale x 16 x i1> [[OP1]], i64 [[VL]])
  34 // CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
  35 //
  36 vbool4_t test_vmmv_m_b4(vbool4_t op1, size_t vl) {
  37   return __riscv_vmmv_m_b4(op1, vl);
  38 }
  39
  40 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vmmv_m_b8
  41 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  42 // CHECK-RV64-NEXT:  entry:
  43 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> [[OP1]], <vscale x 8 x i1> [[OP1]], i64 [[VL]])
  44 // CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]
  45 //
  46 vbool8_t test_vmmv_m_b8(vbool8_t op1, size_t vl) {
  47   return __riscv_vmmv_m_b8(op1, vl);
  48 }
  49
  50 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vmmv_m_b16
  51 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  52 // CHECK-RV64-NEXT:  entry:
  53 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> [[OP1]], <vscale x 4 x i1> [[OP1]], i64 [[VL]])
  54 // CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]
  55 //
  56 vbool16_t test_vmmv_m_b16(vbool16_t op1, size_t vl) {
  57   return __riscv_vmmv_m_b16(op1, vl);
  58 }
  59
  60 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vmmv_m_b32
  61 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  62 // CHECK-RV64-NEXT:  entry:
  63 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> [[OP1]], <vscale x 2 x i1> [[OP1]], i64 [[VL]])
  64 // CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]
  65 //
  66 vbool32_t test_vmmv_m_b32(vbool32_t op1, size_t vl) {
  67   return __riscv_vmmv_m_b32(op1, vl);
  68 }
  69
  70 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vmmv_m_b64
  71 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  72 // CHECK-RV64-NEXT:  entry:
  73 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> [[OP1]], <vscale x 1 x i1> [[OP1]], i64 [[VL]])
  74 // CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]
  75 //
  76 vbool64_t test_vmmv_m_b64(vbool64_t op1, size_t vl) {
  77   return __riscv_vmmv_m_b64(op1, vl);
  78 }
  79