clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
   2 // REQUIRES: riscv-registered-target
   3 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
   4 // RUN:   -target-feature +zvfh -disable-O0-optnone  \
   5 // RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
   6 // RUN:   FileCheck --check-prefix=CHECK-RV64 %s
   7
   8 #include <riscv_vector.h>
   9
  10 // CHECK-RV64-LABEL: define dso_local void @test_vsseg7e64_v_f64m1x7
  11 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
  12 // CHECK-RV64-NEXT:  entry:
  13 // CHECK-RV64-NEXT:    call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[V_TUPLE]], ptr [[BASE]], i64 [[VL]], i64 6)
  14 // CHECK-RV64-NEXT:    ret void
  15 //
  16 void test_vsseg7e64_v_f64m1x7(double *base, vfloat64m1x7_t v_tuple, size_t vl) {
  17   return __riscv_vsseg7e64(base, v_tuple, vl);
  18 }
  19
  20 // CHECK-RV64-LABEL: define dso_local void @test_vsseg7e64_v_i64m1x7
  21 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  22 // CHECK-RV64-NEXT:  entry:
  23 // CHECK-RV64-NEXT:    call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[V_TUPLE]], ptr [[BASE]], i64 [[VL]], i64 6)
  24 // CHECK-RV64-NEXT:    ret void
  25 //
  26 void test_vsseg7e64_v_i64m1x7(int64_t *base, vint64m1x7_t v_tuple, size_t vl) {
  27   return __riscv_vsseg7e64(base, v_tuple, vl);
  28 }
  29
  30 // CHECK-RV64-LABEL: define dso_local void @test_vsseg7e64_v_u64m1x7
  31 // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  32 // CHECK-RV64-NEXT:  entry:
  33 // CHECK-RV64-NEXT:    call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[V_TUPLE]], ptr [[BASE]], i64 [[VL]], i64 6)
  34 // CHECK-RV64-NEXT:    ret void
  35 //
  36 void test_vsseg7e64_v_u64m1x7(uint64_t *base, vuint64m1x7_t v_tuple, size_t vl) {
  37   return __riscv_vsseg7e64(base, v_tuple, vl);
  38 }
  39
  40 // CHECK-RV64-LABEL: define dso_local void @test_vsseg7e64_v_f64m1x7_m
  41 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  42 // CHECK-RV64-NEXT:  entry:
  43 // CHECK-RV64-NEXT:    call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[V_TUPLE]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 6)
  44 // CHECK-RV64-NEXT:    ret void
  45 //
  46 void test_vsseg7e64_v_f64m1x7_m(vbool64_t mask, double *base, vfloat64m1x7_t v_tuple, size_t vl) {
  47   return __riscv_vsseg7e64(mask, base, v_tuple, vl);
  48 }
  49
  50 // CHECK-RV64-LABEL: define dso_local void @test_vsseg7e64_v_i64m1x7_m
  51 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  52 // CHECK-RV64-NEXT:  entry:
  53 // CHECK-RV64-NEXT:    call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[V_TUPLE]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 6)
  54 // CHECK-RV64-NEXT:    ret void
  55 //
  56 void test_vsseg7e64_v_i64m1x7_m(vbool64_t mask, int64_t *base, vint64m1x7_t v_tuple, size_t vl) {
  57   return __riscv_vsseg7e64(mask, base, v_tuple, vl);
  58 }
  59
  60 // CHECK-RV64-LABEL: define dso_local void @test_vsseg7e64_v_u64m1x7_m
  61 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[V_TUPLE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
  62 // CHECK-RV64-NEXT:  entry:
  63 // CHECK-RV64-NEXT:    call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) [[V_TUPLE]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 6)
  64 // CHECK-RV64-NEXT:    ret void
  65 //
  66 void test_vsseg7e64_v_u64m1x7_m(vbool64_t mask, uint64_t *base, vuint64m1x7_t v_tuple, size_t vl) {
  67   return __riscv_vsseg7e64(mask, base, v_tuple, vl);
  68 }
  69