clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals
   2 // REQUIRES: riscv-registered-target
   3 // RUN: %clang_cc1 -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -Qn %s -o - \
   4 // RUN:     | opt -S -O2 | FileCheck --check-prefix=RV32 %s
   5 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm -Qn %s -o - \
   6 // RUN:     | opt -S -O2 | FileCheck --check-prefix=RV64 %s
   7
   8 #include <riscv_vector.h>
   9
  10 // RV32-LABEL: @test_vlenb(
  11 // RV32-NEXT:  entry:
  12 // RV32-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.read_register.i32(metadata [[META3:![0-9]+]])
  13 // RV32-NEXT:    ret i32 [[TMP0]]
  14 //
  15 // RV64-LABEL: @test_vlenb(
  16 // RV64-NEXT:  entry:
  17 // RV64-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.read_register.i64(metadata [[META3:![0-9]+]])
  18 // RV64-NEXT:    ret i64 [[TMP0]]
  19 //
  20 unsigned long test_vlenb(void) {
  21   return __riscv_vlenb();
  22 }
  23 //.
  24 // RV32: attributes #[[ATTR0:[0-9]+]] = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
  25 // RV32: attributes #[[ATTR1:[0-9]+]] = { mustprogress nocallback nofree nosync nounwind willreturn memory(read) }
  26 //.
  27 // RV64: attributes #[[ATTR0:[0-9]+]] = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
  28 // RV64: attributes #[[ATTR1:[0-9]+]] = { mustprogress nocallback nofree nosync nounwind willreturn memory(read) }
  29 //.
  30 // RV32: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
  31 // RV32: [[META1:![0-9]+]] = !{i32 1, !"target-abi", !"ilp32d"}
  32 // RV32: [[META2:![0-9]+]] = !{i32 8, !"SmallDataLimit", i32 0}
  33 // RV32: [[META3]] = !{!"vlenb"}
  34 //.
  35 // RV64: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
  36 // RV64: [[META1:![0-9]+]] = !{i32 1, !"target-abi", !"lp64d"}
  37 // RV64: [[META2:![0-9]+]] = !{i32 8, !"SmallDataLimit", i32 0}
  38 // RV64: [[META3]] = !{!"vlenb"}
  39 //.