clang/test/CodeGen/attr-target-version.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals --include-generated-funcs --global-value-regex ".*"
   2 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | FileCheck %s
   3 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -fmv -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK-NOFMV
   4
   5 int __attribute__((target_version("rng+flagm+fp16fml"))) fmv(void) { return 1; }
   6 int __attribute__((target_version("flagm2+sme-i16i64"))) fmv(void) { return 2; }
   7 int __attribute__((target_version("lse+sha2"))) fmv(void) { return 3; }
   8 int __attribute__((target_version("dotprod+ls64"))) fmv(void) { return 4; }
   9 int __attribute__((target_version("fp16fml+memtag"))) fmv(void) { return 5; }
  10 int __attribute__((target_version("fp+aes"))) fmv(void) { return 6; }
  11 int __attribute__((target_version("crc+ls64"))) fmv(void) { return 7; }
  12 int __attribute__((target_version("bti"))) fmv(void) { return 8; }
  13 int __attribute__((target_version("sme2"))) fmv(void) { return 9; }
  14 int __attribute__((target_version("default"))) fmv(void) { return 0; }
  15 int __attribute__((target_version("ls64+simd"))) fmv_one(void) { return 1; }
  16 int __attribute__((target_version("dpb"))) fmv_one(void) { return 2; }
  17 int __attribute__((target_version("default"))) fmv_one(void) { return 0; }
  18 int __attribute__((target_version("fp"))) fmv_two(void) { return 1; }
  19 int __attribute__((target_version("simd"))) fmv_two(void) { return 2; }
  20 int __attribute__((target_version("fp16+simd"))) fmv_two(void) { return 4; }
  21 int __attribute__((target_version("default"))) fmv_two(void) { return 0; }
  22 int foo() {
  23   return fmv()+fmv_one()+fmv_two();
  24 }
  25
  26 inline int __attribute__((target_version("sha2+aes+f64mm"))) fmv_inline(void) { return 1; }
  27 inline int __attribute__((target_version("fp16+fcma+rdma+sme+ fp16 "))) fmv_inline(void) { return 2; }
  28 inline int __attribute__((target_version("sha3+i8mm+f32mm"))) fmv_inline(void) { return 12; }
  29 inline int __attribute__((target_version("dit+bf16"))) fmv_inline(void) { return 8; }
  30 inline int __attribute__((target_version("dpb+rcpc2 "))) fmv_inline(void) { return 6; }
  31 inline int __attribute__((target_version(" dpb2 + jscvt"))) fmv_inline(void) { return 7; }
  32 inline int __attribute__((target_version("rcpc+frintts"))) fmv_inline(void) { return 3; }
  33 inline int __attribute__((target_version("sve+bf16"))) fmv_inline(void) { return 4; }
  34 inline int __attribute__((target_version("sve2-aes+sve2-sha3"))) fmv_inline(void) { return 5; }
  35 inline int __attribute__((target_version("sve2+sve2-aes+sve2-bitperm"))) fmv_inline(void) { return 9; }
  36 inline int __attribute__((target_version("sve2-sm4+memtag"))) fmv_inline(void) { return 10; }
  37 inline int __attribute__((target_version("memtag+rcpc3+mops"))) fmv_inline(void) { return 11; }
  38 inline int __attribute__((target_version("aes+dotprod"))) fmv_inline(void) { return 13; }
  39 inline int __attribute__((target_version("simd+fp16fml"))) fmv_inline(void) { return 14; }
  40 inline int __attribute__((target_version("fp+sm4"))) fmv_inline(void) { return 15; }
  41 inline int __attribute__((target_version("lse+rdm"))) fmv_inline(void) { return 16; }
  42 inline int __attribute__((target_version("default"))) fmv_inline(void) { return 3; }
  43
  44 __attribute__((target_version("ls64"))) int fmv_e(void);
  45 int fmv_e(void) { return 20; }
  46
  47 static __attribute__((target_version("sb"))) inline int fmv_d(void);
  48 static __attribute__((target_version("default"))) inline int fmv_d(void);
  49
  50 int __attribute__((target_version("default"))) fmv_default(void) { return 111; }
  51 int fmv_default(void);
  52
  53 void fmv_c(void);
  54 void __attribute__((target_version("ssbs"))) fmv_c(void){};
  55 void __attribute__((target_version("default"))) fmv_c(void){};
  56
  57 int goo() {
  58   fmv_inline();
  59   fmv_e();
  60   fmv_d();
  61   fmv_c();
  62   return fmv_default();
  63 }
  64 static inline int __attribute__((target_version("sb"))) fmv_d(void) { return 0; }
  65 static inline int __attribute__((target_version(" default "))) fmv_d(void) { return 1; }
  66
  67 static void func(void) {}
  68 inline __attribute__((target_version("default"))) void recb(void) { func(); }
  69 inline __attribute__((target_version("default"))) void reca(void) { recb(); }
  70 void recur(void) { reca(); }
  71
  72 int __attribute__((target_version("default"))) main(void) {
  73   recur();
  74   return goo();
  75 }
  76
  77 typedef int (*Fptr)();
  78 void f(Fptr);
  79 int hoo(void) {
  80   f(fmv);
  81   Fptr fp1 = &fmv;
  82   Fptr fp2 = fmv;
  83   return fp1() + fp2();
  84 }
  85
  86 // This should generate one target version but no resolver.
  87 __attribute__((target_version("default"))) int unused_with_forward_default_decl(void);
  88 __attribute__((target_version("mops"))) int unused_with_forward_default_decl(void) { return 0; }
  89
  90 // This should also generate one target version but no resolver.
  91 extern int unused_with_implicit_extern_forward_default_decl(void);
  92 __attribute__((target_version("dotprod")))
  93 int unused_with_implicit_extern_forward_default_decl(void) { return 0; }
  94
  95 // This should also generate one target version but no resolver.
  96 __attribute__((target_version("aes"))) int unused_with_default_decl(void) { return 0; }
  97 __attribute__((target_version("default"))) int unused_with_default_decl(void);
  98
  99 // This should generate two target versions and the resolver.
 100 __attribute__((target_version("sve"))) int unused_with_default_def(void) { return 0; }
 101 __attribute__((target_version("default"))) int unused_with_default_def(void) { return 1; }
 102
 103 // This should also generate two target versions and the resolver.
 104 __attribute__((target_version("fp16"))) int unused_with_implicit_default_def(void) { return 0; }
 105 int unused_with_implicit_default_def(void) { return 1; }
 106
 107 // This should also generate two target versions and the resolver.
 108 int unused_with_implicit_forward_default_def(void) { return 0; }
 109 __attribute__((target_version("lse"))) int unused_with_implicit_forward_default_def(void) { return 1; }
 110
 111 // This should generate a target version despite the default not being declared.
 112 __attribute__((target_version("rdm"))) int unused_without_default(void) { return 0; }
 113
 114 // These shouldn't generate anything.
 115 int unused_version_declarations(void);
 116 __attribute__((target_version("jscvt"))) int unused_version_declarations(void);
 117 __attribute__((target_version("rdma"))) int unused_version_declarations(void);
 118
 119 // These should generate the default (mangled) version and the resolver.
 120 int default_def_with_version_decls(void) { return 0; }
 121 __attribute__((target_version("jscvt"))) int default_def_with_version_decls(void);
 122 __attribute__((target_version("rdma"))) int default_def_with_version_decls(void);
 123
 124 // The following is guarded because in NOFMV we get errors for calling undeclared functions.
 125 #ifdef __HAVE_FUNCTION_MULTI_VERSIONING
 126 // This should generate a default declaration, two target versions but no resolver.
 127 __attribute__((target_version("jscvt"))) int used_def_without_default_decl(void) { return 1; }
 128 __attribute__((target_version("rdma"))) int used_def_without_default_decl(void) { return 2; }
 129
 130 // This should generate a default declaration but no resolver.
 131 __attribute__((target_version("jscvt"))) int used_decl_without_default_decl(void);
 132 __attribute__((target_version("rdma"))) int used_decl_without_default_decl(void);
 133
 134 int caller(void) { return used_def_without_default_decl() + used_decl_without_default_decl(); }
 135 #endif
 136
 137 //.
 138 // CHECK: @__aarch64_cpu_features = external dso_local global { i64 }
 139 // CHECK: @fmv = weak_odr ifunc i32 (), ptr @fmv.resolver
 140 // CHECK: @fmv_one = weak_odr ifunc i32 (), ptr @fmv_one.resolver
 141 // CHECK: @fmv_two = weak_odr ifunc i32 (), ptr @fmv_two.resolver
 142 // CHECK: @fmv_e = weak_odr ifunc i32 (), ptr @fmv_e.resolver
 143 // CHECK: @fmv_d = internal ifunc i32 (), ptr @fmv_d.resolver
 144 // CHECK: @fmv_c = weak_odr ifunc void (), ptr @fmv_c.resolver
 145 // CHECK: @fmv_inline = weak_odr ifunc i32 (), ptr @fmv_inline.resolver
 146 // CHECK: @reca = weak_odr ifunc void (), ptr @reca.resolver
 147 // CHECK: @unused_with_default_def = weak_odr ifunc i32 (), ptr @unused_with_default_def.resolver
 148 // CHECK: @unused_with_implicit_default_def = weak_odr ifunc i32 (), ptr @unused_with_implicit_default_def.resolver
 149 // CHECK: @unused_with_implicit_forward_default_def = weak_odr ifunc i32 (), ptr @unused_with_implicit_forward_default_def.resolver
 150 // CHECK: @default_def_with_version_decls = weak_odr ifunc i32 (), ptr @default_def_with_version_decls.resolver
 151 // CHECK: @recb = weak_odr ifunc void (), ptr @recb.resolver
 152 //.
 153 // CHECK: Function Attrs: noinline nounwind optnone
 154 // CHECK-LABEL: define {{[^@]+}}@fmv._MflagmMfp16fmlMrng
 155 // CHECK-SAME: () #[[ATTR0:[0-9]+]] {
 156 // CHECK-NEXT:  entry:
 157 // CHECK-NEXT:    ret i32 1
 158 //
 159 //
 160 // CHECK: Function Attrs: noinline nounwind optnone
 161 // CHECK-LABEL: define {{[^@]+}}@fmv._Mflagm2Msme-i16i64
 162 // CHECK-SAME: () #[[ATTR1:[0-9]+]] {
 163 // CHECK-NEXT:  entry:
 164 // CHECK-NEXT:    ret i32 2
 165 //
 166 //
 167 // CHECK: Function Attrs: noinline nounwind optnone
 168 // CHECK-LABEL: define {{[^@]+}}@fmv._MlseMsha2
 169 // CHECK-SAME: () #[[ATTR2:[0-9]+]] {
 170 // CHECK-NEXT:  entry:
 171 // CHECK-NEXT:    ret i32 3
 172 //
 173 //
 174 // CHECK: Function Attrs: noinline nounwind optnone
 175 // CHECK-LABEL: define {{[^@]+}}@fmv._MdotprodMls64
 176 // CHECK-SAME: () #[[ATTR3:[0-9]+]] {
 177 // CHECK-NEXT:  entry:
 178 // CHECK-NEXT:    ret i32 4
 179 //
 180 //
 181 // CHECK: Function Attrs: noinline nounwind optnone
 182 // CHECK-LABEL: define {{[^@]+}}@fmv._Mfp16fmlMmemtag
 183 // CHECK-SAME: () #[[ATTR4:[0-9]+]] {
 184 // CHECK-NEXT:  entry:
 185 // CHECK-NEXT:    ret i32 5
 186 //
 187 //
 188 // CHECK: Function Attrs: noinline nounwind optnone
 189 // CHECK-LABEL: define {{[^@]+}}@fmv._MaesMfp
 190 // CHECK-SAME: () #[[ATTR5:[0-9]+]] {
 191 // CHECK-NEXT:  entry:
 192 // CHECK-NEXT:    ret i32 6
 193 //
 194 //
 195 // CHECK: Function Attrs: noinline nounwind optnone
 196 // CHECK-LABEL: define {{[^@]+}}@fmv._McrcMls64
 197 // CHECK-SAME: () #[[ATTR6:[0-9]+]] {
 198 // CHECK-NEXT:  entry:
 199 // CHECK-NEXT:    ret i32 7
 200 //
 201 //
 202 // CHECK: Function Attrs: noinline nounwind optnone
 203 // CHECK-LABEL: define {{[^@]+}}@fmv._Mbti
 204 // CHECK-SAME: () #[[ATTR7:[0-9]+]] {
 205 // CHECK-NEXT:  entry:
 206 // CHECK-NEXT:    ret i32 8
 207 //
 208 //
 209 // CHECK: Function Attrs: noinline nounwind optnone
 210 // CHECK-LABEL: define {{[^@]+}}@fmv._Msme2
 211 // CHECK-SAME: () #[[ATTR8:[0-9]+]] {
 212 // CHECK-NEXT:  entry:
 213 // CHECK-NEXT:    ret i32 9
 214 //
 215 //
 216 // CHECK: Function Attrs: noinline nounwind optnone
 217 // CHECK-LABEL: define {{[^@]+}}@fmv.default
 218 // CHECK-SAME: () #[[ATTR9:[0-9]+]] {
 219 // CHECK-NEXT:  entry:
 220 // CHECK-NEXT:    ret i32 0
 221 //
 222 //
 223 // CHECK: Function Attrs: noinline nounwind optnone
 224 // CHECK-LABEL: define {{[^@]+}}@fmv_one._Mls64Msimd
 225 // CHECK-SAME: () #[[ATTR10:[0-9]+]] {
 226 // CHECK-NEXT:  entry:
 227 // CHECK-NEXT:    ret i32 1
 228 //
 229 //
 230 // CHECK: Function Attrs: noinline nounwind optnone
 231 // CHECK-LABEL: define {{[^@]+}}@fmv_one._Mdpb
 232 // CHECK-SAME: () #[[ATTR11:[0-9]+]] {
 233 // CHECK-NEXT:  entry:
 234 // CHECK-NEXT:    ret i32 2
 235 //
 236 //
 237 // CHECK: Function Attrs: noinline nounwind optnone
 238 // CHECK-LABEL: define {{[^@]+}}@fmv_one.default
 239 // CHECK-SAME: () #[[ATTR9]] {
 240 // CHECK-NEXT:  entry:
 241 // CHECK-NEXT:    ret i32 0
 242 //
 243 //
 244 // CHECK: Function Attrs: noinline nounwind optnone
 245 // CHECK-LABEL: define {{[^@]+}}@fmv_two._Mfp
 246 // CHECK-SAME: () #[[ATTR12:[0-9]+]] {
 247 // CHECK-NEXT:  entry:
 248 // CHECK-NEXT:    ret i32 1
 249 //
 250 //
 251 // CHECK: Function Attrs: noinline nounwind optnone
 252 // CHECK-LABEL: define {{[^@]+}}@fmv_two._Msimd
 253 // CHECK-SAME: () #[[ATTR13:[0-9]+]] {
 254 // CHECK-NEXT:  entry:
 255 // CHECK-NEXT:    ret i32 2
 256 //
 257 //
 258 // CHECK: Function Attrs: noinline nounwind optnone
 259 // CHECK-LABEL: define {{[^@]+}}@fmv_two._Mfp16Msimd
 260 // CHECK-SAME: () #[[ATTR14:[0-9]+]] {
 261 // CHECK-NEXT:  entry:
 262 // CHECK-NEXT:    ret i32 4
 263 //
 264 //
 265 // CHECK: Function Attrs: noinline nounwind optnone
 266 // CHECK-LABEL: define {{[^@]+}}@fmv_two.default
 267 // CHECK-SAME: () #[[ATTR9]] {
 268 // CHECK-NEXT:  entry:
 269 // CHECK-NEXT:    ret i32 0
 270 //
 271 //
 272 // CHECK: Function Attrs: noinline nounwind optnone
 273 // CHECK-LABEL: define {{[^@]+}}@foo
 274 // CHECK-SAME: () #[[ATTR15:[0-9]+]] {
 275 // CHECK-NEXT:  entry:
 276 // CHECK-NEXT:    [[CALL:%.*]] = call i32 @fmv()
 277 // CHECK-NEXT:    [[CALL1:%.*]] = call i32 @fmv_one()
 278 // CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
 279 // CHECK-NEXT:    [[CALL2:%.*]] = call i32 @fmv_two()
 280 // CHECK-NEXT:    [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]]
 281 // CHECK-NEXT:    ret i32 [[ADD3]]
 282 //
 283 //
 284 // CHECK: Function Attrs: noinline nounwind optnone
 285 // CHECK-LABEL: define {{[^@]+}}@fmv_e.default
 286 // CHECK-SAME: () #[[ATTR9]] {
 287 // CHECK-NEXT:  entry:
 288 // CHECK-NEXT:    ret i32 20
 289 //
 290 //
 291 // CHECK: Function Attrs: noinline nounwind optnone
 292 // CHECK-LABEL: define {{[^@]+}}@fmv_default.default
 293 // CHECK-SAME: () #[[ATTR9]] {
 294 // CHECK-NEXT:  entry:
 295 // CHECK-NEXT:    ret i32 111
 296 //
 297 //
 298 // CHECK: Function Attrs: noinline nounwind optnone
 299 // CHECK-LABEL: define {{[^@]+}}@fmv_c._Mssbs
 300 // CHECK-SAME: () #[[ATTR17:[0-9]+]] {
 301 // CHECK-NEXT:  entry:
 302 // CHECK-NEXT:    ret void
 303 //
 304 //
 305 // CHECK: Function Attrs: noinline nounwind optnone
 306 // CHECK-LABEL: define {{[^@]+}}@fmv_c.default
 307 // CHECK-SAME: () #[[ATTR9]] {
 308 // CHECK-NEXT:  entry:
 309 // CHECK-NEXT:    ret void
 310 //
 311 //
 312 // CHECK: Function Attrs: noinline nounwind optnone
 313 // CHECK-LABEL: define {{[^@]+}}@goo
 314 // CHECK-SAME: () #[[ATTR15]] {
 315 // CHECK-NEXT:  entry:
 316 // CHECK-NEXT:    [[CALL:%.*]] = call i32 @fmv_inline()
 317 // CHECK-NEXT:    [[CALL1:%.*]] = call i32 @fmv_e()
 318 // CHECK-NEXT:    [[CALL2:%.*]] = call i32 @fmv_d()
 319 // CHECK-NEXT:    call void @fmv_c()
 320 // CHECK-NEXT:    [[CALL3:%.*]] = call i32 @fmv_default()
 321 // CHECK-NEXT:    ret i32 [[CALL3]]
 322 //
 323 //
 324 // CHECK: Function Attrs: noinline nounwind optnone
 325 // CHECK-LABEL: define {{[^@]+}}@recur
 326 // CHECK-SAME: () #[[ATTR15]] {
 327 // CHECK-NEXT:  entry:
 328 // CHECK-NEXT:    call void @reca()
 329 // CHECK-NEXT:    ret void
 330 //
 331 //
 332 // CHECK: Function Attrs: noinline nounwind optnone
 333 // CHECK-LABEL: define {{[^@]+}}@hoo
 334 // CHECK-SAME: () #[[ATTR15]] {
 335 // CHECK-NEXT:  entry:
 336 // CHECK-NEXT:    [[FP1:%.*]] = alloca ptr, align 8
 337 // CHECK-NEXT:    [[FP2:%.*]] = alloca ptr, align 8
 338 // CHECK-NEXT:    call void @f(ptr noundef @fmv)
 339 // CHECK-NEXT:    store ptr @fmv, ptr [[FP1]], align 8
 340 // CHECK-NEXT:    store ptr @fmv, ptr [[FP2]], align 8
 341 // CHECK-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[FP1]], align 8
 342 // CHECK-NEXT:    [[CALL:%.*]] = call i32 [[TMP0]]()
 343 // CHECK-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[FP2]], align 8
 344 // CHECK-NEXT:    [[CALL1:%.*]] = call i32 [[TMP1]]()
 345 // CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
 346 // CHECK-NEXT:    ret i32 [[ADD]]
 347 //
 348 //
 349 // CHECK: Function Attrs: noinline nounwind optnone
 350 // CHECK-LABEL: define {{[^@]+}}@unused_with_forward_default_decl._Mmops
 351 // CHECK-SAME: () #[[ATTR19:[0-9]+]] {
 352 // CHECK-NEXT:  entry:
 353 // CHECK-NEXT:    ret i32 0
 354 //
 355 //
 356 // CHECK: Function Attrs: noinline nounwind optnone
 357 // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_extern_forward_default_decl._Mdotprod
 358 // CHECK-SAME: () #[[ATTR20:[0-9]+]] {
 359 // CHECK-NEXT:  entry:
 360 // CHECK-NEXT:    ret i32 0
 361 //
 362 //
 363 // CHECK: Function Attrs: noinline nounwind optnone
 364 // CHECK-LABEL: define {{[^@]+}}@unused_with_default_decl._Maes
 365 // CHECK-SAME: () #[[ATTR5]] {
 366 // CHECK-NEXT:  entry:
 367 // CHECK-NEXT:    ret i32 0
 368 //
 369 //
 370 // CHECK: Function Attrs: noinline nounwind optnone
 371 // CHECK-LABEL: define {{[^@]+}}@unused_with_default_def._Msve
 372 // CHECK-SAME: () #[[ATTR21:[0-9]+]] {
 373 // CHECK-NEXT:  entry:
 374 // CHECK-NEXT:    ret i32 0
 375 //
 376 //
 377 // CHECK: Function Attrs: noinline nounwind optnone
 378 // CHECK-LABEL: define {{[^@]+}}@unused_with_default_def.default
 379 // CHECK-SAME: () #[[ATTR9]] {
 380 // CHECK-NEXT:  entry:
 381 // CHECK-NEXT:    ret i32 1
 382 //
 383 //
 384 // CHECK: Function Attrs: noinline nounwind optnone
 385 // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_default_def._Mfp16
 386 // CHECK-SAME: () #[[ATTR22:[0-9]+]] {
 387 // CHECK-NEXT:  entry:
 388 // CHECK-NEXT:    ret i32 0
 389 //
 390 //
 391 // CHECK: Function Attrs: noinline nounwind optnone
 392 // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_default_def.default
 393 // CHECK-SAME: () #[[ATTR9]] {
 394 // CHECK-NEXT:  entry:
 395 // CHECK-NEXT:    ret i32 1
 396 //
 397 //
 398 // CHECK: Function Attrs: noinline nounwind optnone
 399 // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_forward_default_def.default
 400 // CHECK-SAME: () #[[ATTR15]] {
 401 // CHECK-NEXT:  entry:
 402 // CHECK-NEXT:    ret i32 0
 403 //
 404 //
 405 // CHECK: Function Attrs: noinline nounwind optnone
 406 // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_forward_default_def._Mlse
 407 // CHECK-SAME: () #[[ATTR23:[0-9]+]] {
 408 // CHECK-NEXT:  entry:
 409 // CHECK-NEXT:    ret i32 1
 410 //
 411 //
 412 // CHECK: Function Attrs: noinline nounwind optnone
 413 // CHECK-LABEL: define {{[^@]+}}@unused_without_default._Mrdm
 414 // CHECK-SAME: () #[[ATTR24:[0-9]+]] {
 415 // CHECK-NEXT:  entry:
 416 // CHECK-NEXT:    ret i32 0
 417 //
 418 //
 419 // CHECK: Function Attrs: noinline nounwind optnone
 420 // CHECK-LABEL: define {{[^@]+}}@default_def_with_version_decls.default
 421 // CHECK-SAME: () #[[ATTR15]] {
 422 // CHECK-NEXT:  entry:
 423 // CHECK-NEXT:    ret i32 0
 424 //
 425 //
 426 // CHECK: Function Attrs: noinline nounwind optnone
 427 // CHECK-LABEL: define {{[^@]+}}@used_def_without_default_decl._Mjscvt
 428 // CHECK-SAME: () #[[ATTR26:[0-9]+]] {
 429 // CHECK-NEXT:  entry:
 430 // CHECK-NEXT:    ret i32 1
 431 //
 432 //
 433 // CHECK: Function Attrs: noinline nounwind optnone
 434 // CHECK-LABEL: define {{[^@]+}}@used_def_without_default_decl._Mrdm
 435 // CHECK-SAME: () #[[ATTR24]] {
 436 // CHECK-NEXT:  entry:
 437 // CHECK-NEXT:    ret i32 2
 438 //
 439 //
 440 // CHECK: Function Attrs: noinline nounwind optnone
 441 // CHECK-LABEL: define {{[^@]+}}@caller
 442 // CHECK-SAME: () #[[ATTR15]] {
 443 // CHECK-NEXT:  entry:
 444 // CHECK-NEXT:    [[CALL:%.*]] = call i32 @used_def_without_default_decl()
 445 // CHECK-NEXT:    [[CALL1:%.*]] = call i32 @used_decl_without_default_decl()
 446 // CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
 447 // CHECK-NEXT:    ret i32 [[ADD]]
 448 //
 449 //
 450 // CHECK: Function Attrs: noinline nounwind optnone
 451 // CHECK-LABEL: define {{[^@]+}}@main
 452 // CHECK-SAME: () #[[ATTR9]] {
 453 // CHECK-NEXT:  entry:
 454 // CHECK-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 455 // CHECK-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 456 // CHECK-NEXT:    call void @recur()
 457 // CHECK-NEXT:    [[CALL:%.*]] = call i32 @goo()
 458 // CHECK-NEXT:    ret i32 [[CALL]]
 459 //
 460 //
 461 // CHECK-LABEL: define {{[^@]+}}@fmv.resolver() comdat {
 462 // CHECK-NEXT:  resolver_entry:
 463 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 464 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 465 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 66315
 466 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 66315
 467 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 468 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 469 // CHECK:       resolver_return:
 470 // CHECK-NEXT:    ret ptr @fmv._MflagmMfp16fmlMrng
 471 // CHECK:       resolver_else:
 472 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 473 // CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 72061992218723078
 474 // CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 72061992218723078
 475 // CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 476 // CHECK-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 477 // CHECK:       resolver_return1:
 478 // CHECK-NEXT:    ret ptr @fmv._Mflagm2Msme-i16i64
 479 // CHECK:       resolver_else2:
 480 // CHECK-NEXT:    [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 481 // CHECK-NEXT:    [[TMP9:%.*]] = and i64 [[TMP8]], 9007199254741776
 482 // CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 9007199254741776
 483 // CHECK-NEXT:    [[TMP11:%.*]] = and i1 true, [[TMP10]]
 484 // CHECK-NEXT:    br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
 485 // CHECK:       resolver_return3:
 486 // CHECK-NEXT:    ret ptr @fmv._MdotprodMls64
 487 // CHECK:       resolver_else4:
 488 // CHECK-NEXT:    [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 489 // CHECK-NEXT:    [[TMP13:%.*]] = and i64 [[TMP12]], 9007199254742016
 490 // CHECK-NEXT:    [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 9007199254742016
 491 // CHECK-NEXT:    [[TMP15:%.*]] = and i1 true, [[TMP14]]
 492 // CHECK-NEXT:    br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]]
 493 // CHECK:       resolver_return5:
 494 // CHECK-NEXT:    ret ptr @fmv._McrcMls64
 495 // CHECK:       resolver_else6:
 496 // CHECK-NEXT:    [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 497 // CHECK-NEXT:    [[TMP17:%.*]] = and i64 [[TMP16]], 17592186110728
 498 // CHECK-NEXT:    [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 17592186110728
 499 // CHECK-NEXT:    [[TMP19:%.*]] = and i1 true, [[TMP18]]
 500 // CHECK-NEXT:    br i1 [[TMP19]], label [[RESOLVER_RETURN7:%.*]], label [[RESOLVER_ELSE8:%.*]]
 501 // CHECK:       resolver_return7:
 502 // CHECK-NEXT:    ret ptr @fmv._Mfp16fmlMmemtag
 503 // CHECK:       resolver_else8:
 504 // CHECK-NEXT:    [[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 505 // CHECK-NEXT:    [[TMP21:%.*]] = and i64 [[TMP20]], 33536
 506 // CHECK-NEXT:    [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 33536
 507 // CHECK-NEXT:    [[TMP23:%.*]] = and i1 true, [[TMP22]]
 508 // CHECK-NEXT:    br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]]
 509 // CHECK:       resolver_return9:
 510 // CHECK-NEXT:    ret ptr @fmv._MaesMfp
 511 // CHECK:       resolver_else10:
 512 // CHECK-NEXT:    [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 513 // CHECK-NEXT:    [[TMP25:%.*]] = and i64 [[TMP24]], 4992
 514 // CHECK-NEXT:    [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 4992
 515 // CHECK-NEXT:    [[TMP27:%.*]] = and i1 true, [[TMP26]]
 516 // CHECK-NEXT:    br i1 [[TMP27]], label [[RESOLVER_RETURN11:%.*]], label [[RESOLVER_ELSE12:%.*]]
 517 // CHECK:       resolver_return11:
 518 // CHECK-NEXT:    ret ptr @fmv._MlseMsha2
 519 // CHECK:       resolver_else12:
 520 // CHECK-NEXT:    [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 521 // CHECK-NEXT:    [[TMP29:%.*]] = and i64 [[TMP28]], 144119586256651008
 522 // CHECK-NEXT:    [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 144119586256651008
 523 // CHECK-NEXT:    [[TMP31:%.*]] = and i1 true, [[TMP30]]
 524 // CHECK-NEXT:    br i1 [[TMP31]], label [[RESOLVER_RETURN13:%.*]], label [[RESOLVER_ELSE14:%.*]]
 525 // CHECK:       resolver_return13:
 526 // CHECK-NEXT:    ret ptr @fmv._Msme2
 527 // CHECK:       resolver_else14:
 528 // CHECK-NEXT:    [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 529 // CHECK-NEXT:    [[TMP33:%.*]] = and i64 [[TMP32]], 1125899906842624
 530 // CHECK-NEXT:    [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 1125899906842624
 531 // CHECK-NEXT:    [[TMP35:%.*]] = and i1 true, [[TMP34]]
 532 // CHECK-NEXT:    br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]]
 533 // CHECK:       resolver_return15:
 534 // CHECK-NEXT:    ret ptr @fmv._Mbti
 535 // CHECK:       resolver_else16:
 536 // CHECK-NEXT:    ret ptr @fmv.default
 537 //
 538 //
 539 // CHECK-LABEL: define {{[^@]+}}@fmv_one.resolver() comdat {
 540 // CHECK-NEXT:  resolver_entry:
 541 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 542 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 543 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 9007199254741760
 544 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 9007199254741760
 545 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 546 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 547 // CHECK:       resolver_return:
 548 // CHECK-NEXT:    ret ptr @fmv_one._Mls64Msimd
 549 // CHECK:       resolver_else:
 550 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 551 // CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 262144
 552 // CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 262144
 553 // CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 554 // CHECK-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 555 // CHECK:       resolver_return1:
 556 // CHECK-NEXT:    ret ptr @fmv_one._Mdpb
 557 // CHECK:       resolver_else2:
 558 // CHECK-NEXT:    ret ptr @fmv_one.default
 559 //
 560 //
 561 // CHECK-LABEL: define {{[^@]+}}@fmv_two.resolver() comdat {
 562 // CHECK-NEXT:  resolver_entry:
 563 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 564 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 565 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 66304
 566 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 66304
 567 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 568 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 569 // CHECK:       resolver_return:
 570 // CHECK-NEXT:    ret ptr @fmv_two._Mfp16Msimd
 571 // CHECK:       resolver_else:
 572 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 573 // CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 768
 574 // CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 768
 575 // CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 576 // CHECK-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 577 // CHECK:       resolver_return1:
 578 // CHECK-NEXT:    ret ptr @fmv_two._Msimd
 579 // CHECK:       resolver_else2:
 580 // CHECK-NEXT:    [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 581 // CHECK-NEXT:    [[TMP9:%.*]] = and i64 [[TMP8]], 256
 582 // CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 256
 583 // CHECK-NEXT:    [[TMP11:%.*]] = and i1 true, [[TMP10]]
 584 // CHECK-NEXT:    br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
 585 // CHECK:       resolver_return3:
 586 // CHECK-NEXT:    ret ptr @fmv_two._Mfp
 587 // CHECK:       resolver_else4:
 588 // CHECK-NEXT:    ret ptr @fmv_two.default
 589 //
 590 //
 591 // CHECK-LABEL: define {{[^@]+}}@fmv_e.resolver() comdat {
 592 // CHECK-NEXT:  resolver_entry:
 593 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 594 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 595 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 9007199254740992
 596 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 9007199254740992
 597 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 598 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 599 // CHECK:       resolver_return:
 600 // CHECK-NEXT:    ret ptr @fmv_e._Mls64
 601 // CHECK:       resolver_else:
 602 // CHECK-NEXT:    ret ptr @fmv_e.default
 603 //
 604 //
 605 // CHECK: Function Attrs: noinline nounwind optnone
 606 // CHECK-LABEL: define {{[^@]+}}@fmv_d._Msb
 607 // CHECK-SAME: () #[[ATTR28:[0-9]+]] {
 608 // CHECK-NEXT:  entry:
 609 // CHECK-NEXT:    ret i32 0
 610 //
 611 //
 612 // CHECK: Function Attrs: noinline nounwind optnone
 613 // CHECK-LABEL: define {{[^@]+}}@fmv_d.default
 614 // CHECK-SAME: () #[[ATTR9]] {
 615 // CHECK-NEXT:  entry:
 616 // CHECK-NEXT:    ret i32 1
 617 //
 618 //
 619 // CHECK-LABEL: define {{[^@]+}}@fmv_d.resolver() {
 620 // CHECK-NEXT:  resolver_entry:
 621 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 622 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 623 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 70368744177664
 624 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 70368744177664
 625 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 626 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 627 // CHECK:       resolver_return:
 628 // CHECK-NEXT:    ret ptr @fmv_d._Msb
 629 // CHECK:       resolver_else:
 630 // CHECK-NEXT:    ret ptr @fmv_d.default
 631 //
 632 //
 633 // CHECK-LABEL: define {{[^@]+}}@fmv_c.resolver() comdat {
 634 // CHECK-NEXT:  resolver_entry:
 635 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 636 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 637 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 562949953421312
 638 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 562949953421312
 639 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 640 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 641 // CHECK:       resolver_return:
 642 // CHECK-NEXT:    ret ptr @fmv_c._Mssbs
 643 // CHECK:       resolver_else:
 644 // CHECK-NEXT:    ret ptr @fmv_c.default
 645 //
 646 //
 647 // CHECK: Function Attrs: noinline nounwind optnone
 648 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MaesMf64mmMsha2
 649 // CHECK-SAME: () #[[ATTR29:[0-9]+]] {
 650 // CHECK-NEXT:  entry:
 651 // CHECK-NEXT:    ret i32 1
 652 //
 653 //
 654 // CHECK: Function Attrs: noinline nounwind optnone
 655 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfcmaMfp16MrdmMsme
 656 // CHECK-SAME: () #[[ATTR30:[0-9]+]] {
 657 // CHECK-NEXT:  entry:
 658 // CHECK-NEXT:    ret i32 2
 659 //
 660 //
 661 // CHECK: Function Attrs: noinline nounwind optnone
 662 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mf32mmMi8mmMsha3
 663 // CHECK-SAME: () #[[ATTR31:[0-9]+]] {
 664 // CHECK-NEXT:  entry:
 665 // CHECK-NEXT:    ret i32 12
 666 //
 667 //
 668 // CHECK: Function Attrs: noinline nounwind optnone
 669 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mbf16Mdit
 670 // CHECK-SAME: () #[[ATTR32:[0-9]+]] {
 671 // CHECK-NEXT:  entry:
 672 // CHECK-NEXT:    ret i32 8
 673 //
 674 //
 675 // CHECK: Function Attrs: noinline nounwind optnone
 676 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MdpbMrcpc2
 677 // CHECK-SAME: () #[[ATTR33:[0-9]+]] {
 678 // CHECK-NEXT:  entry:
 679 // CHECK-NEXT:    ret i32 6
 680 //
 681 //
 682 // CHECK: Function Attrs: noinline nounwind optnone
 683 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mdpb2Mjscvt
 684 // CHECK-SAME: () #[[ATTR34:[0-9]+]] {
 685 // CHECK-NEXT:  entry:
 686 // CHECK-NEXT:    ret i32 7
 687 //
 688 //
 689 // CHECK: Function Attrs: noinline nounwind optnone
 690 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfrinttsMrcpc
 691 // CHECK-SAME: () #[[ATTR35:[0-9]+]] {
 692 // CHECK-NEXT:  entry:
 693 // CHECK-NEXT:    ret i32 3
 694 //
 695 //
 696 // CHECK: Function Attrs: noinline nounwind optnone
 697 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mbf16Msve
 698 // CHECK-SAME: () #[[ATTR36:[0-9]+]] {
 699 // CHECK-NEXT:  entry:
 700 // CHECK-NEXT:    ret i32 4
 701 //
 702 //
 703 // CHECK: Function Attrs: noinline nounwind optnone
 704 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msve2-aesMsve2-sha3
 705 // CHECK-SAME: () #[[ATTR37:[0-9]+]] {
 706 // CHECK-NEXT:  entry:
 707 // CHECK-NEXT:    ret i32 5
 708 //
 709 //
 710 // CHECK: Function Attrs: noinline nounwind optnone
 711 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msve2Msve2-aesMsve2-bitperm
 712 // CHECK-SAME: () #[[ATTR38:[0-9]+]] {
 713 // CHECK-NEXT:  entry:
 714 // CHECK-NEXT:    ret i32 9
 715 //
 716 //
 717 // CHECK: Function Attrs: noinline nounwind optnone
 718 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MmemtagMsve2-sm4
 719 // CHECK-SAME: () #[[ATTR39:[0-9]+]] {
 720 // CHECK-NEXT:  entry:
 721 // CHECK-NEXT:    ret i32 10
 722 //
 723 //
 724 // CHECK: Function Attrs: noinline nounwind optnone
 725 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MmemtagMmopsMrcpc3
 726 // CHECK-SAME: () #[[ATTR40:[0-9]+]] {
 727 // CHECK-NEXT:  entry:
 728 // CHECK-NEXT:    ret i32 11
 729 //
 730 //
 731 // CHECK: Function Attrs: noinline nounwind optnone
 732 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MaesMdotprod
 733 // CHECK-SAME: () #[[ATTR41:[0-9]+]] {
 734 // CHECK-NEXT:  entry:
 735 // CHECK-NEXT:    ret i32 13
 736 //
 737 //
 738 // CHECK: Function Attrs: noinline nounwind optnone
 739 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mfp16fmlMsimd
 740 // CHECK-SAME: () #[[ATTR42:[0-9]+]] {
 741 // CHECK-NEXT:  entry:
 742 // CHECK-NEXT:    ret i32 14
 743 //
 744 //
 745 // CHECK: Function Attrs: noinline nounwind optnone
 746 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfpMsm4
 747 // CHECK-SAME: () #[[ATTR43:[0-9]+]] {
 748 // CHECK-NEXT:  entry:
 749 // CHECK-NEXT:    ret i32 15
 750 //
 751 //
 752 // CHECK: Function Attrs: noinline nounwind optnone
 753 // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MlseMrdm
 754 // CHECK-SAME: () #[[ATTR44:[0-9]+]] {
 755 // CHECK-NEXT:  entry:
 756 // CHECK-NEXT:    ret i32 16
 757 //
 758 //
 759 // CHECK: Function Attrs: noinline nounwind optnone
 760 // CHECK-LABEL: define {{[^@]+}}@fmv_inline.default
 761 // CHECK-SAME: () #[[ATTR9]] {
 762 // CHECK-NEXT:  entry:
 763 // CHECK-NEXT:    ret i32 3
 764 //
 765 //
 766 // CHECK-LABEL: define {{[^@]+}}@fmv_inline.resolver() comdat {
 767 // CHECK-NEXT:  resolver_entry:
 768 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 769 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 770 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 4398182892352
 771 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4398182892352
 772 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 773 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 774 // CHECK:       resolver_return:
 775 // CHECK-NEXT:    ret ptr @fmv_inline._MfcmaMfp16MrdmMsme
 776 // CHECK:       resolver_else:
 777 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 778 // CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 864708720653762560
 779 // CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 864708720653762560
 780 // CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 781 // CHECK-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 782 // CHECK:       resolver_return1:
 783 // CHECK-NEXT:    ret ptr @fmv_inline._MmemtagMmopsMrcpc3
 784 // CHECK:       resolver_else2:
 785 // CHECK-NEXT:    [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 786 // CHECK-NEXT:    [[TMP9:%.*]] = and i64 [[TMP8]], 894427038464
 787 // CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 894427038464
 788 // CHECK-NEXT:    [[TMP11:%.*]] = and i1 true, [[TMP10]]
 789 // CHECK-NEXT:    br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
 790 // CHECK:       resolver_return3:
 791 // CHECK-NEXT:    ret ptr @fmv_inline._Msve2Msve2-aesMsve2-bitperm
 792 // CHECK:       resolver_else4:
 793 // CHECK-NEXT:    [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 794 // CHECK-NEXT:    [[TMP13:%.*]] = and i64 [[TMP12]], 35433583360
 795 // CHECK-NEXT:    [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 35433583360
 796 // CHECK-NEXT:    [[TMP15:%.*]] = and i1 true, [[TMP14]]
 797 // CHECK-NEXT:    br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]]
 798 // CHECK:       resolver_return5:
 799 // CHECK-NEXT:    ret ptr @fmv_inline._MaesMf64mmMsha2
 800 // CHECK:       resolver_else6:
 801 // CHECK-NEXT:    [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 802 // CHECK-NEXT:    [[TMP17:%.*]] = and i64 [[TMP16]], 18320798464
 803 // CHECK-NEXT:    [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 18320798464
 804 // CHECK-NEXT:    [[TMP19:%.*]] = and i1 true, [[TMP18]]
 805 // CHECK-NEXT:    br i1 [[TMP19]], label [[RESOLVER_RETURN7:%.*]], label [[RESOLVER_ELSE8:%.*]]
 806 // CHECK:       resolver_return7:
 807 // CHECK-NEXT:    ret ptr @fmv_inline._Mf32mmMi8mmMsha3
 808 // CHECK:       resolver_else8:
 809 // CHECK-NEXT:    [[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 810 // CHECK-NEXT:    [[TMP21:%.*]] = and i64 [[TMP20]], 19861002584864
 811 // CHECK-NEXT:    [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 19861002584864
 812 // CHECK-NEXT:    [[TMP23:%.*]] = and i1 true, [[TMP22]]
 813 // CHECK-NEXT:    br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]]
 814 // CHECK:       resolver_return9:
 815 // CHECK-NEXT:    ret ptr @fmv_inline._MmemtagMsve2-sm4
 816 // CHECK:       resolver_else10:
 817 // CHECK-NEXT:    [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 818 // CHECK-NEXT:    [[TMP25:%.*]] = and i64 [[TMP24]], 1444182864640
 819 // CHECK-NEXT:    [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 1444182864640
 820 // CHECK-NEXT:    [[TMP27:%.*]] = and i1 true, [[TMP26]]
 821 // CHECK-NEXT:    br i1 [[TMP27]], label [[RESOLVER_RETURN11:%.*]], label [[RESOLVER_ELSE12:%.*]]
 822 // CHECK:       resolver_return11:
 823 // CHECK-NEXT:    ret ptr @fmv_inline._Msve2-aesMsve2-sha3
 824 // CHECK:       resolver_else12:
 825 // CHECK-NEXT:    [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 826 // CHECK-NEXT:    [[TMP29:%.*]] = and i64 [[TMP28]], 1208025856
 827 // CHECK-NEXT:    [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 1208025856
 828 // CHECK-NEXT:    [[TMP31:%.*]] = and i1 true, [[TMP30]]
 829 // CHECK-NEXT:    br i1 [[TMP31]], label [[RESOLVER_RETURN13:%.*]], label [[RESOLVER_ELSE14:%.*]]
 830 // CHECK:       resolver_return13:
 831 // CHECK-NEXT:    ret ptr @fmv_inline._Mbf16Msve
 832 // CHECK:       resolver_else14:
 833 // CHECK-NEXT:    [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 834 // CHECK-NEXT:    [[TMP33:%.*]] = and i64 [[TMP32]], 134349568
 835 // CHECK-NEXT:    [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 134349568
 836 // CHECK-NEXT:    [[TMP35:%.*]] = and i1 true, [[TMP34]]
 837 // CHECK-NEXT:    br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]]
 838 // CHECK:       resolver_return15:
 839 // CHECK-NEXT:    ret ptr @fmv_inline._Mbf16Mdit
 840 // CHECK:       resolver_else16:
 841 // CHECK-NEXT:    [[TMP36:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 842 // CHECK-NEXT:    [[TMP37:%.*]] = and i64 [[TMP36]], 20971776
 843 // CHECK-NEXT:    [[TMP38:%.*]] = icmp eq i64 [[TMP37]], 20971776
 844 // CHECK-NEXT:    [[TMP39:%.*]] = and i1 true, [[TMP38]]
 845 // CHECK-NEXT:    br i1 [[TMP39]], label [[RESOLVER_RETURN17:%.*]], label [[RESOLVER_ELSE18:%.*]]
 846 // CHECK:       resolver_return17:
 847 // CHECK-NEXT:    ret ptr @fmv_inline._MfrinttsMrcpc
 848 // CHECK:       resolver_else18:
 849 // CHECK-NEXT:    [[TMP40:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 850 // CHECK-NEXT:    [[TMP41:%.*]] = and i64 [[TMP40]], 12845056
 851 // CHECK-NEXT:    [[TMP42:%.*]] = icmp eq i64 [[TMP41]], 12845056
 852 // CHECK-NEXT:    [[TMP43:%.*]] = and i1 true, [[TMP42]]
 853 // CHECK-NEXT:    br i1 [[TMP43]], label [[RESOLVER_RETURN19:%.*]], label [[RESOLVER_ELSE20:%.*]]
 854 // CHECK:       resolver_return19:
 855 // CHECK-NEXT:    ret ptr @fmv_inline._MdpbMrcpc2
 856 // CHECK:       resolver_else20:
 857 // CHECK-NEXT:    [[TMP44:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 858 // CHECK-NEXT:    [[TMP45:%.*]] = and i64 [[TMP44]], 1835264
 859 // CHECK-NEXT:    [[TMP46:%.*]] = icmp eq i64 [[TMP45]], 1835264
 860 // CHECK-NEXT:    [[TMP47:%.*]] = and i1 true, [[TMP46]]
 861 // CHECK-NEXT:    br i1 [[TMP47]], label [[RESOLVER_RETURN21:%.*]], label [[RESOLVER_ELSE22:%.*]]
 862 // CHECK:       resolver_return21:
 863 // CHECK-NEXT:    ret ptr @fmv_inline._Mdpb2Mjscvt
 864 // CHECK:       resolver_else22:
 865 // CHECK-NEXT:    [[TMP48:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 866 // CHECK-NEXT:    [[TMP49:%.*]] = and i64 [[TMP48]], 66312
 867 // CHECK-NEXT:    [[TMP50:%.*]] = icmp eq i64 [[TMP49]], 66312
 868 // CHECK-NEXT:    [[TMP51:%.*]] = and i1 true, [[TMP50]]
 869 // CHECK-NEXT:    br i1 [[TMP51]], label [[RESOLVER_RETURN23:%.*]], label [[RESOLVER_ELSE24:%.*]]
 870 // CHECK:       resolver_return23:
 871 // CHECK-NEXT:    ret ptr @fmv_inline._Mfp16fmlMsimd
 872 // CHECK:       resolver_else24:
 873 // CHECK-NEXT:    [[TMP52:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 874 // CHECK-NEXT:    [[TMP53:%.*]] = and i64 [[TMP52]], 33552
 875 // CHECK-NEXT:    [[TMP54:%.*]] = icmp eq i64 [[TMP53]], 33552
 876 // CHECK-NEXT:    [[TMP55:%.*]] = and i1 true, [[TMP54]]
 877 // CHECK-NEXT:    br i1 [[TMP55]], label [[RESOLVER_RETURN25:%.*]], label [[RESOLVER_ELSE26:%.*]]
 878 // CHECK:       resolver_return25:
 879 // CHECK-NEXT:    ret ptr @fmv_inline._MaesMdotprod
 880 // CHECK:       resolver_else26:
 881 // CHECK-NEXT:    [[TMP56:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 882 // CHECK-NEXT:    [[TMP57:%.*]] = and i64 [[TMP56]], 960
 883 // CHECK-NEXT:    [[TMP58:%.*]] = icmp eq i64 [[TMP57]], 960
 884 // CHECK-NEXT:    [[TMP59:%.*]] = and i1 true, [[TMP58]]
 885 // CHECK-NEXT:    br i1 [[TMP59]], label [[RESOLVER_RETURN27:%.*]], label [[RESOLVER_ELSE28:%.*]]
 886 // CHECK:       resolver_return27:
 887 // CHECK-NEXT:    ret ptr @fmv_inline._MlseMrdm
 888 // CHECK:       resolver_else28:
 889 // CHECK-NEXT:    [[TMP60:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 890 // CHECK-NEXT:    [[TMP61:%.*]] = and i64 [[TMP60]], 800
 891 // CHECK-NEXT:    [[TMP62:%.*]] = icmp eq i64 [[TMP61]], 800
 892 // CHECK-NEXT:    [[TMP63:%.*]] = and i1 true, [[TMP62]]
 893 // CHECK-NEXT:    br i1 [[TMP63]], label [[RESOLVER_RETURN29:%.*]], label [[RESOLVER_ELSE30:%.*]]
 894 // CHECK:       resolver_return29:
 895 // CHECK-NEXT:    ret ptr @fmv_inline._MfpMsm4
 896 // CHECK:       resolver_else30:
 897 // CHECK-NEXT:    ret ptr @fmv_inline.default
 898 //
 899 //
 900 // CHECK: Function Attrs: noinline nounwind optnone
 901 // CHECK-LABEL: define {{[^@]+}}@reca.default
 902 // CHECK-SAME: () #[[ATTR9]] {
 903 // CHECK-NEXT:  entry:
 904 // CHECK-NEXT:    call void @recb()
 905 // CHECK-NEXT:    ret void
 906 //
 907 //
 908 // CHECK-LABEL: define {{[^@]+}}@reca.resolver() comdat {
 909 // CHECK-NEXT:  resolver_entry:
 910 // CHECK-NEXT:    ret ptr @reca.default
 911 //
 912 //
 913 // CHECK-LABEL: define {{[^@]+}}@unused_with_default_def.resolver() comdat {
 914 // CHECK-NEXT:  resolver_entry:
 915 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 916 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 917 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 1073807616
 918 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1073807616
 919 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 920 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 921 // CHECK:       resolver_return:
 922 // CHECK-NEXT:    ret ptr @unused_with_default_def._Msve
 923 // CHECK:       resolver_else:
 924 // CHECK-NEXT:    ret ptr @unused_with_default_def.default
 925 //
 926 //
 927 // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_default_def.resolver() comdat {
 928 // CHECK-NEXT:  resolver_entry:
 929 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 930 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 931 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 65792
 932 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 65792
 933 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 934 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 935 // CHECK:       resolver_return:
 936 // CHECK-NEXT:    ret ptr @unused_with_implicit_default_def._Mfp16
 937 // CHECK:       resolver_else:
 938 // CHECK-NEXT:    ret ptr @unused_with_implicit_default_def.default
 939 //
 940 //
 941 // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_forward_default_def.resolver() comdat {
 942 // CHECK-NEXT:  resolver_entry:
 943 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 944 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 945 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 128
 946 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 128
 947 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 948 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 949 // CHECK:       resolver_return:
 950 // CHECK-NEXT:    ret ptr @unused_with_implicit_forward_default_def._Mlse
 951 // CHECK:       resolver_else:
 952 // CHECK-NEXT:    ret ptr @unused_with_implicit_forward_default_def.default
 953 //
 954 //
 955 // CHECK-LABEL: define {{[^@]+}}@default_def_with_version_decls.resolver() comdat {
 956 // CHECK-NEXT:  resolver_entry:
 957 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 958 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 959 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 1048832
 960 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1048832
 961 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 962 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 963 // CHECK:       resolver_return:
 964 // CHECK-NEXT:    ret ptr @default_def_with_version_decls._Mjscvt
 965 // CHECK:       resolver_else:
 966 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
 967 // CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 832
 968 // CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 832
 969 // CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 970 // CHECK-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 971 // CHECK:       resolver_return1:
 972 // CHECK-NEXT:    ret ptr @default_def_with_version_decls._Mrdm
 973 // CHECK:       resolver_else2:
 974 // CHECK-NEXT:    ret ptr @default_def_with_version_decls.default
 975 //
 976 //
 977 // CHECK: Function Attrs: noinline nounwind optnone
 978 // CHECK-LABEL: define {{[^@]+}}@recb.default
 979 // CHECK-SAME: () #[[ATTR9]] {
 980 // CHECK-NEXT:  entry:
 981 // CHECK-NEXT:    call void @func()
 982 // CHECK-NEXT:    ret void
 983 //
 984 //
 985 // CHECK: Function Attrs: noinline nounwind optnone
 986 // CHECK-LABEL: define {{[^@]+}}@func
 987 // CHECK-SAME: () #[[ATTR15]] {
 988 // CHECK-NEXT:  entry:
 989 // CHECK-NEXT:    ret void
 990 //
 991 //
 992 // CHECK-LABEL: define {{[^@]+}}@recb.resolver() comdat {
 993 // CHECK-NEXT:  resolver_entry:
 994 // CHECK-NEXT:    ret ptr @recb.default
 995 //
 996 //
 997 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
 998 // CHECK-NOFMV-LABEL: define {{[^@]+}}@foo
 999 // CHECK-NOFMV-SAME: () #[[ATTR0:[0-9]+]] {
1000 // CHECK-NOFMV-NEXT:  entry:
1001 // CHECK-NOFMV-NEXT:    [[CALL:%.*]] = call i32 @fmv()
1002 // CHECK-NOFMV-NEXT:    [[CALL1:%.*]] = call i32 @fmv_one()
1003 // CHECK-NOFMV-NEXT:    [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
1004 // CHECK-NOFMV-NEXT:    [[CALL2:%.*]] = call i32 @fmv_two()
1005 // CHECK-NOFMV-NEXT:    [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]]
1006 // CHECK-NOFMV-NEXT:    ret i32 [[ADD3]]
1007 //
1008 //
1009 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1010 // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv
1011 // CHECK-NOFMV-SAME: () #[[ATTR1:[0-9]+]] {
1012 // CHECK-NOFMV-NEXT:  entry:
1013 // CHECK-NOFMV-NEXT:    ret i32 0
1014 //
1015 //
1016 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1017 // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_one
1018 // CHECK-NOFMV-SAME: () #[[ATTR1]] {
1019 // CHECK-NOFMV-NEXT:  entry:
1020 // CHECK-NOFMV-NEXT:    ret i32 0
1021 //
1022 //
1023 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1024 // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_two
1025 // CHECK-NOFMV-SAME: () #[[ATTR1]] {
1026 // CHECK-NOFMV-NEXT:  entry:
1027 // CHECK-NOFMV-NEXT:    ret i32 0
1028 //
1029 //
1030 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1031 // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_e
1032 // CHECK-NOFMV-SAME: () #[[ATTR0]] {
1033 // CHECK-NOFMV-NEXT:  entry:
1034 // CHECK-NOFMV-NEXT:    ret i32 20
1035 //
1036 //
1037 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1038 // CHECK-NOFMV-LABEL: define {{[^@]+}}@goo
1039 // CHECK-NOFMV-SAME: () #[[ATTR0]] {
1040 // CHECK-NOFMV-NEXT:  entry:
1041 // CHECK-NOFMV-NEXT:    [[CALL:%.*]] = call i32 @fmv_inline()
1042 // CHECK-NOFMV-NEXT:    [[CALL1:%.*]] = call i32 @fmv_e()
1043 // CHECK-NOFMV-NEXT:    [[CALL2:%.*]] = call i32 @fmv_d()
1044 // CHECK-NOFMV-NEXT:    call void @fmv_c()
1045 // CHECK-NOFMV-NEXT:    [[CALL3:%.*]] = call i32 @fmv_default()
1046 // CHECK-NOFMV-NEXT:    ret i32 [[CALL3]]
1047 //
1048 //
1049 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1050 // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_d
1051 // CHECK-NOFMV-SAME: () #[[ATTR1]] {
1052 // CHECK-NOFMV-NEXT:  entry:
1053 // CHECK-NOFMV-NEXT:    ret i32 1
1054 //
1055 //
1056 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1057 // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_c
1058 // CHECK-NOFMV-SAME: () #[[ATTR1]] {
1059 // CHECK-NOFMV-NEXT:  entry:
1060 // CHECK-NOFMV-NEXT:    ret void
1061 //
1062 //
1063 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1064 // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_default
1065 // CHECK-NOFMV-SAME: () #[[ATTR1]] {
1066 // CHECK-NOFMV-NEXT:  entry:
1067 // CHECK-NOFMV-NEXT:    ret i32 111
1068 //
1069 //
1070 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1071 // CHECK-NOFMV-LABEL: define {{[^@]+}}@recur
1072 // CHECK-NOFMV-SAME: () #[[ATTR0]] {
1073 // CHECK-NOFMV-NEXT:  entry:
1074 // CHECK-NOFMV-NEXT:    call void @reca()
1075 // CHECK-NOFMV-NEXT:    ret void
1076 //
1077 //
1078 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1079 // CHECK-NOFMV-LABEL: define {{[^@]+}}@hoo
1080 // CHECK-NOFMV-SAME: () #[[ATTR0]] {
1081 // CHECK-NOFMV-NEXT:  entry:
1082 // CHECK-NOFMV-NEXT:    [[FP1:%.*]] = alloca ptr, align 8
1083 // CHECK-NOFMV-NEXT:    [[FP2:%.*]] = alloca ptr, align 8
1084 // CHECK-NOFMV-NEXT:    call void @f(ptr noundef @fmv)
1085 // CHECK-NOFMV-NEXT:    store ptr @fmv, ptr [[FP1]], align 8
1086 // CHECK-NOFMV-NEXT:    store ptr @fmv, ptr [[FP2]], align 8
1087 // CHECK-NOFMV-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[FP1]], align 8
1088 // CHECK-NOFMV-NEXT:    [[CALL:%.*]] = call i32 [[TMP0]]()
1089 // CHECK-NOFMV-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[FP2]], align 8
1090 // CHECK-NOFMV-NEXT:    [[CALL1:%.*]] = call i32 [[TMP1]]()
1091 // CHECK-NOFMV-NEXT:    [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
1092 // CHECK-NOFMV-NEXT:    ret i32 [[ADD]]
1093 //
1094 //
1095 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1096 // CHECK-NOFMV-LABEL: define {{[^@]+}}@unused_with_implicit_default_def
1097 // CHECK-NOFMV-SAME: () #[[ATTR0]] {
1098 // CHECK-NOFMV-NEXT:  entry:
1099 // CHECK-NOFMV-NEXT:    ret i32 1
1100 //
1101 //
1102 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1103 // CHECK-NOFMV-LABEL: define {{[^@]+}}@unused_with_implicit_forward_default_def
1104 // CHECK-NOFMV-SAME: () #[[ATTR0]] {
1105 // CHECK-NOFMV-NEXT:  entry:
1106 // CHECK-NOFMV-NEXT:    ret i32 0
1107 //
1108 //
1109 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1110 // CHECK-NOFMV-LABEL: define {{[^@]+}}@default_def_with_version_decls
1111 // CHECK-NOFMV-SAME: () #[[ATTR0]] {
1112 // CHECK-NOFMV-NEXT:  entry:
1113 // CHECK-NOFMV-NEXT:    ret i32 0
1114 //
1115 //
1116 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1117 // CHECK-NOFMV-LABEL: define {{[^@]+}}@main
1118 // CHECK-NOFMV-SAME: () #[[ATTR1]] {
1119 // CHECK-NOFMV-NEXT:  entry:
1120 // CHECK-NOFMV-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1121 // CHECK-NOFMV-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1122 // CHECK-NOFMV-NEXT:    call void @recur()
1123 // CHECK-NOFMV-NEXT:    [[CALL:%.*]] = call i32 @goo()
1124 // CHECK-NOFMV-NEXT:    ret i32 [[CALL]]
1125 //
1126 //
1127 // CHECK-NOFMV: Function Attrs: noinline nounwind optnone
1128 // CHECK-NOFMV-LABEL: define {{[^@]+}}@unused_with_default_def
1129 // CHECK-NOFMV-SAME: () #[[ATTR1]] {
1130 // CHECK-NOFMV-NEXT:  entry:
1131 // CHECK-NOFMV-NEXT:    ret i32 1
1132 //
1133 //.
1134 // CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
1135 // CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
1136 //.
1137 // CHECK-NOFMV: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
1138 // CHECK-NOFMV: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
1139 //.