clang/test/CodeGenCXX/attr-target-clones-riscv.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals all --include-generated-funcs --version 4
   2 // RUN: %clang_cc1 -std=c++11 -triple riscv64-linux-gnu -target-feature +i -target-feature +m -emit-llvm %s -o - | FileCheck %s
   3
   4 __attribute__((target_clones("default", "arch=+m"))) int foo1(void) {
   5   return 1;
   6 }
   7 __attribute__((target_clones("default", "arch=+zbb", "arch=+m"))) int foo2(void) { return 2; }
   8 __attribute__((target_clones("default", "arch=+zbb,+c"))) int foo3(void) { return 3; }
   9 __attribute__((target_clones("default", "arch=+zbb,+v"))) int
  10 foo4(void) {
  11   return 4;
  12 }
  13 __attribute__((target_clones("default"))) int foo5(void) { return 5; }
  14 __attribute__((target_clones("default", "arch=+zvkt"))) int foo6(void) { return 2; }
  15
  16 __attribute__((target_clones("default", "arch=+zbb", "arch=+zba", "arch=+zbb,+zba"))) int foo7(void) { return 2; }
  17 __attribute__((target_clones("default", "arch=+zbb;priority=2", "arch=+zba;priority=1", "arch=+zbb,+zba;priority=3"))) int foo8(void) { return 2; }
  18 __attribute__((target_clones("default", "arch=+zbb;priority=1", "priority=2;arch=+zba", "priority=3;arch=+zbb,+zba"))) int foo9(void) { return 2; }
  19
  20 int bar() { return foo1() + foo2() + foo3() + foo4() + foo5()+ foo6() + foo7() + foo8() + foo9(); }
  21
  22 //.
  23 // CHECK: @__riscv_feature_bits = external dso_local global { i32, [2 x i64] }
  24 // CHECK: @_Z4foo1v.ifunc = weak_odr alias i32 (), ptr @_Z4foo1v
  25 // CHECK: @_Z4foo2v.ifunc = weak_odr alias i32 (), ptr @_Z4foo2v
  26 // CHECK: @_Z4foo3v.ifunc = weak_odr alias i32 (), ptr @_Z4foo3v
  27 // CHECK: @_Z4foo4v.ifunc = weak_odr alias i32 (), ptr @_Z4foo4v
  28 // CHECK: @_Z4foo5v.ifunc = weak_odr alias i32 (), ptr @_Z4foo5v
  29 // CHECK: @_Z4foo6v.ifunc = weak_odr alias i32 (), ptr @_Z4foo6v
  30 // CHECK: @_Z4foo7v.ifunc = weak_odr alias i32 (), ptr @_Z4foo7v
  31 // CHECK: @_Z4foo8v.ifunc = weak_odr alias i32 (), ptr @_Z4foo8v
  32 // CHECK: @_Z4foo9v.ifunc = weak_odr alias i32 (), ptr @_Z4foo9v
  33 // CHECK: @_Z4foo1v = weak_odr ifunc i32 (), ptr @_Z4foo1v.resolver
  34 // CHECK: @_Z4foo2v = weak_odr ifunc i32 (), ptr @_Z4foo2v.resolver
  35 // CHECK: @_Z4foo3v = weak_odr ifunc i32 (), ptr @_Z4foo3v.resolver
  36 // CHECK: @_Z4foo4v = weak_odr ifunc i32 (), ptr @_Z4foo4v.resolver
  37 // CHECK: @_Z4foo5v = weak_odr ifunc i32 (), ptr @_Z4foo5v.resolver
  38 // CHECK: @_Z4foo6v = weak_odr ifunc i32 (), ptr @_Z4foo6v.resolver
  39 // CHECK: @_Z4foo7v = weak_odr ifunc i32 (), ptr @_Z4foo7v.resolver
  40 // CHECK: @_Z4foo8v = weak_odr ifunc i32 (), ptr @_Z4foo8v.resolver
  41 // CHECK: @_Z4foo9v = weak_odr ifunc i32 (), ptr @_Z4foo9v.resolver
  42 //.
  43 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo1v.default(
  44 // CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
  45 // CHECK-NEXT:  entry:
  46 // CHECK-NEXT:    ret i32 1
  47 //
  48 //
  49 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo1v._m(
  50 // CHECK-SAME: ) #[[ATTR0]] {
  51 // CHECK-NEXT:  entry:
  52 // CHECK-NEXT:    ret i32 1
  53 //
  54 //
  55 // CHECK-LABEL: define weak_odr ptr @_Z4foo1v.resolver() comdat {
  56 // CHECK-NEXT:  resolver_entry:
  57 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
  58 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
  59 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 4096
  60 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4096
  61 // CHECK-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
  62 // CHECK:       resolver_return:
  63 // CHECK-NEXT:    ret ptr @_Z4foo1v._m
  64 // CHECK:       resolver_else:
  65 // CHECK-NEXT:    ret ptr @_Z4foo1v.default
  66 //
  67 //
  68 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v.default(
  69 // CHECK-SAME: ) #[[ATTR0]] {
  70 // CHECK-NEXT:  entry:
  71 // CHECK-NEXT:    ret i32 2
  72 //
  73 //
  74 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v._zbb(
  75 // CHECK-SAME: ) #[[ATTR1:[0-9]+]] {
  76 // CHECK-NEXT:  entry:
  77 // CHECK-NEXT:    ret i32 2
  78 //
  79 //
  80 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v._m(
  81 // CHECK-SAME: ) #[[ATTR0]] {
  82 // CHECK-NEXT:  entry:
  83 // CHECK-NEXT:    ret i32 2
  84 //
  85 //
  86 // CHECK-LABEL: define weak_odr ptr @_Z4foo2v.resolver() comdat {
  87 // CHECK-NEXT:  resolver_entry:
  88 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
  89 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
  90 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 268435456
  91 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435456
  92 // CHECK-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
  93 // CHECK:       resolver_return:
  94 // CHECK-NEXT:    ret ptr @_Z4foo2v._zbb
  95 // CHECK:       resolver_else:
  96 // CHECK-NEXT:    [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
  97 // CHECK-NEXT:    [[TMP4:%.*]] = and i64 [[TMP3]], 4096
  98 // CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 4096
  99 // CHECK-NEXT:    br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 100 // CHECK:       resolver_return1:
 101 // CHECK-NEXT:    ret ptr @_Z4foo2v._m
 102 // CHECK:       resolver_else2:
 103 // CHECK-NEXT:    ret ptr @_Z4foo2v.default
 104 //
 105 //
 106 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo3v.default(
 107 // CHECK-SAME: ) #[[ATTR0]] {
 108 // CHECK-NEXT:  entry:
 109 // CHECK-NEXT:    ret i32 3
 110 //
 111 //
 112 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo3v._c_zbb(
 113 // CHECK-SAME: ) #[[ATTR2:[0-9]+]] {
 114 // CHECK-NEXT:  entry:
 115 // CHECK-NEXT:    ret i32 3
 116 //
 117 //
 118 // CHECK-LABEL: define weak_odr ptr @_Z4foo3v.resolver() comdat {
 119 // CHECK-NEXT:  resolver_entry:
 120 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
 121 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 122 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 268435460
 123 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435460
 124 // CHECK-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 125 // CHECK:       resolver_return:
 126 // CHECK-NEXT:    ret ptr @_Z4foo3v._c_zbb
 127 // CHECK:       resolver_else:
 128 // CHECK-NEXT:    ret ptr @_Z4foo3v.default
 129 //
 130 //
 131 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v.default(
 132 // CHECK-SAME: ) #[[ATTR0]] {
 133 // CHECK-NEXT:  entry:
 134 // CHECK-NEXT:    ret i32 4
 135 //
 136 //
 137 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v._v_zbb(
 138 // CHECK-SAME: ) #[[ATTR3:[0-9]+]] {
 139 // CHECK-NEXT:  entry:
 140 // CHECK-NEXT:    ret i32 4
 141 //
 142 //
 143 // CHECK-LABEL: define weak_odr ptr @_Z4foo4v.resolver() comdat {
 144 // CHECK-NEXT:  resolver_entry:
 145 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
 146 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 147 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 270532608
 148 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 270532608
 149 // CHECK-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 150 // CHECK:       resolver_return:
 151 // CHECK-NEXT:    ret ptr @_Z4foo4v._v_zbb
 152 // CHECK:       resolver_else:
 153 // CHECK-NEXT:    ret ptr @_Z4foo4v.default
 154 //
 155 //
 156 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo5v.default(
 157 // CHECK-SAME: ) #[[ATTR0]] {
 158 // CHECK-NEXT:  entry:
 159 // CHECK-NEXT:    ret i32 5
 160 //
 161 //
 162 // CHECK-LABEL: define weak_odr ptr @_Z4foo5v.resolver() comdat {
 163 // CHECK-NEXT:  resolver_entry:
 164 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
 165 // CHECK-NEXT:    ret ptr @_Z4foo5v.default
 166 //
 167 //
 168 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v.default(
 169 // CHECK-SAME: ) #[[ATTR0]] {
 170 // CHECK-NEXT:  entry:
 171 // CHECK-NEXT:    ret i32 2
 172 //
 173 //
 174 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v._zvkt(
 175 // CHECK-SAME: ) #[[ATTR4:[0-9]+]] {
 176 // CHECK-NEXT:  entry:
 177 // CHECK-NEXT:    ret i32 2
 178 //
 179 //
 180 // CHECK-LABEL: define weak_odr ptr @_Z4foo6v.resolver() comdat {
 181 // CHECK-NEXT:  resolver_entry:
 182 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
 183 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 184 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 576460752303423488
 185 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 576460752303423488
 186 // CHECK-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 187 // CHECK:       resolver_return:
 188 // CHECK-NEXT:    ret ptr @_Z4foo6v._zvkt
 189 // CHECK:       resolver_else:
 190 // CHECK-NEXT:    ret ptr @_Z4foo6v.default
 191 //
 192 //
 193 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v.default(
 194 // CHECK-SAME: ) #[[ATTR0]] {
 195 // CHECK-NEXT:  entry:
 196 // CHECK-NEXT:    ret i32 2
 197 //
 198 //
 199 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v._zbb(
 200 // CHECK-SAME: ) #[[ATTR1]] {
 201 // CHECK-NEXT:  entry:
 202 // CHECK-NEXT:    ret i32 2
 203 //
 204 //
 205 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v._zba(
 206 // CHECK-SAME: ) #[[ATTR5:[0-9]+]] {
 207 // CHECK-NEXT:  entry:
 208 // CHECK-NEXT:    ret i32 2
 209 //
 210 //
 211 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v._zba_zbb(
 212 // CHECK-SAME: ) #[[ATTR6:[0-9]+]] {
 213 // CHECK-NEXT:  entry:
 214 // CHECK-NEXT:    ret i32 2
 215 //
 216 //
 217 // CHECK-LABEL: define weak_odr ptr @_Z4foo7v.resolver() comdat {
 218 // CHECK-NEXT:  resolver_entry:
 219 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
 220 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 221 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 268435456
 222 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435456
 223 // CHECK-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 224 // CHECK:       resolver_return:
 225 // CHECK-NEXT:    ret ptr @_Z4foo7v._zbb
 226 // CHECK:       resolver_else:
 227 // CHECK-NEXT:    [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 228 // CHECK-NEXT:    [[TMP4:%.*]] = and i64 [[TMP3]], 134217728
 229 // CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 134217728
 230 // CHECK-NEXT:    br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 231 // CHECK:       resolver_return1:
 232 // CHECK-NEXT:    ret ptr @_Z4foo7v._zba
 233 // CHECK:       resolver_else2:
 234 // CHECK-NEXT:    [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 235 // CHECK-NEXT:    [[TMP7:%.*]] = and i64 [[TMP6]], 402653184
 236 // CHECK-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 402653184
 237 // CHECK-NEXT:    br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
 238 // CHECK:       resolver_return3:
 239 // CHECK-NEXT:    ret ptr @_Z4foo7v._zba_zbb
 240 // CHECK:       resolver_else4:
 241 // CHECK-NEXT:    ret ptr @_Z4foo7v.default
 242 //
 243 //
 244 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo8v.default(
 245 // CHECK-SAME: ) #[[ATTR0]] {
 246 // CHECK-NEXT:  entry:
 247 // CHECK-NEXT:    ret i32 2
 248 //
 249 //
 250 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo8v._zbb(
 251 // CHECK-SAME: ) #[[ATTR1]] {
 252 // CHECK-NEXT:  entry:
 253 // CHECK-NEXT:    ret i32 2
 254 //
 255 //
 256 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo8v._zba(
 257 // CHECK-SAME: ) #[[ATTR5]] {
 258 // CHECK-NEXT:  entry:
 259 // CHECK-NEXT:    ret i32 2
 260 //
 261 //
 262 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo8v._zba_zbb(
 263 // CHECK-SAME: ) #[[ATTR6]] {
 264 // CHECK-NEXT:  entry:
 265 // CHECK-NEXT:    ret i32 2
 266 //
 267 //
 268 // CHECK-LABEL: define weak_odr ptr @_Z4foo8v.resolver() comdat {
 269 // CHECK-NEXT:  resolver_entry:
 270 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
 271 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 272 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 402653184
 273 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184
 274 // CHECK-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 275 // CHECK:       resolver_return:
 276 // CHECK-NEXT:    ret ptr @_Z4foo8v._zba_zbb
 277 // CHECK:       resolver_else:
 278 // CHECK-NEXT:    [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 279 // CHECK-NEXT:    [[TMP4:%.*]] = and i64 [[TMP3]], 268435456
 280 // CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 268435456
 281 // CHECK-NEXT:    br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 282 // CHECK:       resolver_return1:
 283 // CHECK-NEXT:    ret ptr @_Z4foo8v._zbb
 284 // CHECK:       resolver_else2:
 285 // CHECK-NEXT:    [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 286 // CHECK-NEXT:    [[TMP7:%.*]] = and i64 [[TMP6]], 134217728
 287 // CHECK-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 134217728
 288 // CHECK-NEXT:    br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
 289 // CHECK:       resolver_return3:
 290 // CHECK-NEXT:    ret ptr @_Z4foo8v._zba
 291 // CHECK:       resolver_else4:
 292 // CHECK-NEXT:    ret ptr @_Z4foo8v.default
 293 //
 294 //
 295 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo9v.default(
 296 // CHECK-SAME: ) #[[ATTR0]] {
 297 // CHECK-NEXT:  entry:
 298 // CHECK-NEXT:    ret i32 2
 299 //
 300 //
 301 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo9v._zbb(
 302 // CHECK-SAME: ) #[[ATTR1]] {
 303 // CHECK-NEXT:  entry:
 304 // CHECK-NEXT:    ret i32 2
 305 //
 306 //
 307 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo9v._zba(
 308 // CHECK-SAME: ) #[[ATTR5]] {
 309 // CHECK-NEXT:  entry:
 310 // CHECK-NEXT:    ret i32 2
 311 //
 312 //
 313 // CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo9v._zba_zbb(
 314 // CHECK-SAME: ) #[[ATTR6]] {
 315 // CHECK-NEXT:  entry:
 316 // CHECK-NEXT:    ret i32 2
 317 //
 318 //
 319 // CHECK-LABEL: define weak_odr ptr @_Z4foo9v.resolver() comdat {
 320 // CHECK-NEXT:  resolver_entry:
 321 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
 322 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 323 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 402653184
 324 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184
 325 // CHECK-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 326 // CHECK:       resolver_return:
 327 // CHECK-NEXT:    ret ptr @_Z4foo9v._zba_zbb
 328 // CHECK:       resolver_else:
 329 // CHECK-NEXT:    [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 330 // CHECK-NEXT:    [[TMP4:%.*]] = and i64 [[TMP3]], 134217728
 331 // CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 134217728
 332 // CHECK-NEXT:    br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 333 // CHECK:       resolver_return1:
 334 // CHECK-NEXT:    ret ptr @_Z4foo9v._zba
 335 // CHECK:       resolver_else2:
 336 // CHECK-NEXT:    [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 337 // CHECK-NEXT:    [[TMP7:%.*]] = and i64 [[TMP6]], 268435456
 338 // CHECK-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 268435456
 339 // CHECK-NEXT:    br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
 340 // CHECK:       resolver_return3:
 341 // CHECK-NEXT:    ret ptr @_Z4foo9v._zbb
 342 // CHECK:       resolver_else4:
 343 // CHECK-NEXT:    ret ptr @_Z4foo9v.default
 344 //
 345 //
 346 // CHECK-LABEL: define dso_local noundef signext i32 @_Z3barv(
 347 // CHECK-SAME: ) #[[ATTR0]] {
 348 // CHECK-NEXT:  entry:
 349 // CHECK-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z4foo1v()
 350 // CHECK-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_Z4foo2v()
 351 // CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
 352 // CHECK-NEXT:    [[CALL2:%.*]] = call noundef signext i32 @_Z4foo3v()
 353 // CHECK-NEXT:    [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]]
 354 // CHECK-NEXT:    [[CALL4:%.*]] = call noundef signext i32 @_Z4foo4v()
 355 // CHECK-NEXT:    [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]]
 356 // CHECK-NEXT:    [[CALL6:%.*]] = call noundef signext i32 @_Z4foo5v()
 357 // CHECK-NEXT:    [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CALL6]]
 358 // CHECK-NEXT:    [[CALL8:%.*]] = call noundef signext i32 @_Z4foo6v()
 359 // CHECK-NEXT:    [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CALL8]]
 360 // CHECK-NEXT:    [[CALL10:%.*]] = call noundef signext i32 @_Z4foo7v()
 361 // CHECK-NEXT:    [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CALL10]]
 362 // CHECK-NEXT:    [[CALL12:%.*]] = call noundef signext i32 @_Z4foo8v()
 363 // CHECK-NEXT:    [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CALL12]]
 364 // CHECK-NEXT:    [[CALL14:%.*]] = call noundef signext i32 @_Z4foo9v()
 365 // CHECK-NEXT:    [[ADD15:%.*]] = add nsw i32 [[ADD13]], [[CALL14]]
 366 // CHECK-NEXT:    ret i32 [[ADD15]]
 367 //
 368 //.
 369 // CHECK: attributes #[[ATTR0]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul" }
 370 // CHECK: attributes #[[ATTR1]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zbb,+zmmul" }
 371 // CHECK: attributes #[[ATTR2]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+c,+i,+m,+zbb,+zmmul" }
 372 // CHECK: attributes #[[ATTR3]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+m,+v,+zbb,+zicsr,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
 373 // CHECK: attributes #[[ATTR4]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul,+zvkt" }
 374 // CHECK: attributes #[[ATTR5]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zba,+zmmul" }
 375 // CHECK: attributes #[[ATTR6]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zba,+zbb,+zmmul" }
 376 //.
 377 // CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
 378 // CHECK: [[META1:![0-9]+]] = !{i32 1, !"target-abi", !"lp64"}
 379 // CHECK: [[META2:![0-9]+]] = !{i32 6, !"riscv-isa", [[META3:![0-9]+]]}
 380 // CHECK: [[META3]] = !{!"rv64i2p1_m2p0_zmmul1p0"}
 381 // CHECK: [[META4:![0-9]+]] = !{i32 8, !"SmallDataLimit", i32 0}
 382 // CHECK: [[META5:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
 383 //.