[AMDGPU][True16][CodeGen] true16 codegen pattern for v_med3_u/i16 (#121850)
[llvm-project.git] / clang / test / CodeGenCXX / pragma-loop-safety-imperfectly_nested.cpp
blob99079f6c03673d1b48f2e4806af137824dc58213
1 // RUN: %clang_cc1 -triple x86_64-apple-darwin -std=c++11 -emit-llvm -o - %s | FileCheck %s
3 // Verify that the outer loop has the llvm.access.group property for the
4 // accesses outside and inside the inner loop, even when the inner loop
5 // is not perfectly nested.
6 void vectorize_imperfectly_nested_test(int *List, int Length) {
7 #pragma clang loop vectorize(assume_safety) interleave(disable) unroll(disable)
8 for (int i = 0; i < Length; ++i) {
9 List[i * Length] = 42;
10 #pragma clang loop vectorize(assume_safety) interleave(disable) unroll(disable)
11 for (int j = 1; j < Length - 1; ++j)
12 List[i * Length + j] = (i + j) * 2;
13 List[(i + 1) * Length - 1] = 21;
18 // CHECK: load i32, ptr %Length.addr, align 4, !llvm.access.group ![[ACCESS_GROUP_2:[0-9]+]]
20 // CHECK: %[[MUL:.+]] = mul nsw i32 %add, 2
21 // CHECK: store i32 %[[MUL]], ptr %{{.+}}, !llvm.access.group ![[ACCESS_GROUP_3:[0-9]+]]
22 // CHECK: br label %{{.+}}, !llvm.loop ![[INNER_LOOPID:[0-9]+]]
23 // CHECK: store i32 21, ptr %{{.+}}, !llvm.access.group ![[ACCESS_GROUP_2]]
24 // CHECK: br label %{{.+}}, !llvm.loop ![[OUTER_LOOPID:[0-9]+]]
26 // CHECK: ![[ACCESS_GROUP_2]] = distinct !{}
27 // CHECK: ![[ACCESS_GROUP_LIST_3:[0-9]+]] = !{![[ACCESS_GROUP_2]], ![[ACCESS_GROUP_4:[0-9]+]]}
28 // CHECK: ![[ACCESS_GROUP_4]] = distinct !{}
29 // CHECK: ![[INNER_LOOPID]] = distinct !{![[INNER_LOOPID]], [[MP:![0-9]+]], ![[PARALLEL_ACCESSES_8:[0-9]+]]
30 // CHECK: [[MP]] = !{!"llvm.loop.mustprogress"}
31 // CHECK: ![[PARALLEL_ACCESSES_8]] = !{!"llvm.loop.parallel_accesses", ![[ACCESS_GROUP_4]]}
32 // CHECK: ![[OUTER_LOOPID]] = distinct !{![[OUTER_LOOPID]], [[MP]], ![[PARALLEL_ACCESSES_10:[0-9]+]]
33 // CHECK: ![[PARALLEL_ACCESSES_10]] = !{!"llvm.loop.parallel_accesses", ![[ACCESS_GROUP_2]]}