[AMDGPU][True16][CodeGen] true16 codegen pattern for v_med3_u/i16 (#121850)
[llvm-project.git] / clang / test / CodeGenCXX / trivial_abi_debuginfo.cpp
blob3e486140b8acd8696bad18604fbe3da8622e0624
1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --functions "makeTrivial" --version 2
2 // RUN: %clang_cc1 -debug-info-kind=limited -triple x86_64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s
4 struct __attribute__((trivial_abi)) Trivial {
5 ~Trivial() {}
6 int ivar = 10;
7 };
9 // The dbg.declare should be on %retval, not on %nrvo.
11 // CHECK-LABEL: define dso_local i32 @_Z11makeTrivialv
12 // CHECK-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG5:![0-9]+]] {
13 // CHECK-NEXT: entry:
14 // CHECK-NEXT: [[RETVAL:%.*]] = alloca [[STRUCT_TRIVIAL:%.*]], align 4
15 // CHECK-NEXT: [[NRVO:%.*]] = alloca i1, align 1
16 // CHECK-NEXT: store i1 false, ptr [[NRVO]], align 1, !dbg [[DBG18:![0-9]+]]
17 // CHECK-NEXT: #dbg_declare(ptr [[RETVAL]], [[META19:![0-9]+]], !DIExpression(), [[META20:![0-9]+]])
18 // CHECK-NEXT: call void @_ZN7TrivialC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[RETVAL]]) #[[ATTR1:[0-9]+]], !dbg [[META20]]
19 // CHECK-NEXT: store i1 true, ptr [[NRVO]], align 1, !dbg [[DBG21:![0-9]+]]
20 // CHECK-NEXT: [[NRVO_VAL:%.*]] = load i1, ptr [[NRVO]], align 1, !dbg [[DBG22:![0-9]+]]
21 // CHECK-NEXT: br i1 [[NRVO_VAL]], label [[NRVO_SKIPDTOR:%.*]], label [[NRVO_UNUSED:%.*]], !dbg [[DBG22]]
22 // CHECK: nrvo.unused:
23 // CHECK-NEXT: call void @_ZN7TrivialD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[RETVAL]]) #[[ATTR1]], !dbg [[DBG22]]
24 // CHECK-NEXT: br label [[NRVO_SKIPDTOR]], !dbg [[DBG22]]
25 // CHECK: nrvo.skipdtor:
26 // CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[STRUCT_TRIVIAL]], ptr [[RETVAL]], i32 0, i32 0, !dbg [[DBG22]]
27 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[COERCE_DIVE]], align 4, !dbg [[DBG22]]
28 // CHECK-NEXT: ret i32 [[TMP0]], !dbg [[DBG22]]
30 Trivial makeTrivial() {
31 Trivial ret_val;
32 return ret_val;