clang/test/OpenMP/for_firstprivate_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
   3 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s
   4 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
   5 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
   6 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4
   7
   8 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
   9 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s
  10 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  11 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  12 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  13 // expected-no-diagnostics
  14 #ifndef HEADER
  15 #define HEADER
  16
  17 struct St {
  18   int a, b;
  19   St() : a(0), b(0) {}
  20   St(const St &st) : a(st.a + st.b), b(0) {}
  21   ~St() {}
  22 };
  23
  24 volatile int g = 1212;
  25 volatile int &g1 = g;
  26
  27 template <class T>
  28 struct S {
  29   T f;
  30   S(T a) : f(a + g) {}
  31   S() : f(g) {}
  32   S(const S &s, St t = St()) : f(s.f + t.a) {}
  33   operator T() { return T(); }
  34   ~S() {}
  35 };
  36
  37
  38 template <typename T>
  39 T tmain() {
  40   S<T> test;
  41   T t_var = T();
  42   T vec[] = {1, 2};
  43   S<T> s_arr[] = {1, 2};
  44   S<T> &var = test;
  45 #pragma omp parallel
  46 #pragma omp for firstprivate(t_var, vec, s_arr, var)
  47   for (int i = 0; i < 2; ++i) {
  48     vec[i] = t_var;
  49     s_arr[i] = var;
  50   }
  51   return T();
  52 }
  53
  54 S<float> test;
  55 int t_var = 333;
  56 int vec[] = {1, 2};
  57 S<float> s_arr[] = {1, 2};
  58 S<float> var(3);
  59
  60 int main() {
  61   static int sivar;
  62 #ifdef LAMBDA
  63   [&]() {
  64 #pragma omp parallel
  65 #pragma omp for firstprivate(g, g1, sivar)
  66   for (int i = 0; i < 2; ++i) {
  67     // Skip temp vars for loop
  68
  69
  70
  71
  72     g = 1;
  73     g1 = 2;
  74     sivar = 3;
  75
  76     [&]() {
  77       g = 4;
  78       g1 = 5;
  79       sivar = 6;
  80
  81     }();
  82   }
  83   }();
  84   return 0;
  85 #elif defined(BLOCKS)
  86   ^{
  87 #pragma omp parallel
  88 #pragma omp for firstprivate(g, g1, sivar)
  89   for (int i = 0; i < 2; ++i) {
  90     // Skip temp vars for loop
  91
  92
  93
  94
  95     g = 1;
  96     g1 =1;
  97     sivar = 2;
  98     ^{
  99       g = 2;
 100       g1 = 2;
 101       sivar = 4;
 102     }();
 103   }
 104   }();
 105   return 0;
 106 #else
 107 #pragma omp for firstprivate(t_var, vec, s_arr, var, sivar)
 108   for (int i = 0; i < 2; ++i) {
 109     vec[i] = t_var;
 110     s_arr[i] = var;
 111     sivar += i;
 112   }
 113   return tmain<int>();
 114 #endif
 115 }
 116
 117 // Skip temp vars for loop
 118
 119 // firstprivate t_var(t_var)
 120
 121 // firstprivate vec(vec)
 122
 123 // firstprivate s_arr(s_arr)
 124
 125 // firstprivate var(var)
 126
 127 // firstprivate (sivar)
 128
 129 // Synchronization for initialization.
 130
 131
 132 // ~(firstprivate var), ~(firstprivate s_arr)
 133
 134
 135
 136 // Skip temp vars for loop
 137
 138
 139 // firstprivate vec(vec)
 140
 141 // firstprivate s_arr(s_arr)
 142
 143 // firstprivate var(var)
 144
 145 // No synchronization for initialization.
 146
 147
 148 // ~(firstprivate var), ~(firstprivate s_arr)
 149 #endif
 150
 151 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init
 152 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {
 153 // CHECK1-NEXT:  entry:
 154 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
 155 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
 156 // CHECK1-NEXT:    ret void
 157 //
 158 //
 159 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
 160 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {
 161 // CHECK1-NEXT:  entry:
 162 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 163 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 164 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 165 // CHECK1-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 166 // CHECK1-NEXT:    ret void
 167 //
 168 //
 169 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
 170 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 171 // CHECK1-NEXT:  entry:
 172 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 173 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 174 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 175 // CHECK1-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
 176 // CHECK1-NEXT:    ret void
 177 //
 178 //
 179 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
 180 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 181 // CHECK1-NEXT:  entry:
 182 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 183 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 184 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 185 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 186 // CHECK1-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
 187 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
 188 // CHECK1-NEXT:    store float [[CONV]], ptr [[F]], align 4
 189 // CHECK1-NEXT:    ret void
 190 //
 191 //
 192 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
 193 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 194 // CHECK1-NEXT:  entry:
 195 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 196 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 197 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 198 // CHECK1-NEXT:    ret void
 199 //
 200 //
 201 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
 202 // CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
 203 // CHECK1-NEXT:  entry:
 204 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
 205 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
 206 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
 207 // CHECK1-NEXT:    ret void
 208 //
 209 //
 210 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
 211 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 212 // CHECK1-NEXT:  entry:
 213 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 214 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 215 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 216 // CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 217 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 218 // CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 219 // CHECK1-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
 220 // CHECK1-NEXT:    ret void
 221 //
 222 //
 223 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
 224 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
 225 // CHECK1-NEXT:  entry:
 226 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 227 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 228 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 229 // CHECK1:       arraydestroy.body:
 230 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 231 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 232 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 233 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
 234 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
 235 // CHECK1:       arraydestroy.done1:
 236 // CHECK1-NEXT:    ret void
 237 //
 238 //
 239 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
 240 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 241 // CHECK1-NEXT:  entry:
 242 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 243 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 244 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 245 // CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 246 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 247 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 248 // CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 249 // CHECK1-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
 250 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
 251 // CHECK1-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
 252 // CHECK1-NEXT:    store float [[ADD]], ptr [[F]], align 4
 253 // CHECK1-NEXT:    ret void
 254 //
 255 //
 256 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
 257 // CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
 258 // CHECK1-NEXT:  entry:
 259 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
 260 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
 261 // CHECK1-NEXT:    ret void
 262 //
 263 //
 264 // CHECK1-LABEL: define {{[^@]+}}@main
 265 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
 266 // CHECK1-NEXT:  entry:
 267 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 268 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 269 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 270 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 271 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 272 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 273 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 274 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 275 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 276 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
 277 // CHECK1-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
 278 // CHECK1-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
 279 // CHECK1-NEXT:    [[AGG_TMP2:%.*]] = alloca [[STRUCT_ST]], align 4
 280 // CHECK1-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
 281 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 282 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
 283 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 284 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 285 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 286 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 287 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 288 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr @t_var, align 4
 289 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[T_VAR]], align 4
 290 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @vec, i64 8, i1 false)
 291 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 292 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
 293 // CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP2]]
 294 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
 295 // CHECK1:       omp.arraycpy.body:
 296 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ @s_arr, [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
 297 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
 298 // CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
 299 // CHECK1-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])
 300 // CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
 301 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
 302 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
 303 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP2]]
 304 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]
 305 // CHECK1:       omp.arraycpy.done1:
 306 // CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP2]])
 307 // CHECK1-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], ptr noundef nonnull align 4 dereferenceable(4) @var, ptr noundef [[AGG_TMP2]])
 308 // CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]]
 309 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
 310 // CHECK1-NEXT:    store i32 [[TMP3]], ptr [[SIVAR]], align 4
 311 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 312 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 313 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
 314 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 315 // CHECK1:       cond.true:
 316 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 317 // CHECK1:       cond.false:
 318 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 319 // CHECK1-NEXT:    br label [[COND_END]]
 320 // CHECK1:       cond.end:
 321 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
 322 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 323 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 324 // CHECK1-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
 325 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 326 // CHECK1:       omp.inner.for.cond:
 327 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 328 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 329 // CHECK1-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
 330 // CHECK1-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
 331 // CHECK1:       omp.inner.for.cond.cleanup:
 332 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
 333 // CHECK1:       omp.inner.for.body:
 334 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 335 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
 336 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 337 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
 338 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4
 339 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4
 340 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
 341 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]
 342 // CHECK1-NEXT:    store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4
 343 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I]], align 4
 344 // CHECK1-NEXT:    [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64
 345 // CHECK1-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]]
 346 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[VAR]], i64 4, i1 false)
 347 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
 348 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4
 349 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
 350 // CHECK1-NEXT:    store i32 [[ADD6]], ptr [[SIVAR]], align 4
 351 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 352 // CHECK1:       omp.body.continue:
 353 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 354 // CHECK1:       omp.inner.for.inc:
 355 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 356 // CHECK1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1
 357 // CHECK1-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4
 358 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 359 // CHECK1:       omp.inner.for.end:
 360 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 361 // CHECK1:       omp.loop.exit:
 362 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])
 363 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
 364 // CHECK1-NEXT:    [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 365 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN8]], i64 2
 366 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 367 // CHECK1:       arraydestroy.body:
 368 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 369 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 370 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 371 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
 372 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
 373 // CHECK1:       arraydestroy.done9:
 374 // CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP0]])
 375 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
 376 // CHECK1-NEXT:    ret i32 [[CALL]]
 377 //
 378 //
 379 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev
 380 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 381 // CHECK1-NEXT:  entry:
 382 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 383 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 384 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 385 // CHECK1-NEXT:    call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])
 386 // CHECK1-NEXT:    ret void
 387 //
 388 //
 389 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
 390 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 391 // CHECK1-NEXT:  entry:
 392 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 393 // CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
 394 // CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
 395 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 396 // CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
 397 // CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
 398 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 399 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
 400 // CHECK1-NEXT:    call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])
 401 // CHECK1-NEXT:    ret void
 402 //
 403 //
 404 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev
 405 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 406 // CHECK1-NEXT:  entry:
 407 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 408 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 409 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 410 // CHECK1-NEXT:    call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
 411 // CHECK1-NEXT:    ret void
 412 //
 413 //
 414 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
 415 // CHECK1-SAME: () #[[ATTR1]] {
 416 // CHECK1-NEXT:  entry:
 417 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 418 // CHECK1-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
 419 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 420 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 421 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
 422 // CHECK1-NEXT:    [[VAR:%.*]] = alloca ptr, align 8
 423 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
 424 // CHECK1-NEXT:    store i32 0, ptr [[T_VAR]], align 4
 425 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
 426 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)
 427 // CHECK1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1
 428 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
 429 // CHECK1-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8
 430 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8
 431 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[T_VAR]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP0]])
 432 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 433 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 434 // CHECK1-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
 435 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 436 // CHECK1:       arraydestroy.body:
 437 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 438 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 439 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 440 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
 441 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
 442 // CHECK1:       arraydestroy.done1:
 443 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
 444 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4
 445 // CHECK1-NEXT:    ret i32 [[TMP2]]
 446 //
 447 //
 448 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev
 449 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 450 // CHECK1-NEXT:  entry:
 451 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 452 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 453 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 454 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
 455 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 4
 456 // CHECK1-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
 457 // CHECK1-NEXT:    store i32 0, ptr [[B]], align 4
 458 // CHECK1-NEXT:    ret void
 459 //
 460 //
 461 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
 462 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 463 // CHECK1-NEXT:  entry:
 464 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 465 // CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
 466 // CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
 467 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 468 // CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
 469 // CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
 470 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 471 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 472 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
 473 // CHECK1-NEXT:    [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0
 474 // CHECK1-NEXT:    [[TMP1:%.*]] = load float, ptr [[F2]], align 4
 475 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
 476 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 4
 477 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
 478 // CHECK1-NEXT:    [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
 479 // CHECK1-NEXT:    store float [[ADD]], ptr [[F]], align 4
 480 // CHECK1-NEXT:    ret void
 481 //
 482 //
 483 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev
 484 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 485 // CHECK1-NEXT:  entry:
 486 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 487 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 488 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 489 // CHECK1-NEXT:    ret void
 490 //
 491 //
 492 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
 493 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 494 // CHECK1-NEXT:  entry:
 495 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 496 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 497 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 498 // CHECK1-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 499 // CHECK1-NEXT:    ret void
 500 //
 501 //
 502 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
 503 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 504 // CHECK1-NEXT:  entry:
 505 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 506 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 507 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 508 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
 509 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 510 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 511 // CHECK1-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
 512 // CHECK1-NEXT:    ret void
 513 //
 514 //
 515 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined
 516 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR6:[0-9]+]] {
 517 // CHECK1-NEXT:  entry:
 518 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 519 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 520 // CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca ptr, align 8
 521 // CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
 522 // CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
 523 // CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
 524 // CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
 525 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
 526 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 527 // CHECK1-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4
 528 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 529 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 530 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 531 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 532 // CHECK1-NEXT:    [[T_VAR3:%.*]] = alloca i32, align 4
 533 // CHECK1-NEXT:    [[VEC4:%.*]] = alloca [2 x i32], align 4
 534 // CHECK1-NEXT:    [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4
 535 // CHECK1-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
 536 // CHECK1-NEXT:    [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
 537 // CHECK1-NEXT:    [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4
 538 // CHECK1-NEXT:    [[_TMP9:%.*]] = alloca ptr, align 8
 539 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 540 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 541 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 542 // CHECK1-NEXT:    store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
 543 // CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
 544 // CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
 545 // CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
 546 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8
 547 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
 548 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
 549 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
 550 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[TMP]], align 8
 551 // CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8
 552 // CHECK1-NEXT:    store ptr [[TMP4]], ptr [[_TMP1]], align 8
 553 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 554 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 555 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 556 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 557 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4
 558 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[T_VAR3]], align 4
 559 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i64 8, i1 false)
 560 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0
 561 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
 562 // CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]]
 563 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
 564 // CHECK1:       omp.arraycpy.body:
 565 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
 566 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
 567 // CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
 568 // CHECK1-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])
 569 // CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
 570 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
 571 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
 572 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
 573 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]]
 574 // CHECK1:       omp.arraycpy.done6:
 575 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 8
 576 // CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]])
 577 // CHECK1-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP7]], ptr noundef [[AGG_TMP8]])
 578 // CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]]
 579 // CHECK1-NEXT:    store ptr [[VAR7]], ptr [[_TMP9]], align 8
 580 // CHECK1-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 581 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
 582 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 583 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 584 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1
 585 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 586 // CHECK1:       cond.true:
 587 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 588 // CHECK1:       cond.false:
 589 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 590 // CHECK1-NEXT:    br label [[COND_END]]
 591 // CHECK1:       cond.end:
 592 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
 593 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 594 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 595 // CHECK1-NEXT:    store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4
 596 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 597 // CHECK1:       omp.inner.for.cond:
 598 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 599 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 600 // CHECK1-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
 601 // CHECK1-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
 602 // CHECK1:       omp.inner.for.cond.cleanup:
 603 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
 604 // CHECK1:       omp.inner.for.body:
 605 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 606 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
 607 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 608 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
 609 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[T_VAR3]], align 4
 610 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4
 611 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
 612 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]]
 613 // CHECK1-NEXT:    store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4
 614 // CHECK1-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[_TMP9]], align 8
 615 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[I]], align 4
 616 // CHECK1-NEXT:    [[IDXPROM11:%.*]] = sext i32 [[TMP19]] to i64
 617 // CHECK1-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM11]]
 618 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX12]], ptr align 4 [[TMP18]], i64 4, i1 false)
 619 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 620 // CHECK1:       omp.body.continue:
 621 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 622 // CHECK1:       omp.inner.for.inc:
 623 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 624 // CHECK1-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP20]], 1
 625 // CHECK1-NEXT:    store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4
 626 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 627 // CHECK1:       omp.inner.for.end:
 628 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 629 // CHECK1:       omp.loop.exit:
 630 // CHECK1-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 631 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4
 632 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]])
 633 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]]
 634 // CHECK1-NEXT:    [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0
 635 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN14]], i64 2
 636 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 637 // CHECK1:       arraydestroy.body:
 638 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 639 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 640 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 641 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
 642 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
 643 // CHECK1:       arraydestroy.done15:
 644 // CHECK1-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 645 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4
 646 // CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP25]])
 647 // CHECK1-NEXT:    ret void
 648 //
 649 //
 650 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
 651 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 652 // CHECK1-NEXT:  entry:
 653 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 654 // CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
 655 // CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
 656 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 657 // CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
 658 // CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
 659 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 660 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
 661 // CHECK1-NEXT:    call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])
 662 // CHECK1-NEXT:    ret void
 663 //
 664 //
 665 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
 666 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 667 // CHECK1-NEXT:  entry:
 668 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 669 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 670 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 671 // CHECK1-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
 672 // CHECK1-NEXT:    ret void
 673 //
 674 //
 675 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
 676 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 677 // CHECK1-NEXT:  entry:
 678 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 679 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 680 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 681 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
 682 // CHECK1-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
 683 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
 684 // CHECK1-NEXT:    ret void
 685 //
 686 //
 687 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
 688 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 689 // CHECK1-NEXT:  entry:
 690 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 691 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 692 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 693 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
 694 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 695 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
 696 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 697 // CHECK1-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
 698 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
 699 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
 700 // CHECK1-NEXT:    ret void
 701 //
 702 //
 703 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
 704 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 705 // CHECK1-NEXT:  entry:
 706 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 707 // CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
 708 // CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
 709 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 710 // CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
 711 // CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
 712 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 713 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
 714 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
 715 // CHECK1-NEXT:    [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0
 716 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[F2]], align 4
 717 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
 718 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 4
 719 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
 720 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
 721 // CHECK1-NEXT:    ret void
 722 //
 723 //
 724 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
 725 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 726 // CHECK1-NEXT:  entry:
 727 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 728 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 729 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 730 // CHECK1-NEXT:    ret void
 731 //
 732 //
 733 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_for_firstprivate_codegen.cpp
 734 // CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
 735 // CHECK1-NEXT:  entry:
 736 // CHECK1-NEXT:    call void @__cxx_global_var_init()
 737 // CHECK1-NEXT:    call void @__cxx_global_var_init.1()
 738 // CHECK1-NEXT:    call void @__cxx_global_var_init.2()
 739 // CHECK1-NEXT:    ret void
 740 //
 741 //
 742 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init
 743 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {
 744 // CHECK3-NEXT:  entry:
 745 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
 746 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
 747 // CHECK3-NEXT:    ret void
 748 //
 749 //
 750 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
 751 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {
 752 // CHECK3-NEXT:  entry:
 753 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 754 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 755 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 756 // CHECK3-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 757 // CHECK3-NEXT:    ret void
 758 //
 759 //
 760 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
 761 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 762 // CHECK3-NEXT:  entry:
 763 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 764 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 765 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 766 // CHECK3-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
 767 // CHECK3-NEXT:    ret void
 768 //
 769 //
 770 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
 771 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 772 // CHECK3-NEXT:  entry:
 773 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 774 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 775 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 776 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 777 // CHECK3-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
 778 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
 779 // CHECK3-NEXT:    store float [[CONV]], ptr [[F]], align 4
 780 // CHECK3-NEXT:    ret void
 781 //
 782 //
 783 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
 784 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 785 // CHECK3-NEXT:  entry:
 786 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 787 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 788 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 789 // CHECK3-NEXT:    ret void
 790 //
 791 //
 792 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
 793 // CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
 794 // CHECK3-NEXT:  entry:
 795 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
 796 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
 797 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
 798 // CHECK3-NEXT:    ret void
 799 //
 800 //
 801 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
 802 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 803 // CHECK3-NEXT:  entry:
 804 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 805 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 806 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 807 // CHECK3-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 808 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 809 // CHECK3-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 810 // CHECK3-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
 811 // CHECK3-NEXT:    ret void
 812 //
 813 //
 814 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
 815 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
 816 // CHECK3-NEXT:  entry:
 817 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 818 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 819 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 820 // CHECK3:       arraydestroy.body:
 821 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 822 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 823 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 824 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
 825 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
 826 // CHECK3:       arraydestroy.done1:
 827 // CHECK3-NEXT:    ret void
 828 //
 829 //
 830 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
 831 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 832 // CHECK3-NEXT:  entry:
 833 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 834 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 835 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 836 // CHECK3-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 837 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 838 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 839 // CHECK3-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 840 // CHECK3-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
 841 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
 842 // CHECK3-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
 843 // CHECK3-NEXT:    store float [[ADD]], ptr [[F]], align 4
 844 // CHECK3-NEXT:    ret void
 845 //
 846 //
 847 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
 848 // CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
 849 // CHECK3-NEXT:  entry:
 850 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
 851 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
 852 // CHECK3-NEXT:    ret void
 853 //
 854 //
 855 // CHECK3-LABEL: define {{[^@]+}}@main
 856 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
 857 // CHECK3-NEXT:  entry:
 858 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 859 // CHECK3-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8
 860 // CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 861 // CHECK3-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0
 862 // CHECK3-NEXT:    store ptr @_ZZ4mainE5sivar, ptr [[TMP0]], align 8
 863 // CHECK3-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(8) [[REF_TMP]])
 864 // CHECK3-NEXT:    ret i32 0
 865 //
 866 //
 867 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_for_firstprivate_codegen.cpp
 868 // CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
 869 // CHECK3-NEXT:  entry:
 870 // CHECK3-NEXT:    call void @__cxx_global_var_init()
 871 // CHECK3-NEXT:    call void @__cxx_global_var_init.1()
 872 // CHECK3-NEXT:    call void @__cxx_global_var_init.2()
 873 // CHECK3-NEXT:    ret void
 874 //
 875 //
 876 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init
 877 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {
 878 // CHECK4-NEXT:  entry:
 879 // CHECK4-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
 880 // CHECK4-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
 881 // CHECK4-NEXT:    ret void
 882 //
 883 //
 884 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
 885 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {
 886 // CHECK4-NEXT:  entry:
 887 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 888 // CHECK4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 889 // CHECK4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 890 // CHECK4-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 891 // CHECK4-NEXT:    ret void
 892 //
 893 //
 894 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
 895 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 896 // CHECK4-NEXT:  entry:
 897 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 898 // CHECK4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 899 // CHECK4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 900 // CHECK4-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
 901 // CHECK4-NEXT:    ret void
 902 //
 903 //
 904 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
 905 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 906 // CHECK4-NEXT:  entry:
 907 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 908 // CHECK4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 909 // CHECK4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 910 // CHECK4-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 911 // CHECK4-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
 912 // CHECK4-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
 913 // CHECK4-NEXT:    store float [[CONV]], ptr [[F]], align 4
 914 // CHECK4-NEXT:    ret void
 915 //
 916 //
 917 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
 918 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 919 // CHECK4-NEXT:  entry:
 920 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 921 // CHECK4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 922 // CHECK4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 923 // CHECK4-NEXT:    ret void
 924 //
 925 //
 926 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
 927 // CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
 928 // CHECK4-NEXT:  entry:
 929 // CHECK4-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
 930 // CHECK4-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
 931 // CHECK4-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
 932 // CHECK4-NEXT:    ret void
 933 //
 934 //
 935 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
 936 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 937 // CHECK4-NEXT:  entry:
 938 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 939 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 940 // CHECK4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 941 // CHECK4-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 942 // CHECK4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 943 // CHECK4-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 944 // CHECK4-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
 945 // CHECK4-NEXT:    ret void
 946 //
 947 //
 948 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
 949 // CHECK4-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
 950 // CHECK4-NEXT:  entry:
 951 // CHECK4-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 952 // CHECK4-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 953 // CHECK4-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 954 // CHECK4:       arraydestroy.body:
 955 // CHECK4-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 956 // CHECK4-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 957 // CHECK4-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 958 // CHECK4-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
 959 // CHECK4-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
 960 // CHECK4:       arraydestroy.done1:
 961 // CHECK4-NEXT:    ret void
 962 //
 963 //
 964 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
 965 // CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 966 // CHECK4-NEXT:  entry:
 967 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 968 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 969 // CHECK4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 970 // CHECK4-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 971 // CHECK4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 972 // CHECK4-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 973 // CHECK4-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 974 // CHECK4-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
 975 // CHECK4-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
 976 // CHECK4-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
 977 // CHECK4-NEXT:    store float [[ADD]], ptr [[F]], align 4
 978 // CHECK4-NEXT:    ret void
 979 //
 980 //
 981 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
 982 // CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
 983 // CHECK4-NEXT:  entry:
 984 // CHECK4-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
 985 // CHECK4-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
 986 // CHECK4-NEXT:    ret void
 987 //
 988 //
 989 // CHECK4-LABEL: define {{[^@]+}}@main
 990 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] {
 991 // CHECK4-NEXT:  entry:
 992 // CHECK4-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 993 // CHECK4-NEXT:    [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32 }>, align 8
 994 // CHECK4-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 995 // CHECK4-NEXT:    [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 0
 996 // CHECK4-NEXT:    store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8
 997 // CHECK4-NEXT:    [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 1
 998 // CHECK4-NEXT:    store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8
 999 // CHECK4-NEXT:    [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 2
1000 // CHECK4-NEXT:    store i32 0, ptr [[BLOCK_RESERVED]], align 4
1001 // CHECK4-NEXT:    [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 3
1002 // CHECK4-NEXT:    store ptr @__main_block_invoke, ptr [[BLOCK_INVOKE]], align 8
1003 // CHECK4-NEXT:    [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 4
1004 // CHECK4-NEXT:    store ptr @__block_descriptor_tmp.3, ptr [[BLOCK_DESCRIPTOR]], align 8
1005 // CHECK4-NEXT:    [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 5
1006 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
1007 // CHECK4-NEXT:    store i32 [[TMP0]], ptr [[BLOCK_CAPTURED]], align 8
1008 // CHECK4-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3
1009 // CHECK4-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
1010 // CHECK4-NEXT:    call void [[TMP2]](ptr noundef [[BLOCK]])
1011 // CHECK4-NEXT:    ret i32 0
1012 //
1013 //
1014 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke
1015 // CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR4:[0-9]+]] {
1016 // CHECK4-NEXT:  entry:
1017 // CHECK4-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8
1018 // CHECK4-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 8
1019 // CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
1020 // CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8
1021 // CHECK4-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 1, ptr @__main_block_invoke.omp_outlined, ptr @_ZZ4mainE5sivar)
1022 // CHECK4-NEXT:    ret void
1023 //
1024 //
1025 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined
1026 // CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] {
1027 // CHECK4-NEXT:  entry:
1028 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1029 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1030 // CHECK4-NEXT:    [[SIVAR_ADDR:%.*]] = alloca ptr, align 8
1031 // CHECK4-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
1032 // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1033 // CHECK4-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1034 // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1035 // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1036 // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1037 // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1038 // CHECK4-NEXT:    [[G:%.*]] = alloca i32, align 4
1039 // CHECK4-NEXT:    [[G1:%.*]] = alloca i32, align 4
1040 // CHECK4-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 8
1041 // CHECK4-NEXT:    [[SIVAR3:%.*]] = alloca i32, align 4
1042 // CHECK4-NEXT:    [[I:%.*]] = alloca i32, align 4
1043 // CHECK4-NEXT:    [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, ptr, i32, i32 }>, align 8
1044 // CHECK4-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1045 // CHECK4-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1046 // CHECK4-NEXT:    store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
1047 // CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8
1048 // CHECK4-NEXT:    [[TMP1:%.*]] = load ptr, ptr @g1, align 8
1049 // CHECK4-NEXT:    store ptr [[TMP1]], ptr [[TMP]], align 8
1050 // CHECK4-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1051 // CHECK4-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1052 // CHECK4-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1053 // CHECK4-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1054 // CHECK4-NEXT:    [[TMP2:%.*]] = load volatile i32, ptr @g, align 4
1055 // CHECK4-NEXT:    store i32 [[TMP2]], ptr [[G]], align 4
1056 // CHECK4-NEXT:    [[TMP3:%.*]] = load volatile i32, ptr @g, align 4
1057 // CHECK4-NEXT:    store i32 [[TMP3]], ptr [[G1]], align 4
1058 // CHECK4-NEXT:    store ptr [[G1]], ptr [[_TMP2]], align 8
1059 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP0]], align 4
1060 // CHECK4-NEXT:    store i32 [[TMP4]], ptr [[SIVAR3]], align 4
1061 // CHECK4-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1062 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
1063 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1064 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1065 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1
1066 // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1067 // CHECK4:       cond.true:
1068 // CHECK4-NEXT:    br label [[COND_END:%.*]]
1069 // CHECK4:       cond.false:
1070 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1071 // CHECK4-NEXT:    br label [[COND_END]]
1072 // CHECK4:       cond.end:
1073 // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
1074 // CHECK4-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1075 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1076 // CHECK4-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
1077 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1078 // CHECK4:       omp.inner.for.cond:
1079 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1080 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1081 // CHECK4-NEXT:    [[CMP4:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
1082 // CHECK4-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1083 // CHECK4:       omp.inner.for.body:
1084 // CHECK4-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1085 // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
1086 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1087 // CHECK4-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
1088 // CHECK4-NEXT:    store i32 1, ptr [[G]], align 4
1089 // CHECK4-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[_TMP2]], align 8
1090 // CHECK4-NEXT:    store volatile i32 1, ptr [[TMP13]], align 4
1091 // CHECK4-NEXT:    store i32 2, ptr [[SIVAR3]], align 4
1092 // CHECK4-NEXT:    [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 0
1093 // CHECK4-NEXT:    store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8
1094 // CHECK4-NEXT:    [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 1
1095 // CHECK4-NEXT:    store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8
1096 // CHECK4-NEXT:    [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 2
1097 // CHECK4-NEXT:    store i32 0, ptr [[BLOCK_RESERVED]], align 4
1098 // CHECK4-NEXT:    [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 3
1099 // CHECK4-NEXT:    store ptr @var_block_invoke, ptr [[BLOCK_INVOKE]], align 8
1100 // CHECK4-NEXT:    [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 4
1101 // CHECK4-NEXT:    store ptr @__block_descriptor_tmp, ptr [[BLOCK_DESCRIPTOR]], align 8
1102 // CHECK4-NEXT:    [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 6
1103 // CHECK4-NEXT:    [[TMP14:%.*]] = load volatile i32, ptr [[G]], align 4
1104 // CHECK4-NEXT:    store volatile i32 [[TMP14]], ptr [[BLOCK_CAPTURED]], align 8
1105 // CHECK4-NEXT:    [[BLOCK_CAPTURED5:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 5
1106 // CHECK4-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[_TMP2]], align 8
1107 // CHECK4-NEXT:    store ptr [[TMP15]], ptr [[BLOCK_CAPTURED5]], align 8
1108 // CHECK4-NEXT:    [[BLOCK_CAPTURED6:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 7
1109 // CHECK4-NEXT:    [[TMP16:%.*]] = load i32, ptr [[SIVAR3]], align 4
1110 // CHECK4-NEXT:    store i32 [[TMP16]], ptr [[BLOCK_CAPTURED6]], align 4
1111 // CHECK4-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3
1112 // CHECK4-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8
1113 // CHECK4-NEXT:    call void [[TMP18]](ptr noundef [[BLOCK]])
1114 // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1115 // CHECK4:       omp.body.continue:
1116 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1117 // CHECK4:       omp.inner.for.inc:
1118 // CHECK4-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1119 // CHECK4-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
1120 // CHECK4-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4
1121 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]]
1122 // CHECK4:       omp.inner.for.end:
1123 // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1124 // CHECK4:       omp.loop.exit:
1125 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP6]])
1126 // CHECK4-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]])
1127 // CHECK4-NEXT:    ret void
1128 //
1129 //
1130 // CHECK4-LABEL: define {{[^@]+}}@var_block_invoke
1131 // CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR4]] {
1132 // CHECK4-NEXT:  entry:
1133 // CHECK4-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8
1134 // CHECK4-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 8
1135 // CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
1136 // CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8
1137 // CHECK4-NEXT:    [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6
1138 // CHECK4-NEXT:    store i32 2, ptr [[BLOCK_CAPTURE_ADDR]], align 8
1139 // CHECK4-NEXT:    [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5
1140 // CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR1]], align 8
1141 // CHECK4-NEXT:    store i32 2, ptr [[TMP0]], align 4
1142 // CHECK4-NEXT:    [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7
1143 // CHECK4-NEXT:    store i32 4, ptr [[BLOCK_CAPTURE_ADDR2]], align 4
1144 // CHECK4-NEXT:    ret void
1145 //
1146 //
1147 // CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_for_firstprivate_codegen.cpp
1148 // CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" {
1149 // CHECK4-NEXT:  entry:
1150 // CHECK4-NEXT:    call void @__cxx_global_var_init()
1151 // CHECK4-NEXT:    call void @__cxx_global_var_init.1()
1152 // CHECK4-NEXT:    call void @__cxx_global_var_init.2()
1153 // CHECK4-NEXT:    ret void
1154 //