clang/test/OpenMP/parallel_firstprivate_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
   3 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple i386-pc-linux-gnu -emit-pch -o %t %s
   4 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
   5 // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
   6 // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4
   7
   8 // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
   9 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple i386-pc-linux-gnu -emit-pch -o %t %s
  10 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  11 // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  12 // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  13
  14 // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9
  15 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple x86_64-pc-linux-gnu -emit-pch -o %t %s
  16 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9
  17 // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11
  18 // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK12
  19
  20 // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  21 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple x86_64-pc-linux-gnu -emit-pch -o %t %s
  22 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  23 // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  24 // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  25
  26 // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17
  27
  28 // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  29 // expected-no-diagnostics
  30 #ifndef ARRAY
  31 #ifndef HEADER
  32 #define HEADER
  33
  34 enum omp_allocator_handle_t {
  35   omp_null_allocator = 0,
  36   omp_default_mem_alloc = 1,
  37   omp_large_cap_mem_alloc = 2,
  38   omp_const_mem_alloc = 3,
  39   omp_high_bw_mem_alloc = 4,
  40   omp_low_lat_mem_alloc = 5,
  41   omp_cgroup_mem_alloc = 6,
  42   omp_pteam_mem_alloc = 7,
  43   omp_thread_mem_alloc = 8,
  44   KMP_ALLOCATOR_MAX_HANDLE = __UINTPTR_MAX__
  45 };
  46
  47 struct St {
  48   int a, b;
  49   St() : a(0), b(0) {}
  50   St(const St &st) : a(st.a + st.b), b(0) {}
  51   ~St() {}
  52 };
  53
  54 volatile int g __attribute__((aligned(128))) = 1212;
  55
  56 struct SS {
  57   int a;
  58   int b : 4;
  59   int &c;
  60   int e[4];
  61   SS(int &d) : a(0), b(0), c(d) {
  62 #pragma omp parallel firstprivate(a, b, c, e)
  63 #ifdef LAMBDA
  64     [&]() {
  65       ++this->a, --b, (this)->c /= 1;
  66 #pragma omp parallel firstprivate(a, b, c)
  67       ++(this)->a, --b, this->c /= 1;
  68     }();
  69 #elif defined(BLOCKS)
  70     ^{
  71       ++a;
  72       --this->b;
  73       (this)->c /= 1;
  74 #pragma omp parallel firstprivate(a, b, c)
  75       ++(this)->a, --b, this->c /= 1;
  76     }();
  77 #else
  78     ++this->a, --b, c /= 1, e[2] = 1111;
  79 #endif
  80   }
  81 };
  82
  83 template<typename T>
  84 struct SST {
  85   T a;
  86   SST() : a(T()) {
  87 #pragma omp parallel firstprivate(a)
  88 #ifdef LAMBDA
  89     [&]() {
  90       [&]() {
  91         ++this->a;
  92 #pragma omp parallel firstprivate(a)
  93         ++(this)->a;
  94       }();
  95     }();
  96 #elif defined(BLOCKS)
  97     ^{
  98       ^{
  99         ++a;
 100 #pragma omp parallel firstprivate(a)
 101         ++(this)->a;
 102       }();
 103     }();
 104 #else
 105     ++(this)->a;
 106 #endif
 107   }
 108 };
 109
 110 template <class T>
 111 struct S {
 112   T f;
 113   S(T a) : f(a + g) {}
 114   S() : f(g) {}
 115   S(const S &s, St t = St()) : f(s.f + t.a) {}
 116   operator T() { return T(); }
 117   ~S() {}
 118 };
 119
 120
 121 template <typename T>
 122 T tmain() {
 123   S<T> test;
 124   SST<T> sst;
 125   T t_var __attribute__((aligned(128))) = T();
 126   T vec[] __attribute__((aligned(128))) = {1, 2};
 127   S<T> s_arr[] __attribute__((aligned(128))) = {1, 2};
 128   S<T> var __attribute__((aligned(128))) (3);
 129 #pragma omp parallel firstprivate(t_var, vec, s_arr, var)
 130   {
 131     vec[0] = t_var;
 132     s_arr[0] = var;
 133   }
 134 #pragma omp parallel firstprivate(t_var)
 135   {}
 136   return T();
 137 }
 138
 139 int main() {
 140   static int sivar;
 141   SS ss(sivar);
 142 #ifdef LAMBDA
 143   [&]() {
 144 #pragma omp parallel firstprivate(g, sivar)
 145   {
 146
 147
 148
 149     g = 1;
 150     sivar = 2;
 151     [&]() {
 152       g = 2;
 153       sivar = 4;
 154     }();
 155   }
 156   }();
 157   return 0;
 158 #elif defined(BLOCKS)
 159   ^{
 160 #pragma omp parallel firstprivate(g, sivar)
 161   {
 162     g = 1;
 163     sivar = 2;
 164     ^{
 165       g = 2;
 166       sivar = 4;
 167     }();
 168   }
 169   }();
 170   return 0;
 171
 172
 173 #else
 174   S<float> test;
 175   int t_var = 0;
 176   int vec[] = {1, 2};
 177   S<float> s_arr[] = {1, 2};
 178   S<float> var(3);
 179 #pragma omp parallel firstprivate(t_var, vec, s_arr, var, sivar)
 180   {
 181     vec[0] = t_var;
 182     s_arr[0] = var;
 183     sivar = 2;
 184   }
 185   const int a = 0;
 186 #pragma omp parallel allocate(omp_default_mem_alloc: t_var) firstprivate(t_var, a)
 187   { t_var = a; }
 188   return tmain<int>();
 189 #endif
 190 }
 191
 192
 193
 194
 195
 196
 197
 198
 199
 200
 201
 202
 203
 204 #endif
 205 #else
 206
 207 enum omp_allocator_handle_t {
 208   omp_null_allocator = 0,
 209   omp_default_mem_alloc = 1,
 210   omp_large_cap_mem_alloc = 2,
 211   omp_const_mem_alloc = 3,
 212   omp_high_bw_mem_alloc = 4,
 213   omp_low_lat_mem_alloc = 5,
 214   omp_cgroup_mem_alloc = 6,
 215   omp_pteam_mem_alloc = 7,
 216   omp_thread_mem_alloc = 8,
 217   KMP_ALLOCATOR_MAX_HANDLE = __UINTPTR_MAX__
 218 };
 219
 220 struct St {
 221   int a, b;
 222   St() : a(0), b(0) {}
 223   St(const St &) { }
 224   ~St() {}
 225   void St_func(St s[2], int n, long double vla1[n]) {
 226     double vla2[n][n] __attribute__((aligned(128)));
 227     a = b;
 228 #pragma omp parallel allocate(omp_thread_mem_alloc:vla2) firstprivate(s, vla1, vla2)
 229     vla1[b] = vla2[1][n - 1] = a = b;
 230   }
 231 };
 232
 233 void array_func(float a[3], St s[2], int n, long double vla1[n]) {
 234   double vla2[n][n] __attribute__((aligned(128)));
 235 #pragma omp parallel firstprivate(a, s, vla1, vla2)
 236   s[0].St_func(s, n, vla1);
 237   ;
 238 }
 239
 240 #endif
 241
 242 // CHECK1-LABEL: define {{[^@]+}}@main
 243 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
 244 // CHECK1-NEXT:  entry:
 245 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 246 // CHECK1-NEXT:    [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
 247 // CHECK1-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
 248 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 249 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 250 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
 251 // CHECK1-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S]], align 4
 252 // CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
 253 // CHECK1-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i32, align 4
 254 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
 255 // CHECK1-NEXT:    [[T_VAR_CASTED1:%.*]] = alloca i32, align 4
 256 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 257 // CHECK1-NEXT:    call void @_ZN2SSC1ERi(ptr nonnull align 4 dereferenceable(28) [[SS]], ptr nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar)
 258 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]])
 259 // CHECK1-NEXT:    store i32 0, ptr [[T_VAR]], align 4
 260 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i32 8, i1 false)
 261 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[S_ARR]], float 1.000000e+00)
 262 // CHECK1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i32 1
 263 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00)
 264 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00)
 265 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4
 266 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4
 267 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
 268 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
 269 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4
 270 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4
 271 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 5, ptr @main.omp_outlined, ptr [[VEC]], i32 [[TMP1]], ptr [[S_ARR]], ptr [[VAR]], i32 [[TMP3]])
 272 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 4
 273 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4
 274 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[T_VAR_CASTED1]], align 4
 275 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[T_VAR_CASTED1]], align 4
 276 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined.1, i32 [[TMP5]])
 277 // CHECK1-NEXT:    [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
 278 // CHECK1-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 4
 279 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]]
 280 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 281 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
 282 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 283 // CHECK1:       arraydestroy.body:
 284 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 285 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
 286 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
 287 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
 288 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
 289 // CHECK1:       arraydestroy.done2:
 290 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
 291 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4
 292 // CHECK1-NEXT:    ret i32 [[TMP7]]
 293 //
 294 //
 295 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC1ERi
 296 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(28) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
 297 // CHECK1-NEXT:  entry:
 298 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 299 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
 300 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 301 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
 302 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 303 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4
 304 // CHECK1-NEXT:    call void @_ZN2SSC2ERi(ptr nonnull align 4 dereferenceable(28) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]])
 305 // CHECK1-NEXT:    ret void
 306 //
 307 //
 308 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
 309 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 310 // CHECK1-NEXT:  entry:
 311 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 312 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 313 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 314 // CHECK1-NEXT:    call void @_ZN1SIfEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]])
 315 // CHECK1-NEXT:    ret void
 316 //
 317 //
 318 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
 319 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 320 // CHECK1-NEXT:  entry:
 321 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 322 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 323 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 324 // CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 325 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 326 // CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 327 // CHECK1-NEXT:    call void @_ZN1SIfEC2Ef(ptr nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
 328 // CHECK1-NEXT:    ret void
 329 //
 330 //
 331 // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined
 332 // CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] {
 333 // CHECK1-NEXT:  entry:
 334 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
 335 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
 336 // CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4
 337 // CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
 338 // CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
 339 // CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4
 340 // CHECK1-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i32, align 4
 341 // CHECK1-NEXT:    [[VEC1:%.*]] = alloca [2 x i32], align 4
 342 // CHECK1-NEXT:    [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
 343 // CHECK1-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
 344 // CHECK1-NEXT:    [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
 345 // CHECK1-NEXT:    [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
 346 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
 347 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
 348 // CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
 349 // CHECK1-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
 350 // CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
 351 // CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
 352 // CHECK1-NEXT:    store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4
 353 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
 354 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
 355 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
 356 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false)
 357 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0
 358 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
 359 // CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]
 360 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
 361 // CHECK1:       omp.arraycpy.body:
 362 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
 363 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
 364 // CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]])
 365 // CHECK1-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]])
 366 // CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
 367 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
 368 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
 369 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]
 370 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
 371 // CHECK1:       omp.arraycpy.done3:
 372 // CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
 373 // CHECK1-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]])
 374 // CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]]
 375 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
 376 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 0
 377 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4
 378 // CHECK1-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0
 379 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR4]], i32 4, i1 false)
 380 // CHECK1-NEXT:    store i32 2, ptr [[SIVAR_ADDR]], align 4
 381 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]]
 382 // CHECK1-NEXT:    [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0
 383 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i32 2
 384 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 385 // CHECK1:       arraydestroy.body:
 386 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 387 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
 388 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
 389 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
 390 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
 391 // CHECK1:       arraydestroy.done8:
 392 // CHECK1-NEXT:    ret void
 393 //
 394 //
 395 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev
 396 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 397 // CHECK1-NEXT:  entry:
 398 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 399 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 400 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 401 // CHECK1-NEXT:    call void @_ZN2StC2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]])
 402 // CHECK1-NEXT:    ret void
 403 //
 404 //
 405 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
 406 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 407 // CHECK1-NEXT:  entry:
 408 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 409 // CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
 410 // CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4
 411 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 412 // CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
 413 // CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4
 414 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 415 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
 416 // CHECK1-NEXT:    call void @_ZN1SIfEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]])
 417 // CHECK1-NEXT:    ret void
 418 //
 419 //
 420 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev
 421 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 422 // CHECK1-NEXT:  entry:
 423 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 424 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 425 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 426 // CHECK1-NEXT:    call void @_ZN2StD2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]]
 427 // CHECK1-NEXT:    ret void
 428 //
 429 //
 430 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
 431 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 432 // CHECK1-NEXT:  entry:
 433 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 434 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 435 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 436 // CHECK1-NEXT:    call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
 437 // CHECK1-NEXT:    ret void
 438 //
 439 //
 440 // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.1
 441 // CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[T_VAR:%.*]]) #[[ATTR3]] {
 442 // CHECK1-NEXT:  entry:
 443 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
 444 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
 445 // CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
 446 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
 447 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
 448 // CHECK1-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
 449 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
 450 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 451 // CHECK1-NEXT:    [[DOTT_VAR__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP1]], i32 4, ptr inttoptr (i32 1 to ptr))
 452 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
 453 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTT_VAR__VOID_ADDR]], align 4
 454 // CHECK1-NEXT:    store i32 0, ptr [[DOTT_VAR__VOID_ADDR]], align 4
 455 // CHECK1-NEXT:    call void @__kmpc_free(i32 [[TMP1]], ptr [[DOTT_VAR__VOID_ADDR]], ptr inttoptr (i32 1 to ptr))
 456 // CHECK1-NEXT:    ret void
 457 //
 458 //
 459 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
 460 // CHECK1-SAME: () #[[ATTR1]] comdat {
 461 // CHECK1-NEXT:  entry:
 462 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 463 // CHECK1-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
 464 // CHECK1-NEXT:    [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4
 465 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 128
 466 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 128
 467 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128
 468 // CHECK1-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128
 469 // CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
 470 // CHECK1-NEXT:    [[T_VAR_CASTED1:%.*]] = alloca i32, align 4
 471 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]])
 472 // CHECK1-NEXT:    call void @_ZN3SSTIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[SST]])
 473 // CHECK1-NEXT:    store i32 0, ptr [[T_VAR]], align 128
 474 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[VEC]], ptr align 128 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)
 475 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[S_ARR]], i32 1)
 476 // CHECK1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1
 477 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
 478 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[VAR]], i32 3)
 479 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 128
 480 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4
 481 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
 482 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[VEC]], i32 [[TMP1]], ptr [[S_ARR]], ptr [[VAR]])
 483 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[T_VAR]], align 128
 484 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[T_VAR_CASTED1]], align 4
 485 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[T_VAR_CASTED1]], align 4
 486 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_Z5tmainIiET_v.omp_outlined.2, i32 [[TMP3]])
 487 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 488 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
 489 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 490 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
 491 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 492 // CHECK1:       arraydestroy.body:
 493 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 494 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
 495 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
 496 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
 497 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
 498 // CHECK1:       arraydestroy.done2:
 499 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
 500 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[RETVAL]], align 4
 501 // CHECK1-NEXT:    ret i32 [[TMP5]]
 502 //
 503 //
 504 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC2ERi
 505 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(28) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 506 // CHECK1-NEXT:  entry:
 507 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 508 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
 509 // CHECK1-NEXT:    [[A2:%.*]] = alloca ptr, align 4
 510 // CHECK1-NEXT:    [[B4:%.*]] = alloca i32, align 4
 511 // CHECK1-NEXT:    [[C7:%.*]] = alloca ptr, align 4
 512 // CHECK1-NEXT:    [[E:%.*]] = alloca ptr, align 4
 513 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
 514 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
 515 // CHECK1-NEXT:    [[C_CASTED:%.*]] = alloca i32, align 4
 516 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 517 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
 518 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 519 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0
 520 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 4
 521 // CHECK1-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1
 522 // CHECK1-NEXT:    [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 4
 523 // CHECK1-NEXT:    [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16
 524 // CHECK1-NEXT:    [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0
 525 // CHECK1-NEXT:    store i8 [[BF_SET]], ptr [[B]], align 4
 526 // CHECK1-NEXT:    [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2
 527 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4
 528 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[C]], align 4
 529 // CHECK1-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0
 530 // CHECK1-NEXT:    store ptr [[A3]], ptr [[A2]], align 4
 531 // CHECK1-NEXT:    [[B5:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1
 532 // CHECK1-NEXT:    [[BF_LOAD6:%.*]] = load i8, ptr [[B5]], align 4
 533 // CHECK1-NEXT:    [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4
 534 // CHECK1-NEXT:    [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4
 535 // CHECK1-NEXT:    [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32
 536 // CHECK1-NEXT:    store i32 [[BF_CAST]], ptr [[B4]], align 4
 537 // CHECK1-NEXT:    [[C8:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2
 538 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[C8]], align 4
 539 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[C7]], align 4
 540 // CHECK1-NEXT:    [[E9:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3
 541 // CHECK1-NEXT:    store ptr [[E9]], ptr [[E]], align 4
 542 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[A2]], align 4
 543 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
 544 // CHECK1-NEXT:    store i32 [[TMP3]], ptr [[A_CASTED]], align 4
 545 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4
 546 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B4]], align 4
 547 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[B_CASTED]], align 4
 548 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4
 549 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[C7]], align 4
 550 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
 551 // CHECK1-NEXT:    store i32 [[TMP8]], ptr [[C_CASTED]], align 4
 552 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[C_CASTED]], align 4
 553 // CHECK1-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[E]], align 4
 554 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP9]], ptr [[TMP10]])
 555 // CHECK1-NEXT:    ret void
 556 //
 557 //
 558 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined
 559 // CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], ptr nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3]] {
 560 // CHECK1-NEXT:  entry:
 561 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
 562 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
 563 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 564 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 565 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
 566 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 4
 567 // CHECK1-NEXT:    [[E_ADDR:%.*]] = alloca ptr, align 4
 568 // CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
 569 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
 570 // CHECK1-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 4
 571 // CHECK1-NEXT:    [[E3:%.*]] = alloca [4 x i32], align 4
 572 // CHECK1-NEXT:    [[_TMP4:%.*]] = alloca ptr, align 4
 573 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
 574 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
 575 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 576 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
 577 // CHECK1-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
 578 // CHECK1-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 4
 579 // CHECK1-NEXT:    store ptr [[E]], ptr [[E_ADDR]], align 4
 580 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 581 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[E_ADDR]], align 4
 582 // CHECK1-NEXT:    store ptr [[A_ADDR]], ptr [[TMP]], align 4
 583 // CHECK1-NEXT:    store ptr [[C_ADDR]], ptr [[_TMP1]], align 4
 584 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[_TMP2]], align 4
 585 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[_TMP2]], align 4
 586 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[E3]], ptr align 4 [[TMP2]], i32 16, i1 false)
 587 // CHECK1-NEXT:    store ptr [[E3]], ptr [[_TMP4]], align 4
 588 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4
 589 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
 590 // CHECK1-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 1
 591 // CHECK1-NEXT:    store i32 [[INC]], ptr [[TMP3]], align 4
 592 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 4
 593 // CHECK1-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP5]], -1
 594 // CHECK1-NEXT:    store i32 [[DEC]], ptr [[B_ADDR]], align 4
 595 // CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 4
 596 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
 597 // CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP7]], 1
 598 // CHECK1-NEXT:    store i32 [[DIV]], ptr [[TMP6]], align 4
 599 // CHECK1-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 4
 600 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], ptr [[TMP8]], i32 0, i32 2
 601 // CHECK1-NEXT:    store i32 1111, ptr [[ARRAYIDX]], align 4
 602 // CHECK1-NEXT:    ret void
 603 //
 604 //
 605 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
 606 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 607 // CHECK1-NEXT:  entry:
 608 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 609 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 610 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 611 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 612 // CHECK1-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 128
 613 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
 614 // CHECK1-NEXT:    store float [[CONV]], ptr [[F]], align 4
 615 // CHECK1-NEXT:    ret void
 616 //
 617 //
 618 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
 619 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 620 // CHECK1-NEXT:  entry:
 621 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 622 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 623 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 624 // CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 625 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 626 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 627 // CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 628 // CHECK1-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 128
 629 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
 630 // CHECK1-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
 631 // CHECK1-NEXT:    store float [[ADD]], ptr [[F]], align 4
 632 // CHECK1-NEXT:    ret void
 633 //
 634 //
 635 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev
 636 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 637 // CHECK1-NEXT:  entry:
 638 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 639 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 640 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 641 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
 642 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 4
 643 // CHECK1-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
 644 // CHECK1-NEXT:    store i32 0, ptr [[B]], align 4
 645 // CHECK1-NEXT:    ret void
 646 //
 647 //
 648 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
 649 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 650 // CHECK1-NEXT:  entry:
 651 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 652 // CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
 653 // CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4
 654 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 655 // CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
 656 // CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4
 657 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 658 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 659 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
 660 // CHECK1-NEXT:    [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0
 661 // CHECK1-NEXT:    [[TMP1:%.*]] = load float, ptr [[F2]], align 4
 662 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
 663 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 4
 664 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
 665 // CHECK1-NEXT:    [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
 666 // CHECK1-NEXT:    store float [[ADD]], ptr [[F]], align 4
 667 // CHECK1-NEXT:    ret void
 668 //
 669 //
 670 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev
 671 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 672 // CHECK1-NEXT:  entry:
 673 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 674 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 675 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 676 // CHECK1-NEXT:    ret void
 677 //
 678 //
 679 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
 680 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 681 // CHECK1-NEXT:  entry:
 682 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 683 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 684 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 685 // CHECK1-NEXT:    ret void
 686 //
 687 //
 688 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
 689 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 690 // CHECK1-NEXT:  entry:
 691 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 692 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 693 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 694 // CHECK1-NEXT:    call void @_ZN1SIiEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]])
 695 // CHECK1-NEXT:    ret void
 696 //
 697 //
 698 // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev
 699 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 700 // CHECK1-NEXT:  entry:
 701 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 702 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 703 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 704 // CHECK1-NEXT:    call void @_ZN3SSTIiEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]])
 705 // CHECK1-NEXT:    ret void
 706 //
 707 //
 708 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
 709 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 710 // CHECK1-NEXT:  entry:
 711 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 712 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 713 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 714 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
 715 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 716 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 717 // CHECK1-NEXT:    call void @_ZN1SIiEC2Ei(ptr nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
 718 // CHECK1-NEXT:    ret void
 719 //
 720 //
 721 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined
 722 // CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
 723 // CHECK1-NEXT:  entry:
 724 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
 725 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
 726 // CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4
 727 // CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
 728 // CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
 729 // CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4
 730 // CHECK1-NEXT:    [[VEC1:%.*]] = alloca [2 x i32], align 128
 731 // CHECK1-NEXT:    [[S_ARR2:%.*]] = alloca [2 x %struct.S.0], align 128
 732 // CHECK1-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
 733 // CHECK1-NEXT:    [[VAR4:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128
 734 // CHECK1-NEXT:    [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
 735 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
 736 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
 737 // CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
 738 // CHECK1-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
 739 // CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
 740 // CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
 741 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
 742 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
 743 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
 744 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[VEC1]], ptr align 128 [[TMP0]], i32 8, i1 false)
 745 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0
 746 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
 747 // CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]
 748 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
 749 // CHECK1:       omp.arraycpy.body:
 750 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
 751 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
 752 // CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]])
 753 // CHECK1-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]])
 754 // CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
 755 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
 756 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
 757 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]
 758 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
 759 // CHECK1:       omp.arraycpy.done3:
 760 // CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
 761 // CHECK1-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]])
 762 // CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]]
 763 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
 764 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 0
 765 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[ARRAYIDX]], align 128
 766 // CHECK1-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0
 767 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[ARRAYIDX6]], ptr align 128 [[VAR4]], i32 4, i1 false)
 768 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]]
 769 // CHECK1-NEXT:    [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0
 770 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i32 2
 771 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 772 // CHECK1:       arraydestroy.body:
 773 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 774 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
 775 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
 776 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
 777 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
 778 // CHECK1:       arraydestroy.done8:
 779 // CHECK1-NEXT:    ret void
 780 //
 781 //
 782 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
 783 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 784 // CHECK1-NEXT:  entry:
 785 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 786 // CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
 787 // CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4
 788 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 789 // CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
 790 // CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4
 791 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 792 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
 793 // CHECK1-NEXT:    call void @_ZN1SIiEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]])
 794 // CHECK1-NEXT:    ret void
 795 //
 796 //
 797 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
 798 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 799 // CHECK1-NEXT:  entry:
 800 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 801 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 802 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 803 // CHECK1-NEXT:    call void @_ZN1SIiED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
 804 // CHECK1-NEXT:    ret void
 805 //
 806 //
 807 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined.2
 808 // CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[T_VAR:%.*]]) #[[ATTR3]] {
 809 // CHECK1-NEXT:  entry:
 810 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
 811 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
 812 // CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
 813 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
 814 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
 815 // CHECK1-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
 816 // CHECK1-NEXT:    ret void
 817 //
 818 //
 819 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
 820 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 821 // CHECK1-NEXT:  entry:
 822 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 823 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 824 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 825 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
 826 // CHECK1-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 128
 827 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
 828 // CHECK1-NEXT:    ret void
 829 //
 830 //
 831 // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev
 832 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 833 // CHECK1-NEXT:  entry:
 834 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 835 // CHECK1-NEXT:    [[A2:%.*]] = alloca ptr, align 4
 836 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
 837 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 838 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 839 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SST:%.*]], ptr [[THIS1]], i32 0, i32 0
 840 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 4
 841 // CHECK1-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SST]], ptr [[THIS1]], i32 0, i32 0
 842 // CHECK1-NEXT:    store ptr [[A3]], ptr [[A2]], align 4
 843 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A2]], align 4
 844 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 845 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
 846 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
 847 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @_ZN3SSTIiEC2Ev.omp_outlined, ptr [[THIS1]], i32 [[TMP2]])
 848 // CHECK1-NEXT:    ret void
 849 //
 850 //
 851 // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev.omp_outlined
 852 // CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i32 [[A:%.*]]) #[[ATTR3]] {
 853 // CHECK1-NEXT:  entry:
 854 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
 855 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
 856 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 857 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 858 // CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
 859 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
 860 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
 861 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 862 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
 863 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 864 // CHECK1-NEXT:    store ptr [[A_ADDR]], ptr [[TMP]], align 4
 865 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 4
 866 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
 867 // CHECK1-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP2]], 1
 868 // CHECK1-NEXT:    store i32 [[INC]], ptr [[TMP1]], align 4
 869 // CHECK1-NEXT:    ret void
 870 //
 871 //
 872 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
 873 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 874 // CHECK1-NEXT:  entry:
 875 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 876 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 877 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 878 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
 879 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 880 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
 881 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 882 // CHECK1-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 128
 883 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
 884 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
 885 // CHECK1-NEXT:    ret void
 886 //
 887 //
 888 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
 889 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 890 // CHECK1-NEXT:  entry:
 891 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 892 // CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
 893 // CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4
 894 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 895 // CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
 896 // CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4
 897 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 898 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
 899 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
 900 // CHECK1-NEXT:    [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0
 901 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[F2]], align 4
 902 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
 903 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 4
 904 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
 905 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
 906 // CHECK1-NEXT:    ret void
 907 //
 908 //
 909 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
 910 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 911 // CHECK1-NEXT:  entry:
 912 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 913 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 914 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 915 // CHECK1-NEXT:    ret void
 916 //
 917 //
 918 // CHECK3-LABEL: define {{[^@]+}}@main
 919 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
 920 // CHECK3-NEXT:  entry:
 921 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 922 // CHECK3-NEXT:    [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
 923 // CHECK3-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4
 924 // CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 925 // CHECK3-NEXT:    call void @_ZN2SSC1ERi(ptr nonnull align 4 dereferenceable(28) [[SS]], ptr nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar)
 926 // CHECK3-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0
 927 // CHECK3-NEXT:    store ptr @_ZZ4mainE5sivar, ptr [[TMP0]], align 4
 928 // CHECK3-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr nonnull align 4 dereferenceable(4) [[REF_TMP]])
 929 // CHECK3-NEXT:    ret i32 0
 930 //
 931 //
 932 // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC1ERi
 933 // CHECK3-SAME: (ptr nonnull align 4 dereferenceable(28) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
 934 // CHECK3-NEXT:  entry:
 935 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 936 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
 937 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 938 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
 939 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 940 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4
 941 // CHECK3-NEXT:    call void @_ZN2SSC2ERi(ptr nonnull align 4 dereferenceable(28) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]])
 942 // CHECK3-NEXT:    ret void
 943 //
 944 //
 945 // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC2ERi
 946 // CHECK3-SAME: (ptr nonnull align 4 dereferenceable(28) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 947 // CHECK3-NEXT:  entry:
 948 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 949 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
 950 // CHECK3-NEXT:    [[A2:%.*]] = alloca ptr, align 4
 951 // CHECK3-NEXT:    [[B4:%.*]] = alloca i32, align 4
 952 // CHECK3-NEXT:    [[C7:%.*]] = alloca ptr, align 4
 953 // CHECK3-NEXT:    [[E:%.*]] = alloca ptr, align 4
 954 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
 955 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
 956 // CHECK3-NEXT:    [[C_CASTED:%.*]] = alloca i32, align 4
 957 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 958 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
 959 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 960 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0
 961 // CHECK3-NEXT:    store i32 0, ptr [[A]], align 4
 962 // CHECK3-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1
 963 // CHECK3-NEXT:    [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 4
 964 // CHECK3-NEXT:    [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16
 965 // CHECK3-NEXT:    [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0
 966 // CHECK3-NEXT:    store i8 [[BF_SET]], ptr [[B]], align 4
 967 // CHECK3-NEXT:    [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2
 968 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4
 969 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[C]], align 4
 970 // CHECK3-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0
 971 // CHECK3-NEXT:    store ptr [[A3]], ptr [[A2]], align 4
 972 // CHECK3-NEXT:    [[B5:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1
 973 // CHECK3-NEXT:    [[BF_LOAD6:%.*]] = load i8, ptr [[B5]], align 4
 974 // CHECK3-NEXT:    [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4
 975 // CHECK3-NEXT:    [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4
 976 // CHECK3-NEXT:    [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32
 977 // CHECK3-NEXT:    store i32 [[BF_CAST]], ptr [[B4]], align 4
 978 // CHECK3-NEXT:    [[C8:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2
 979 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[C8]], align 4
 980 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[C7]], align 4
 981 // CHECK3-NEXT:    [[E9:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3
 982 // CHECK3-NEXT:    store ptr [[E9]], ptr [[E]], align 4
 983 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[A2]], align 4
 984 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
 985 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[A_CASTED]], align 4
 986 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4
 987 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B4]], align 4
 988 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[B_CASTED]], align 4
 989 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4
 990 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[C7]], align 4
 991 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
 992 // CHECK3-NEXT:    store i32 [[TMP8]], ptr [[C_CASTED]], align 4
 993 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[C_CASTED]], align 4
 994 // CHECK3-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[E]], align 4
 995 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 5, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP9]], ptr [[TMP10]])
 996 // CHECK3-NEXT:    ret void
 997 //
 998 //
 999 // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined
1000 // CHECK3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], ptr nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR2:[0-9]+]] {
1001 // CHECK3-NEXT:  entry:
1002 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1003 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1004 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1005 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1006 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
1007 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 4
1008 // CHECK3-NEXT:    [[E_ADDR:%.*]] = alloca ptr, align 4
1009 // CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
1010 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
1011 // CHECK3-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 4
1012 // CHECK3-NEXT:    [[E3:%.*]] = alloca [4 x i32], align 4
1013 // CHECK3-NEXT:    [[_TMP4:%.*]] = alloca ptr, align 4
1014 // CHECK3-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4
1015 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1016 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1017 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1018 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1019 // CHECK3-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
1020 // CHECK3-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 4
1021 // CHECK3-NEXT:    store ptr [[E]], ptr [[E_ADDR]], align 4
1022 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1023 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[E_ADDR]], align 4
1024 // CHECK3-NEXT:    store ptr [[A_ADDR]], ptr [[TMP]], align 4
1025 // CHECK3-NEXT:    store ptr [[C_ADDR]], ptr [[_TMP1]], align 4
1026 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[_TMP2]], align 4
1027 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[_TMP2]], align 4
1028 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[E3]], ptr align 4 [[TMP2]], i32 16, i1 false)
1029 // CHECK3-NEXT:    store ptr [[E3]], ptr [[_TMP4]], align 4
1030 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
1031 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP3]], align 4
1032 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
1033 // CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4
1034 // CHECK3-NEXT:    store ptr [[TMP5]], ptr [[TMP4]], align 4
1035 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2
1036 // CHECK3-NEXT:    store ptr [[B_ADDR]], ptr [[TMP6]], align 4
1037 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3
1038 // CHECK3-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 4
1039 // CHECK3-NEXT:    store ptr [[TMP8]], ptr [[TMP7]], align 4
1040 // CHECK3-NEXT:    call void @_ZZN2SSC1ERiENKUlvE_clEv(ptr nonnull align 4 dereferenceable(16) [[REF_TMP]])
1041 // CHECK3-NEXT:    ret void
1042 //
1043 //
1044 // CHECK3-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv
1045 // CHECK3-SAME: (ptr nonnull align 4 dereferenceable(16) [[THIS:%.*]]) #[[ATTR1]] align 2 {
1046 // CHECK3-NEXT:  entry:
1047 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1048 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
1049 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
1050 // CHECK3-NEXT:    [[C_CASTED:%.*]] = alloca i32, align 4
1051 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1052 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1053 // CHECK3-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1054 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 4
1055 // CHECK3-NEXT:    [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1
1056 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
1057 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
1058 // CHECK3-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 1
1059 // CHECK3-NEXT:    store i32 [[INC]], ptr [[TMP3]], align 4
1060 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 2
1061 // CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
1062 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
1063 // CHECK3-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP7]], -1
1064 // CHECK3-NEXT:    store i32 [[DEC]], ptr [[TMP6]], align 4
1065 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 3
1066 // CHECK3-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 4
1067 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
1068 // CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP10]], 1
1069 // CHECK3-NEXT:    store i32 [[DIV]], ptr [[TMP9]], align 4
1070 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1
1071 // CHECK3-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 4
1072 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4
1073 // CHECK3-NEXT:    store i32 [[TMP13]], ptr [[A_CASTED]], align 4
1074 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[A_CASTED]], align 4
1075 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 2
1076 // CHECK3-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 4
1077 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4
1078 // CHECK3-NEXT:    store i32 [[TMP17]], ptr [[B_CASTED]], align 4
1079 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[B_CASTED]], align 4
1080 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 3
1081 // CHECK3-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 4
1082 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
1083 // CHECK3-NEXT:    store i32 [[TMP21]], ptr [[C_CASTED]], align 4
1084 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32, ptr [[C_CASTED]], align 4
1085 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined, ptr [[TMP1]], i32 [[TMP14]], i32 [[TMP18]], i32 [[TMP22]])
1086 // CHECK3-NEXT:    ret void
1087 //
1088 //
1089 // CHECK3-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined
1090 // CHECK3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) #[[ATTR2]] {
1091 // CHECK3-NEXT:  entry:
1092 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1093 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1094 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1095 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1096 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
1097 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 4
1098 // CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
1099 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
1100 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1101 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1102 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1103 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1104 // CHECK3-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
1105 // CHECK3-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 4
1106 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1107 // CHECK3-NEXT:    store ptr [[A_ADDR]], ptr [[TMP]], align 4
1108 // CHECK3-NEXT:    store ptr [[C_ADDR]], ptr [[_TMP1]], align 4
1109 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 4
1110 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
1111 // CHECK3-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP2]], 1
1112 // CHECK3-NEXT:    store i32 [[INC]], ptr [[TMP1]], align 4
1113 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[B_ADDR]], align 4
1114 // CHECK3-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP3]], -1
1115 // CHECK3-NEXT:    store i32 [[DEC]], ptr [[B_ADDR]], align 4
1116 // CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 4
1117 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
1118 // CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP5]], 1
1119 // CHECK3-NEXT:    store i32 [[DIV]], ptr [[TMP4]], align 4
1120 // CHECK3-NEXT:    ret void
1121 //
1122 //
1123 // CHECK4-LABEL: define {{[^@]+}}@main
1124 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] {
1125 // CHECK4-NEXT:  entry:
1126 // CHECK4-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1127 // CHECK4-NEXT:    [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
1128 // CHECK4-NEXT:    [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32 }>, align 4
1129 // CHECK4-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1130 // CHECK4-NEXT:    call void @_ZN2SSC1ERi(ptr nonnull align 4 dereferenceable(28) [[SS]], ptr nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar)
1131 // CHECK4-NEXT:    [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 0
1132 // CHECK4-NEXT:    store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 4
1133 // CHECK4-NEXT:    [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 1
1134 // CHECK4-NEXT:    store i32 1073741824, ptr [[BLOCK_FLAGS]], align 4
1135 // CHECK4-NEXT:    [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 2
1136 // CHECK4-NEXT:    store i32 0, ptr [[BLOCK_RESERVED]], align 4
1137 // CHECK4-NEXT:    [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 3
1138 // CHECK4-NEXT:    store ptr @__main_block_invoke, ptr [[BLOCK_INVOKE]], align 4
1139 // CHECK4-NEXT:    [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 4
1140 // CHECK4-NEXT:    store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR]], align 4
1141 // CHECK4-NEXT:    [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 5
1142 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
1143 // CHECK4-NEXT:    store i32 [[TMP0]], ptr [[BLOCK_CAPTURED]], align 4
1144 // CHECK4-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3
1145 // CHECK4-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
1146 // CHECK4-NEXT:    call void [[TMP2]](ptr [[BLOCK]])
1147 // CHECK4-NEXT:    ret i32 0
1148 //
1149 //
1150 // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC1ERi
1151 // CHECK4-SAME: (ptr nonnull align 4 dereferenceable(28) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1152 // CHECK4-NEXT:  entry:
1153 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1154 // CHECK4-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
1155 // CHECK4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1156 // CHECK4-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
1157 // CHECK4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1158 // CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4
1159 // CHECK4-NEXT:    call void @_ZN2SSC2ERi(ptr nonnull align 4 dereferenceable(28) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]])
1160 // CHECK4-NEXT:    ret void
1161 //
1162 //
1163 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke
1164 // CHECK4-SAME: (ptr [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {
1165 // CHECK4-NEXT:  entry:
1166 // CHECK4-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 4
1167 // CHECK4-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 4
1168 // CHECK4-NEXT:    [[G_CASTED:%.*]] = alloca i32, align 4
1169 // CHECK4-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i32, align 4
1170 // CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 4
1171 // CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 4
1172 // CHECK4-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 128
1173 // CHECK4-NEXT:    store i32 [[TMP0]], ptr [[G_CASTED]], align 4
1174 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, ptr [[G_CASTED]], align 4
1175 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
1176 // CHECK4-NEXT:    store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4
1177 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4
1178 // CHECK4-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @__main_block_invoke.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])
1179 // CHECK4-NEXT:    ret void
1180 //
1181 //
1182 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined
1183 // CHECK4-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] {
1184 // CHECK4-NEXT:  entry:
1185 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1186 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1187 // CHECK4-NEXT:    [[G_ADDR:%.*]] = alloca i32, align 4
1188 // CHECK4-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i32, align 4
1189 // CHECK4-NEXT:    [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, align 128
1190 // CHECK4-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1191 // CHECK4-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1192 // CHECK4-NEXT:    store i32 [[G]], ptr [[G_ADDR]], align 4
1193 // CHECK4-NEXT:    store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4
1194 // CHECK4-NEXT:    store i32 1, ptr [[G_ADDR]], align 4
1195 // CHECK4-NEXT:    store i32 2, ptr [[SIVAR_ADDR]], align 4
1196 // CHECK4-NEXT:    [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 0
1197 // CHECK4-NEXT:    store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 128
1198 // CHECK4-NEXT:    [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 1
1199 // CHECK4-NEXT:    store i32 1073741824, ptr [[BLOCK_FLAGS]], align 4
1200 // CHECK4-NEXT:    [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 2
1201 // CHECK4-NEXT:    store i32 0, ptr [[BLOCK_RESERVED]], align 8
1202 // CHECK4-NEXT:    [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 3
1203 // CHECK4-NEXT:    store ptr @g_block_invoke, ptr [[BLOCK_INVOKE]], align 4
1204 // CHECK4-NEXT:    [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 4
1205 // CHECK4-NEXT:    store ptr @__block_descriptor_tmp, ptr [[BLOCK_DESCRIPTOR]], align 16
1206 // CHECK4-NEXT:    [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 7
1207 // CHECK4-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr [[G_ADDR]], align 4
1208 // CHECK4-NEXT:    store volatile i32 [[TMP0]], ptr [[BLOCK_CAPTURED]], align 128
1209 // CHECK4-NEXT:    [[BLOCK_CAPTURED1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 5
1210 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4
1211 // CHECK4-NEXT:    store i32 [[TMP1]], ptr [[BLOCK_CAPTURED1]], align 4
1212 // CHECK4-NEXT:    [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3
1213 // CHECK4-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
1214 // CHECK4-NEXT:    call void [[TMP3]](ptr [[BLOCK]])
1215 // CHECK4-NEXT:    ret void
1216 //
1217 //
1218 // CHECK4-LABEL: define {{[^@]+}}@g_block_invoke
1219 // CHECK4-SAME: (ptr [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {
1220 // CHECK4-NEXT:  entry:
1221 // CHECK4-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 4
1222 // CHECK4-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 4
1223 // CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 4
1224 // CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 4
1225 // CHECK4-NEXT:    [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7
1226 // CHECK4-NEXT:    store i32 2, ptr [[BLOCK_CAPTURE_ADDR]], align 128
1227 // CHECK4-NEXT:    [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5
1228 // CHECK4-NEXT:    store i32 4, ptr [[BLOCK_CAPTURE_ADDR1]], align 4
1229 // CHECK4-NEXT:    ret void
1230 //
1231 //
1232 // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC2ERi
1233 // CHECK4-SAME: (ptr nonnull align 4 dereferenceable(28) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1234 // CHECK4-NEXT:  entry:
1235 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1236 // CHECK4-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
1237 // CHECK4-NEXT:    [[A2:%.*]] = alloca ptr, align 4
1238 // CHECK4-NEXT:    [[B4:%.*]] = alloca i32, align 4
1239 // CHECK4-NEXT:    [[C7:%.*]] = alloca ptr, align 4
1240 // CHECK4-NEXT:    [[E:%.*]] = alloca ptr, align 4
1241 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
1242 // CHECK4-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
1243 // CHECK4-NEXT:    [[C_CASTED:%.*]] = alloca i32, align 4
1244 // CHECK4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1245 // CHECK4-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
1246 // CHECK4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1247 // CHECK4-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0
1248 // CHECK4-NEXT:    store i32 0, ptr [[A]], align 4
1249 // CHECK4-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1
1250 // CHECK4-NEXT:    [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 4
1251 // CHECK4-NEXT:    [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16
1252 // CHECK4-NEXT:    [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0
1253 // CHECK4-NEXT:    store i8 [[BF_SET]], ptr [[B]], align 4
1254 // CHECK4-NEXT:    [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2
1255 // CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4
1256 // CHECK4-NEXT:    store ptr [[TMP0]], ptr [[C]], align 4
1257 // CHECK4-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0
1258 // CHECK4-NEXT:    store ptr [[A3]], ptr [[A2]], align 4
1259 // CHECK4-NEXT:    [[B5:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1
1260 // CHECK4-NEXT:    [[BF_LOAD6:%.*]] = load i8, ptr [[B5]], align 4
1261 // CHECK4-NEXT:    [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4
1262 // CHECK4-NEXT:    [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4
1263 // CHECK4-NEXT:    [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32
1264 // CHECK4-NEXT:    store i32 [[BF_CAST]], ptr [[B4]], align 4
1265 // CHECK4-NEXT:    [[C8:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2
1266 // CHECK4-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[C8]], align 4
1267 // CHECK4-NEXT:    store ptr [[TMP1]], ptr [[C7]], align 4
1268 // CHECK4-NEXT:    [[E9:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3
1269 // CHECK4-NEXT:    store ptr [[E9]], ptr [[E]], align 4
1270 // CHECK4-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[A2]], align 4
1271 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
1272 // CHECK4-NEXT:    store i32 [[TMP3]], ptr [[A_CASTED]], align 4
1273 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4
1274 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B4]], align 4
1275 // CHECK4-NEXT:    store i32 [[TMP5]], ptr [[B_CASTED]], align 4
1276 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4
1277 // CHECK4-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[C7]], align 4
1278 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
1279 // CHECK4-NEXT:    store i32 [[TMP8]], ptr [[C_CASTED]], align 4
1280 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, ptr [[C_CASTED]], align 4
1281 // CHECK4-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[E]], align 4
1282 // CHECK4-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP9]], ptr [[TMP10]])
1283 // CHECK4-NEXT:    ret void
1284 //
1285 //
1286 // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined
1287 // CHECK4-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], ptr nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3]] {
1288 // CHECK4-NEXT:  entry:
1289 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1290 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1291 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1292 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1293 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
1294 // CHECK4-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 4
1295 // CHECK4-NEXT:    [[E_ADDR:%.*]] = alloca ptr, align 4
1296 // CHECK4-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
1297 // CHECK4-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
1298 // CHECK4-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 4
1299 // CHECK4-NEXT:    [[E3:%.*]] = alloca [4 x i32], align 4
1300 // CHECK4-NEXT:    [[_TMP4:%.*]] = alloca ptr, align 4
1301 // CHECK4-NEXT:    [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, align 4
1302 // CHECK4-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1303 // CHECK4-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1304 // CHECK4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1305 // CHECK4-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1306 // CHECK4-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
1307 // CHECK4-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 4
1308 // CHECK4-NEXT:    store ptr [[E]], ptr [[E_ADDR]], align 4
1309 // CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1310 // CHECK4-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[E_ADDR]], align 4
1311 // CHECK4-NEXT:    store ptr [[A_ADDR]], ptr [[TMP]], align 4
1312 // CHECK4-NEXT:    store ptr [[C_ADDR]], ptr [[_TMP1]], align 4
1313 // CHECK4-NEXT:    store ptr [[TMP1]], ptr [[_TMP2]], align 4
1314 // CHECK4-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[_TMP2]], align 4
1315 // CHECK4-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[E3]], ptr align 4 [[TMP2]], i32 16, i1 false)
1316 // CHECK4-NEXT:    store ptr [[E3]], ptr [[_TMP4]], align 4
1317 // CHECK4-NEXT:    [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 0
1318 // CHECK4-NEXT:    store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 4
1319 // CHECK4-NEXT:    [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 1
1320 // CHECK4-NEXT:    store i32 1073741824, ptr [[BLOCK_FLAGS]], align 4
1321 // CHECK4-NEXT:    [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 2
1322 // CHECK4-NEXT:    store i32 0, ptr [[BLOCK_RESERVED]], align 4
1323 // CHECK4-NEXT:    [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 3
1324 // CHECK4-NEXT:    store ptr @g_block_invoke_2, ptr [[BLOCK_INVOKE]], align 4
1325 // CHECK4-NEXT:    [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 4
1326 // CHECK4-NEXT:    store ptr @__block_descriptor_tmp.2, ptr [[BLOCK_DESCRIPTOR]], align 4
1327 // CHECK4-NEXT:    [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 5
1328 // CHECK4-NEXT:    store ptr [[TMP0]], ptr [[BLOCK_CAPTURED_THIS_ADDR]], align 4
1329 // CHECK4-NEXT:    [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 6
1330 // CHECK4-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4
1331 // CHECK4-NEXT:    store ptr [[TMP3]], ptr [[BLOCK_CAPTURED]], align 4
1332 // CHECK4-NEXT:    [[BLOCK_CAPTURED5:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 7
1333 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
1334 // CHECK4-NEXT:    store i32 [[TMP4]], ptr [[BLOCK_CAPTURED5]], align 4
1335 // CHECK4-NEXT:    [[BLOCK_CAPTURED6:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[BLOCK]], i32 0, i32 8
1336 // CHECK4-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 4
1337 // CHECK4-NEXT:    store ptr [[TMP5]], ptr [[BLOCK_CAPTURED6]], align 4
1338 // CHECK4-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3
1339 // CHECK4-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
1340 // CHECK4-NEXT:    call void [[TMP7]](ptr [[BLOCK]])
1341 // CHECK4-NEXT:    ret void
1342 //
1343 //
1344 // CHECK4-LABEL: define {{[^@]+}}@g_block_invoke_2
1345 // CHECK4-SAME: (ptr [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {
1346 // CHECK4-NEXT:  entry:
1347 // CHECK4-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 4
1348 // CHECK4-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 4
1349 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
1350 // CHECK4-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
1351 // CHECK4-NEXT:    [[C_CASTED:%.*]] = alloca i32, align 4
1352 // CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 4
1353 // CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 4
1354 // CHECK4-NEXT:    [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5
1355 // CHECK4-NEXT:    [[THIS:%.*]] = load ptr, ptr [[BLOCK_CAPTURED_THIS]], align 4
1356 // CHECK4-NEXT:    [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6
1357 // CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR]], align 4
1358 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1359 // CHECK4-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP1]], 1
1360 // CHECK4-NEXT:    store i32 [[INC]], ptr [[TMP0]], align 4
1361 // CHECK4-NEXT:    [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7
1362 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, ptr [[BLOCK_CAPTURE_ADDR1]], align 4
1363 // CHECK4-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP2]], -1
1364 // CHECK4-NEXT:    store i32 [[DEC]], ptr [[BLOCK_CAPTURE_ADDR1]], align 4
1365 // CHECK4-NEXT:    [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 8
1366 // CHECK4-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR2]], align 4
1367 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
1368 // CHECK4-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP4]], 1
1369 // CHECK4-NEXT:    store i32 [[DIV]], ptr [[TMP3]], align 4
1370 // CHECK4-NEXT:    [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6
1371 // CHECK4-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR3]], align 4
1372 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
1373 // CHECK4-NEXT:    store i32 [[TMP6]], ptr [[A_CASTED]], align 4
1374 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A_CASTED]], align 4
1375 // CHECK4-NEXT:    [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7
1376 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, ptr [[BLOCK_CAPTURE_ADDR4]], align 4
1377 // CHECK4-NEXT:    store i32 [[TMP8]], ptr [[B_CASTED]], align 4
1378 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, ptr [[B_CASTED]], align 4
1379 // CHECK4-NEXT:    [[BLOCK_CAPTURE_ADDR5:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 8
1380 // CHECK4-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR5]], align 4
1381 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
1382 // CHECK4-NEXT:    store i32 [[TMP11]], ptr [[C_CASTED]], align 4
1383 // CHECK4-NEXT:    [[TMP12:%.*]] = load i32, ptr [[C_CASTED]], align 4
1384 // CHECK4-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @g_block_invoke_2.omp_outlined, ptr [[THIS]], i32 [[TMP7]], i32 [[TMP9]], i32 [[TMP12]])
1385 // CHECK4-NEXT:    ret void
1386 //
1387 //
1388 // CHECK4-LABEL: define {{[^@]+}}@g_block_invoke_2.omp_outlined
1389 // CHECK4-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) #[[ATTR3]] {
1390 // CHECK4-NEXT:  entry:
1391 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1392 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1393 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1394 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1395 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
1396 // CHECK4-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 4
1397 // CHECK4-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
1398 // CHECK4-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
1399 // CHECK4-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1400 // CHECK4-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1401 // CHECK4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1402 // CHECK4-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1403 // CHECK4-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
1404 // CHECK4-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 4
1405 // CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1406 // CHECK4-NEXT:    store ptr [[A_ADDR]], ptr [[TMP]], align 4
1407 // CHECK4-NEXT:    store ptr [[C_ADDR]], ptr [[_TMP1]], align 4
1408 // CHECK4-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 4
1409 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
1410 // CHECK4-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP2]], 1
1411 // CHECK4-NEXT:    store i32 [[INC]], ptr [[TMP1]], align 4
1412 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, ptr [[B_ADDR]], align 4
1413 // CHECK4-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP3]], -1
1414 // CHECK4-NEXT:    store i32 [[DEC]], ptr [[B_ADDR]], align 4
1415 // CHECK4-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 4
1416 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
1417 // CHECK4-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP5]], 1
1418 // CHECK4-NEXT:    store i32 [[DIV]], ptr [[TMP4]], align 4
1419 // CHECK4-NEXT:    ret void
1420 //
1421 //
1422 // CHECK9-LABEL: define {{[^@]+}}@main
1423 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
1424 // CHECK9-NEXT:  entry:
1425 // CHECK9-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1426 // CHECK9-NEXT:    [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8
1427 // CHECK9-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1428 // CHECK9-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1429 // CHECK9-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1430 // CHECK9-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1431 // CHECK9-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S]], align 4
1432 // CHECK9-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1433 // CHECK9-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 8
1434 // CHECK9-NEXT:    [[A:%.*]] = alloca i32, align 4
1435 // CHECK9-NEXT:    [[T_VAR_CASTED1:%.*]] = alloca i64, align 8
1436 // CHECK9-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1437 // CHECK9-NEXT:    call void @_ZN2SSC1ERi(ptr nonnull align 8 dereferenceable(32) [[SS]], ptr nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar)
1438 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]])
1439 // CHECK9-NEXT:    store i32 0, ptr [[T_VAR]], align 4
1440 // CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false)
1441 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[S_ARR]], float 1.000000e+00)
1442 // CHECK9-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1
1443 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00)
1444 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00)
1445 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4
1446 // CHECK9-NEXT:    store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4
1447 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
1448 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
1449 // CHECK9-NEXT:    store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4
1450 // CHECK9-NEXT:    [[TMP3:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
1451 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 5, ptr @main.omp_outlined, ptr [[VEC]], i64 [[TMP1]], ptr [[S_ARR]], ptr [[VAR]], i64 [[TMP3]])
1452 // CHECK9-NEXT:    store i32 0, ptr [[A]], align 4
1453 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4
1454 // CHECK9-NEXT:    store i32 [[TMP4]], ptr [[T_VAR_CASTED1]], align 4
1455 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, ptr [[T_VAR_CASTED1]], align 8
1456 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined.1, i64 [[TMP5]])
1457 // CHECK9-NEXT:    [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
1458 // CHECK9-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 4
1459 // CHECK9-NEXT:    call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]]
1460 // CHECK9-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1461 // CHECK9-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
1462 // CHECK9-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1463 // CHECK9:       arraydestroy.body:
1464 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1465 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1466 // CHECK9-NEXT:    call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1467 // CHECK9-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1468 // CHECK9-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1469 // CHECK9:       arraydestroy.done2:
1470 // CHECK9-NEXT:    call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
1471 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4
1472 // CHECK9-NEXT:    ret i32 [[TMP7]]
1473 //
1474 //
1475 // CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC1ERi
1476 // CHECK9-SAME: (ptr nonnull align 8 dereferenceable(32) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1477 // CHECK9-NEXT:  entry:
1478 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1479 // CHECK9-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1480 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1481 // CHECK9-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1482 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1483 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1484 // CHECK9-NEXT:    call void @_ZN2SSC2ERi(ptr nonnull align 8 dereferenceable(32) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]])
1485 // CHECK9-NEXT:    ret void
1486 //
1487 //
1488 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1489 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1490 // CHECK9-NEXT:  entry:
1491 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1492 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1493 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1494 // CHECK9-NEXT:    call void @_ZN1SIfEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]])
1495 // CHECK9-NEXT:    ret void
1496 //
1497 //
1498 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1499 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1500 // CHECK9-NEXT:  entry:
1501 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1502 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1503 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1504 // CHECK9-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1505 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1506 // CHECK9-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1507 // CHECK9-NEXT:    call void @_ZN1SIfEC2Ef(ptr nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
1508 // CHECK9-NEXT:    ret void
1509 //
1510 //
1511 // CHECK9-LABEL: define {{[^@]+}}@main.omp_outlined
1512 // CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] {
1513 // CHECK9-NEXT:  entry:
1514 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1515 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1516 // CHECK9-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
1517 // CHECK9-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1518 // CHECK9-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
1519 // CHECK9-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
1520 // CHECK9-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8
1521 // CHECK9-NEXT:    [[VEC1:%.*]] = alloca [2 x i32], align 4
1522 // CHECK9-NEXT:    [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
1523 // CHECK9-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1524 // CHECK9-NEXT:    [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1525 // CHECK9-NEXT:    [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
1526 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1527 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1528 // CHECK9-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
1529 // CHECK9-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
1530 // CHECK9-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
1531 // CHECK9-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
1532 // CHECK9-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
1533 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
1534 // CHECK9-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
1535 // CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
1536 // CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false)
1537 // CHECK9-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0
1538 // CHECK9-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
1539 // CHECK9-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]
1540 // CHECK9-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1541 // CHECK9:       omp.arraycpy.body:
1542 // CHECK9-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1543 // CHECK9-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1544 // CHECK9-NEXT:    call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]])
1545 // CHECK9-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]])
1546 // CHECK9-NEXT:    call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
1547 // CHECK9-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1548 // CHECK9-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1549 // CHECK9-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]
1550 // CHECK9-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
1551 // CHECK9:       omp.arraycpy.done3:
1552 // CHECK9-NEXT:    call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
1553 // CHECK9-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]])
1554 // CHECK9-NEXT:    call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]]
1555 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
1556 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 0
1557 // CHECK9-NEXT:    store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4
1558 // CHECK9-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i64 0, i64 0
1559 // CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR4]], i64 4, i1 false)
1560 // CHECK9-NEXT:    store i32 2, ptr [[SIVAR_ADDR]], align 4
1561 // CHECK9-NEXT:    call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]]
1562 // CHECK9-NEXT:    [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0
1563 // CHECK9-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2
1564 // CHECK9-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1565 // CHECK9:       arraydestroy.body:
1566 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1567 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1568 // CHECK9-NEXT:    call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1569 // CHECK9-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
1570 // CHECK9-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
1571 // CHECK9:       arraydestroy.done8:
1572 // CHECK9-NEXT:    ret void
1573 //
1574 //
1575 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StC1Ev
1576 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1577 // CHECK9-NEXT:  entry:
1578 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1579 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1580 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1581 // CHECK9-NEXT:    call void @_ZN2StC2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]])
1582 // CHECK9-NEXT:    ret void
1583 //
1584 //
1585 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
1586 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1587 // CHECK9-NEXT:  entry:
1588 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1589 // CHECK9-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
1590 // CHECK9-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
1591 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1592 // CHECK9-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
1593 // CHECK9-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
1594 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1595 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
1596 // CHECK9-NEXT:    call void @_ZN1SIfEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]])
1597 // CHECK9-NEXT:    ret void
1598 //
1599 //
1600 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StD1Ev
1601 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1602 // CHECK9-NEXT:  entry:
1603 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1604 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1605 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1606 // CHECK9-NEXT:    call void @_ZN2StD2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]]
1607 // CHECK9-NEXT:    ret void
1608 //
1609 //
1610 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1611 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1612 // CHECK9-NEXT:  entry:
1613 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1614 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1615 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1616 // CHECK9-NEXT:    call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
1617 // CHECK9-NEXT:    ret void
1618 //
1619 //
1620 // CHECK9-LABEL: define {{[^@]+}}@main.omp_outlined.1
1621 // CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR3]] {
1622 // CHECK9-NEXT:  entry:
1623 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1624 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1625 // CHECK9-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1626 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1627 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1628 // CHECK9-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
1629 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1630 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1631 // CHECK9-NEXT:    [[DOTT_VAR__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP1]], i64 4, ptr inttoptr (i64 1 to ptr))
1632 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
1633 // CHECK9-NEXT:    store i32 [[TMP2]], ptr [[DOTT_VAR__VOID_ADDR]], align 4
1634 // CHECK9-NEXT:    store i32 0, ptr [[DOTT_VAR__VOID_ADDR]], align 4
1635 // CHECK9-NEXT:    call void @__kmpc_free(i32 [[TMP1]], ptr [[DOTT_VAR__VOID_ADDR]], ptr inttoptr (i64 1 to ptr))
1636 // CHECK9-NEXT:    ret void
1637 //
1638 //
1639 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1640 // CHECK9-SAME: () #[[ATTR1]] comdat {
1641 // CHECK9-NEXT:  entry:
1642 // CHECK9-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1643 // CHECK9-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1644 // CHECK9-NEXT:    [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4
1645 // CHECK9-NEXT:    [[T_VAR:%.*]] = alloca i32, align 128
1646 // CHECK9-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 128
1647 // CHECK9-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128
1648 // CHECK9-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128
1649 // CHECK9-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1650 // CHECK9-NEXT:    [[T_VAR_CASTED1:%.*]] = alloca i64, align 8
1651 // CHECK9-NEXT:    call void @_ZN1SIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]])
1652 // CHECK9-NEXT:    call void @_ZN3SSTIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[SST]])
1653 // CHECK9-NEXT:    store i32 0, ptr [[T_VAR]], align 128
1654 // CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VEC]], ptr align 128 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
1655 // CHECK9-NEXT:    call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[S_ARR]], i32 1)
1656 // CHECK9-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1
1657 // CHECK9-NEXT:    call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
1658 // CHECK9-NEXT:    call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[VAR]], i32 3)
1659 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 128
1660 // CHECK9-NEXT:    store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4
1661 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
1662 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[VEC]], i64 [[TMP1]], ptr [[S_ARR]], ptr [[VAR]])
1663 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[T_VAR]], align 128
1664 // CHECK9-NEXT:    store i32 [[TMP2]], ptr [[T_VAR_CASTED1]], align 4
1665 // CHECK9-NEXT:    [[TMP3:%.*]] = load i64, ptr [[T_VAR_CASTED1]], align 8
1666 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_Z5tmainIiET_v.omp_outlined.2, i64 [[TMP3]])
1667 // CHECK9-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1668 // CHECK9-NEXT:    call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
1669 // CHECK9-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1670 // CHECK9-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
1671 // CHECK9-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1672 // CHECK9:       arraydestroy.body:
1673 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1674 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1675 // CHECK9-NEXT:    call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1676 // CHECK9-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1677 // CHECK9-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1678 // CHECK9:       arraydestroy.done2:
1679 // CHECK9-NEXT:    call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
1680 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[RETVAL]], align 4
1681 // CHECK9-NEXT:    ret i32 [[TMP5]]
1682 //
1683 //
1684 // CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC2ERi
1685 // CHECK9-SAME: (ptr nonnull align 8 dereferenceable(32) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1686 // CHECK9-NEXT:  entry:
1687 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1688 // CHECK9-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1689 // CHECK9-NEXT:    [[A2:%.*]] = alloca ptr, align 8
1690 // CHECK9-NEXT:    [[B4:%.*]] = alloca i32, align 4
1691 // CHECK9-NEXT:    [[C7:%.*]] = alloca ptr, align 8
1692 // CHECK9-NEXT:    [[E:%.*]] = alloca ptr, align 8
1693 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1694 // CHECK9-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
1695 // CHECK9-NEXT:    [[C_CASTED:%.*]] = alloca i64, align 8
1696 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1697 // CHECK9-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1698 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1699 // CHECK9-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0
1700 // CHECK9-NEXT:    store i32 0, ptr [[A]], align 8
1701 // CHECK9-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1
1702 // CHECK9-NEXT:    [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 4
1703 // CHECK9-NEXT:    [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16
1704 // CHECK9-NEXT:    [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0
1705 // CHECK9-NEXT:    store i8 [[BF_SET]], ptr [[B]], align 4
1706 // CHECK9-NEXT:    [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2
1707 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1708 // CHECK9-NEXT:    store ptr [[TMP0]], ptr [[C]], align 8
1709 // CHECK9-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0
1710 // CHECK9-NEXT:    store ptr [[A3]], ptr [[A2]], align 8
1711 // CHECK9-NEXT:    [[B5:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1
1712 // CHECK9-NEXT:    [[BF_LOAD6:%.*]] = load i8, ptr [[B5]], align 4
1713 // CHECK9-NEXT:    [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4
1714 // CHECK9-NEXT:    [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4
1715 // CHECK9-NEXT:    [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32
1716 // CHECK9-NEXT:    store i32 [[BF_CAST]], ptr [[B4]], align 4
1717 // CHECK9-NEXT:    [[C8:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2
1718 // CHECK9-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[C8]], align 8
1719 // CHECK9-NEXT:    store ptr [[TMP1]], ptr [[C7]], align 8
1720 // CHECK9-NEXT:    [[E9:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3
1721 // CHECK9-NEXT:    store ptr [[E9]], ptr [[E]], align 8
1722 // CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8
1723 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
1724 // CHECK9-NEXT:    store i32 [[TMP3]], ptr [[A_CASTED]], align 4
1725 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8
1726 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B4]], align 4
1727 // CHECK9-NEXT:    store i32 [[TMP5]], ptr [[B_CASTED]], align 4
1728 // CHECK9-NEXT:    [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
1729 // CHECK9-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[C7]], align 8
1730 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
1731 // CHECK9-NEXT:    store i32 [[TMP8]], ptr [[C_CASTED]], align 4
1732 // CHECK9-NEXT:    [[TMP9:%.*]] = load i64, ptr [[C_CASTED]], align 8
1733 // CHECK9-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[E]], align 8
1734 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]], ptr [[TMP10]])
1735 // CHECK9-NEXT:    ret void
1736 //
1737 //
1738 // CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined
1739 // CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]], ptr nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3]] {
1740 // CHECK9-NEXT:  entry:
1741 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1742 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1743 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1744 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1745 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
1746 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca i64, align 8
1747 // CHECK9-NEXT:    [[E_ADDR:%.*]] = alloca ptr, align 8
1748 // CHECK9-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
1749 // CHECK9-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
1750 // CHECK9-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 8
1751 // CHECK9-NEXT:    [[E3:%.*]] = alloca [4 x i32], align 16
1752 // CHECK9-NEXT:    [[_TMP4:%.*]] = alloca ptr, align 8
1753 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1754 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1755 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1756 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1757 // CHECK9-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
1758 // CHECK9-NEXT:    store i64 [[C]], ptr [[C_ADDR]], align 8
1759 // CHECK9-NEXT:    store ptr [[E]], ptr [[E_ADDR]], align 8
1760 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1761 // CHECK9-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[E_ADDR]], align 8
1762 // CHECK9-NEXT:    store ptr [[A_ADDR]], ptr [[TMP]], align 8
1763 // CHECK9-NEXT:    store ptr [[C_ADDR]], ptr [[_TMP1]], align 8
1764 // CHECK9-NEXT:    store ptr [[TMP1]], ptr [[_TMP2]], align 8
1765 // CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[_TMP2]], align 8
1766 // CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[E3]], ptr align 4 [[TMP2]], i64 16, i1 false)
1767 // CHECK9-NEXT:    store ptr [[E3]], ptr [[_TMP4]], align 8
1768 // CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8
1769 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
1770 // CHECK9-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 1
1771 // CHECK9-NEXT:    store i32 [[INC]], ptr [[TMP3]], align 4
1772 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 4
1773 // CHECK9-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP5]], -1
1774 // CHECK9-NEXT:    store i32 [[DEC]], ptr [[B_ADDR]], align 4
1775 // CHECK9-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8
1776 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
1777 // CHECK9-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP7]], 1
1778 // CHECK9-NEXT:    store i32 [[DIV]], ptr [[TMP6]], align 4
1779 // CHECK9-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8
1780 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], ptr [[TMP8]], i64 0, i64 2
1781 // CHECK9-NEXT:    store i32 1111, ptr [[ARRAYIDX]], align 4
1782 // CHECK9-NEXT:    ret void
1783 //
1784 //
1785 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1786 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1787 // CHECK9-NEXT:  entry:
1788 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1789 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1790 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1791 // CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1792 // CHECK9-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 128
1793 // CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1794 // CHECK9-NEXT:    store float [[CONV]], ptr [[F]], align 4
1795 // CHECK9-NEXT:    ret void
1796 //
1797 //
1798 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1799 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1800 // CHECK9-NEXT:  entry:
1801 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1802 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1803 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1804 // CHECK9-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1805 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1806 // CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1807 // CHECK9-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1808 // CHECK9-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 128
1809 // CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1810 // CHECK9-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1811 // CHECK9-NEXT:    store float [[ADD]], ptr [[F]], align 4
1812 // CHECK9-NEXT:    ret void
1813 //
1814 //
1815 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StC2Ev
1816 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1817 // CHECK9-NEXT:  entry:
1818 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1819 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1820 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1821 // CHECK9-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
1822 // CHECK9-NEXT:    store i32 0, ptr [[A]], align 4
1823 // CHECK9-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
1824 // CHECK9-NEXT:    store i32 0, ptr [[B]], align 4
1825 // CHECK9-NEXT:    ret void
1826 //
1827 //
1828 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
1829 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1830 // CHECK9-NEXT:  entry:
1831 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1832 // CHECK9-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
1833 // CHECK9-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
1834 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1835 // CHECK9-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
1836 // CHECK9-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
1837 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1838 // CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1839 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
1840 // CHECK9-NEXT:    [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0
1841 // CHECK9-NEXT:    [[TMP1:%.*]] = load float, ptr [[F2]], align 4
1842 // CHECK9-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
1843 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 4
1844 // CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
1845 // CHECK9-NEXT:    [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
1846 // CHECK9-NEXT:    store float [[ADD]], ptr [[F]], align 4
1847 // CHECK9-NEXT:    ret void
1848 //
1849 //
1850 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StD2Ev
1851 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1852 // CHECK9-NEXT:  entry:
1853 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1854 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1855 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1856 // CHECK9-NEXT:    ret void
1857 //
1858 //
1859 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1860 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1861 // CHECK9-NEXT:  entry:
1862 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1863 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1864 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1865 // CHECK9-NEXT:    ret void
1866 //
1867 //
1868 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1869 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1870 // CHECK9-NEXT:  entry:
1871 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1872 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1873 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1874 // CHECK9-NEXT:    call void @_ZN1SIiEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]])
1875 // CHECK9-NEXT:    ret void
1876 //
1877 //
1878 // CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev
1879 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1880 // CHECK9-NEXT:  entry:
1881 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1882 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1883 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1884 // CHECK9-NEXT:    call void @_ZN3SSTIiEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]])
1885 // CHECK9-NEXT:    ret void
1886 //
1887 //
1888 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1889 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1890 // CHECK9-NEXT:  entry:
1891 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1892 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1893 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1894 // CHECK9-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1895 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1896 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1897 // CHECK9-NEXT:    call void @_ZN1SIiEC2Ei(ptr nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
1898 // CHECK9-NEXT:    ret void
1899 //
1900 //
1901 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined
1902 // CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
1903 // CHECK9-NEXT:  entry:
1904 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1905 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1906 // CHECK9-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
1907 // CHECK9-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1908 // CHECK9-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
1909 // CHECK9-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
1910 // CHECK9-NEXT:    [[VEC1:%.*]] = alloca [2 x i32], align 128
1911 // CHECK9-NEXT:    [[S_ARR2:%.*]] = alloca [2 x %struct.S.0], align 128
1912 // CHECK9-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1913 // CHECK9-NEXT:    [[VAR4:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128
1914 // CHECK9-NEXT:    [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
1915 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1916 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1917 // CHECK9-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
1918 // CHECK9-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
1919 // CHECK9-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
1920 // CHECK9-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
1921 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
1922 // CHECK9-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
1923 // CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
1924 // CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VEC1]], ptr align 128 [[TMP0]], i64 8, i1 false)
1925 // CHECK9-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0
1926 // CHECK9-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
1927 // CHECK9-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]
1928 // CHECK9-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1929 // CHECK9:       omp.arraycpy.body:
1930 // CHECK9-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1931 // CHECK9-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1932 // CHECK9-NEXT:    call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]])
1933 // CHECK9-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]])
1934 // CHECK9-NEXT:    call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
1935 // CHECK9-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1936 // CHECK9-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1937 // CHECK9-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]
1938 // CHECK9-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
1939 // CHECK9:       omp.arraycpy.done3:
1940 // CHECK9-NEXT:    call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
1941 // CHECK9-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]])
1942 // CHECK9-NEXT:    call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]]
1943 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
1944 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 0
1945 // CHECK9-NEXT:    store i32 [[TMP4]], ptr [[ARRAYIDX]], align 128
1946 // CHECK9-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i64 0, i64 0
1947 // CHECK9-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[ARRAYIDX6]], ptr align 128 [[VAR4]], i64 4, i1 false)
1948 // CHECK9-NEXT:    call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]]
1949 // CHECK9-NEXT:    [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0
1950 // CHECK9-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2
1951 // CHECK9-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1952 // CHECK9:       arraydestroy.body:
1953 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1954 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1955 // CHECK9-NEXT:    call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1956 // CHECK9-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
1957 // CHECK9-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
1958 // CHECK9:       arraydestroy.done8:
1959 // CHECK9-NEXT:    ret void
1960 //
1961 //
1962 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
1963 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1964 // CHECK9-NEXT:  entry:
1965 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1966 // CHECK9-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
1967 // CHECK9-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
1968 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1969 // CHECK9-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
1970 // CHECK9-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
1971 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1972 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
1973 // CHECK9-NEXT:    call void @_ZN1SIiEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]])
1974 // CHECK9-NEXT:    ret void
1975 //
1976 //
1977 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1978 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1979 // CHECK9-NEXT:  entry:
1980 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1981 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1982 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1983 // CHECK9-NEXT:    call void @_ZN1SIiED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
1984 // CHECK9-NEXT:    ret void
1985 //
1986 //
1987 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined.2
1988 // CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR3]] {
1989 // CHECK9-NEXT:  entry:
1990 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1991 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1992 // CHECK9-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1993 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1994 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1995 // CHECK9-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
1996 // CHECK9-NEXT:    ret void
1997 //
1998 //
1999 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2000 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2001 // CHECK9-NEXT:  entry:
2002 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2003 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2004 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2005 // CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2006 // CHECK9-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 128
2007 // CHECK9-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
2008 // CHECK9-NEXT:    ret void
2009 //
2010 //
2011 // CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev
2012 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2013 // CHECK9-NEXT:  entry:
2014 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2015 // CHECK9-NEXT:    [[A2:%.*]] = alloca ptr, align 8
2016 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2017 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2018 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2019 // CHECK9-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SST:%.*]], ptr [[THIS1]], i32 0, i32 0
2020 // CHECK9-NEXT:    store i32 0, ptr [[A]], align 4
2021 // CHECK9-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SST]], ptr [[THIS1]], i32 0, i32 0
2022 // CHECK9-NEXT:    store ptr [[A3]], ptr [[A2]], align 8
2023 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A2]], align 8
2024 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
2025 // CHECK9-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
2026 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
2027 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @_ZN3SSTIiEC2Ev.omp_outlined, ptr [[THIS1]], i64 [[TMP2]])
2028 // CHECK9-NEXT:    ret void
2029 //
2030 //
2031 // CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev.omp_outlined
2032 // CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i64 [[A:%.*]]) #[[ATTR3]] {
2033 // CHECK9-NEXT:  entry:
2034 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2035 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2036 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2037 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2038 // CHECK9-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
2039 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2040 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2041 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2042 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
2043 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2044 // CHECK9-NEXT:    store ptr [[A_ADDR]], ptr [[TMP]], align 8
2045 // CHECK9-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8
2046 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
2047 // CHECK9-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP2]], 1
2048 // CHECK9-NEXT:    store i32 [[INC]], ptr [[TMP1]], align 4
2049 // CHECK9-NEXT:    ret void
2050 //
2051 //
2052 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2053 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2054 // CHECK9-NEXT:  entry:
2055 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2056 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2057 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2058 // CHECK9-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2059 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2060 // CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2061 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2062 // CHECK9-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 128
2063 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2064 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
2065 // CHECK9-NEXT:    ret void
2066 //
2067 //
2068 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
2069 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2070 // CHECK9-NEXT:  entry:
2071 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2072 // CHECK9-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
2073 // CHECK9-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
2074 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2075 // CHECK9-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
2076 // CHECK9-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
2077 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2078 // CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2079 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
2080 // CHECK9-NEXT:    [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0
2081 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[F2]], align 4
2082 // CHECK9-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
2083 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 4
2084 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
2085 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
2086 // CHECK9-NEXT:    ret void
2087 //
2088 //
2089 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2090 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2091 // CHECK9-NEXT:  entry:
2092 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2093 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2094 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2095 // CHECK9-NEXT:    ret void
2096 //
2097 //
2098 // CHECK11-LABEL: define {{[^@]+}}@main
2099 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
2100 // CHECK11-NEXT:  entry:
2101 // CHECK11-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2102 // CHECK11-NEXT:    [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8
2103 // CHECK11-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8
2104 // CHECK11-NEXT:    store i32 0, ptr [[RETVAL]], align 4
2105 // CHECK11-NEXT:    call void @_ZN2SSC1ERi(ptr nonnull align 8 dereferenceable(32) [[SS]], ptr nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar)
2106 // CHECK11-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0
2107 // CHECK11-NEXT:    store ptr @_ZZ4mainE5sivar, ptr [[TMP0]], align 8
2108 // CHECK11-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr nonnull align 8 dereferenceable(8) [[REF_TMP]])
2109 // CHECK11-NEXT:    ret i32 0
2110 //
2111 //
2112 // CHECK11-LABEL: define {{[^@]+}}@_ZN2SSC1ERi
2113 // CHECK11-SAME: (ptr nonnull align 8 dereferenceable(32) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2114 // CHECK11-NEXT:  entry:
2115 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2116 // CHECK11-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2117 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2118 // CHECK11-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2119 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2120 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2121 // CHECK11-NEXT:    call void @_ZN2SSC2ERi(ptr nonnull align 8 dereferenceable(32) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]])
2122 // CHECK11-NEXT:    ret void
2123 //
2124 //
2125 // CHECK11-LABEL: define {{[^@]+}}@_ZN2SSC2ERi
2126 // CHECK11-SAME: (ptr nonnull align 8 dereferenceable(32) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2127 // CHECK11-NEXT:  entry:
2128 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2129 // CHECK11-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2130 // CHECK11-NEXT:    [[A2:%.*]] = alloca ptr, align 8
2131 // CHECK11-NEXT:    [[B4:%.*]] = alloca i32, align 4
2132 // CHECK11-NEXT:    [[C7:%.*]] = alloca ptr, align 8
2133 // CHECK11-NEXT:    [[E:%.*]] = alloca ptr, align 8
2134 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2135 // CHECK11-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
2136 // CHECK11-NEXT:    [[C_CASTED:%.*]] = alloca i64, align 8
2137 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2138 // CHECK11-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2139 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2140 // CHECK11-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0
2141 // CHECK11-NEXT:    store i32 0, ptr [[A]], align 8
2142 // CHECK11-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1
2143 // CHECK11-NEXT:    [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 4
2144 // CHECK11-NEXT:    [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16
2145 // CHECK11-NEXT:    [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0
2146 // CHECK11-NEXT:    store i8 [[BF_SET]], ptr [[B]], align 4
2147 // CHECK11-NEXT:    [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2
2148 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2149 // CHECK11-NEXT:    store ptr [[TMP0]], ptr [[C]], align 8
2150 // CHECK11-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0
2151 // CHECK11-NEXT:    store ptr [[A3]], ptr [[A2]], align 8
2152 // CHECK11-NEXT:    [[B5:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1
2153 // CHECK11-NEXT:    [[BF_LOAD6:%.*]] = load i8, ptr [[B5]], align 4
2154 // CHECK11-NEXT:    [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4
2155 // CHECK11-NEXT:    [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4
2156 // CHECK11-NEXT:    [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32
2157 // CHECK11-NEXT:    store i32 [[BF_CAST]], ptr [[B4]], align 4
2158 // CHECK11-NEXT:    [[C8:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2
2159 // CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[C8]], align 8
2160 // CHECK11-NEXT:    store ptr [[TMP1]], ptr [[C7]], align 8
2161 // CHECK11-NEXT:    [[E9:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3
2162 // CHECK11-NEXT:    store ptr [[E9]], ptr [[E]], align 8
2163 // CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8
2164 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
2165 // CHECK11-NEXT:    store i32 [[TMP3]], ptr [[A_CASTED]], align 4
2166 // CHECK11-NEXT:    [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8
2167 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B4]], align 4
2168 // CHECK11-NEXT:    store i32 [[TMP5]], ptr [[B_CASTED]], align 4
2169 // CHECK11-NEXT:    [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
2170 // CHECK11-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[C7]], align 8
2171 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
2172 // CHECK11-NEXT:    store i32 [[TMP8]], ptr [[C_CASTED]], align 4
2173 // CHECK11-NEXT:    [[TMP9:%.*]] = load i64, ptr [[C_CASTED]], align 8
2174 // CHECK11-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[E]], align 8
2175 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 5, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]], ptr [[TMP10]])
2176 // CHECK11-NEXT:    ret void
2177 //
2178 //
2179 // CHECK11-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined
2180 // CHECK11-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]], ptr nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR2:[0-9]+]] {
2181 // CHECK11-NEXT:  entry:
2182 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2183 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2184 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2185 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2186 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
2187 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca i64, align 8
2188 // CHECK11-NEXT:    [[E_ADDR:%.*]] = alloca ptr, align 8
2189 // CHECK11-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
2190 // CHECK11-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
2191 // CHECK11-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 8
2192 // CHECK11-NEXT:    [[E3:%.*]] = alloca [4 x i32], align 16
2193 // CHECK11-NEXT:    [[_TMP4:%.*]] = alloca ptr, align 8
2194 // CHECK11-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
2195 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2196 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2197 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2198 // CHECK11-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
2199 // CHECK11-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
2200 // CHECK11-NEXT:    store i64 [[C]], ptr [[C_ADDR]], align 8
2201 // CHECK11-NEXT:    store ptr [[E]], ptr [[E_ADDR]], align 8
2202 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2203 // CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[E_ADDR]], align 8
2204 // CHECK11-NEXT:    store ptr [[A_ADDR]], ptr [[TMP]], align 8
2205 // CHECK11-NEXT:    store ptr [[C_ADDR]], ptr [[_TMP1]], align 8
2206 // CHECK11-NEXT:    store ptr [[TMP1]], ptr [[_TMP2]], align 8
2207 // CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[_TMP2]], align 8
2208 // CHECK11-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[E3]], ptr align 4 [[TMP2]], i64 16, i1 false)
2209 // CHECK11-NEXT:    store ptr [[E3]], ptr [[_TMP4]], align 8
2210 // CHECK11-NEXT:    [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
2211 // CHECK11-NEXT:    store ptr [[TMP0]], ptr [[TMP3]], align 8
2212 // CHECK11-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
2213 // CHECK11-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8
2214 // CHECK11-NEXT:    store ptr [[TMP5]], ptr [[TMP4]], align 8
2215 // CHECK11-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2
2216 // CHECK11-NEXT:    store ptr [[B_ADDR]], ptr [[TMP6]], align 8
2217 // CHECK11-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3
2218 // CHECK11-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8
2219 // CHECK11-NEXT:    store ptr [[TMP8]], ptr [[TMP7]], align 8
2220 // CHECK11-NEXT:    call void @_ZZN2SSC1ERiENKUlvE_clEv(ptr nonnull align 8 dereferenceable(32) [[REF_TMP]])
2221 // CHECK11-NEXT:    ret void
2222 //
2223 //
2224 // CHECK11-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv
2225 // CHECK11-SAME: (ptr nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR1]] align 2 {
2226 // CHECK11-NEXT:  entry:
2227 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2228 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2229 // CHECK11-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
2230 // CHECK11-NEXT:    [[C_CASTED:%.*]] = alloca i64, align 8
2231 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2232 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2233 // CHECK11-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2234 // CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
2235 // CHECK11-NEXT:    [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1
2236 // CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
2237 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
2238 // CHECK11-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP4]], 1
2239 // CHECK11-NEXT:    store i32 [[INC]], ptr [[TMP3]], align 4
2240 // CHECK11-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 2
2241 // CHECK11-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
2242 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
2243 // CHECK11-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP7]], -1
2244 // CHECK11-NEXT:    store i32 [[DEC]], ptr [[TMP6]], align 4
2245 // CHECK11-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 3
2246 // CHECK11-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8
2247 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
2248 // CHECK11-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP10]], 1
2249 // CHECK11-NEXT:    store i32 [[DIV]], ptr [[TMP9]], align 4
2250 // CHECK11-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1
2251 // CHECK11-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8
2252 // CHECK11-NEXT:    [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4
2253 // CHECK11-NEXT:    store i32 [[TMP13]], ptr [[A_CASTED]], align 4
2254 // CHECK11-NEXT:    [[TMP14:%.*]] = load i64, ptr [[A_CASTED]], align 8
2255 // CHECK11-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 2
2256 // CHECK11-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8
2257 // CHECK11-NEXT:    [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4
2258 // CHECK11-NEXT:    store i32 [[TMP17]], ptr [[B_CASTED]], align 4
2259 // CHECK11-NEXT:    [[TMP18:%.*]] = load i64, ptr [[B_CASTED]], align 8
2260 // CHECK11-NEXT:    [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 3
2261 // CHECK11-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8
2262 // CHECK11-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
2263 // CHECK11-NEXT:    store i32 [[TMP21]], ptr [[C_CASTED]], align 4
2264 // CHECK11-NEXT:    [[TMP22:%.*]] = load i64, ptr [[C_CASTED]], align 8
2265 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined, ptr [[TMP1]], i64 [[TMP14]], i64 [[TMP18]], i64 [[TMP22]])
2266 // CHECK11-NEXT:    ret void
2267 //
2268 //
2269 // CHECK11-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined
2270 // CHECK11-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR2]] {
2271 // CHECK11-NEXT:  entry:
2272 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2273 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2274 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2275 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2276 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
2277 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca i64, align 8
2278 // CHECK11-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
2279 // CHECK11-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
2280 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2281 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2282 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2283 // CHECK11-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
2284 // CHECK11-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
2285 // CHECK11-NEXT:    store i64 [[C]], ptr [[C_ADDR]], align 8
2286 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2287 // CHECK11-NEXT:    store ptr [[A_ADDR]], ptr [[TMP]], align 8
2288 // CHECK11-NEXT:    store ptr [[C_ADDR]], ptr [[_TMP1]], align 8
2289 // CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8
2290 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
2291 // CHECK11-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP2]], 1
2292 // CHECK11-NEXT:    store i32 [[INC]], ptr [[TMP1]], align 4
2293 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[B_ADDR]], align 4
2294 // CHECK11-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP3]], -1
2295 // CHECK11-NEXT:    store i32 [[DEC]], ptr [[B_ADDR]], align 4
2296 // CHECK11-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8
2297 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
2298 // CHECK11-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP5]], 1
2299 // CHECK11-NEXT:    store i32 [[DIV]], ptr [[TMP4]], align 4
2300 // CHECK11-NEXT:    ret void
2301 //
2302 //
2303 // CHECK12-LABEL: define {{[^@]+}}@main
2304 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] {
2305 // CHECK12-NEXT:  entry:
2306 // CHECK12-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2307 // CHECK12-NEXT:    [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8
2308 // CHECK12-NEXT:    [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32 }>, align 8
2309 // CHECK12-NEXT:    store i32 0, ptr [[RETVAL]], align 4
2310 // CHECK12-NEXT:    call void @_ZN2SSC1ERi(ptr nonnull align 8 dereferenceable(32) [[SS]], ptr nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar)
2311 // CHECK12-NEXT:    [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 0
2312 // CHECK12-NEXT:    store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8
2313 // CHECK12-NEXT:    [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 1
2314 // CHECK12-NEXT:    store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8
2315 // CHECK12-NEXT:    [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 2
2316 // CHECK12-NEXT:    store i32 0, ptr [[BLOCK_RESERVED]], align 4
2317 // CHECK12-NEXT:    [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 3
2318 // CHECK12-NEXT:    store ptr @__main_block_invoke, ptr [[BLOCK_INVOKE]], align 8
2319 // CHECK12-NEXT:    [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 4
2320 // CHECK12-NEXT:    store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR]], align 8
2321 // CHECK12-NEXT:    [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 5
2322 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
2323 // CHECK12-NEXT:    store i32 [[TMP0]], ptr [[BLOCK_CAPTURED]], align 8
2324 // CHECK12-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3
2325 // CHECK12-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
2326 // CHECK12-NEXT:    call void [[TMP2]](ptr [[BLOCK]])
2327 // CHECK12-NEXT:    ret i32 0
2328 //
2329 //
2330 // CHECK12-LABEL: define {{[^@]+}}@_ZN2SSC1ERi
2331 // CHECK12-SAME: (ptr nonnull align 8 dereferenceable(32) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2332 // CHECK12-NEXT:  entry:
2333 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2334 // CHECK12-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2335 // CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2336 // CHECK12-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2337 // CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2338 // CHECK12-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2339 // CHECK12-NEXT:    call void @_ZN2SSC2ERi(ptr nonnull align 8 dereferenceable(32) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]])
2340 // CHECK12-NEXT:    ret void
2341 //
2342 //
2343 // CHECK12-LABEL: define {{[^@]+}}@__main_block_invoke
2344 // CHECK12-SAME: (ptr [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {
2345 // CHECK12-NEXT:  entry:
2346 // CHECK12-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8
2347 // CHECK12-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 8
2348 // CHECK12-NEXT:    [[G_CASTED:%.*]] = alloca i64, align 8
2349 // CHECK12-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 8
2350 // CHECK12-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
2351 // CHECK12-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8
2352 // CHECK12-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 128
2353 // CHECK12-NEXT:    store i32 [[TMP0]], ptr [[G_CASTED]], align 4
2354 // CHECK12-NEXT:    [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 8
2355 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
2356 // CHECK12-NEXT:    store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4
2357 // CHECK12-NEXT:    [[TMP3:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
2358 // CHECK12-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @__main_block_invoke.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])
2359 // CHECK12-NEXT:    ret void
2360 //
2361 //
2362 // CHECK12-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined
2363 // CHECK12-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] {
2364 // CHECK12-NEXT:  entry:
2365 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2366 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2367 // CHECK12-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 8
2368 // CHECK12-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8
2369 // CHECK12-NEXT:    [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, align 128
2370 // CHECK12-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2371 // CHECK12-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2372 // CHECK12-NEXT:    store i64 [[G]], ptr [[G_ADDR]], align 8
2373 // CHECK12-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
2374 // CHECK12-NEXT:    store i32 1, ptr [[G_ADDR]], align 4
2375 // CHECK12-NEXT:    store i32 2, ptr [[SIVAR_ADDR]], align 4
2376 // CHECK12-NEXT:    [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 0
2377 // CHECK12-NEXT:    store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 128
2378 // CHECK12-NEXT:    [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 1
2379 // CHECK12-NEXT:    store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8
2380 // CHECK12-NEXT:    [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 2
2381 // CHECK12-NEXT:    store i32 0, ptr [[BLOCK_RESERVED]], align 4
2382 // CHECK12-NEXT:    [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 3
2383 // CHECK12-NEXT:    store ptr @g_block_invoke, ptr [[BLOCK_INVOKE]], align 16
2384 // CHECK12-NEXT:    [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 4
2385 // CHECK12-NEXT:    store ptr @__block_descriptor_tmp, ptr [[BLOCK_DESCRIPTOR]], align 8
2386 // CHECK12-NEXT:    [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 7
2387 // CHECK12-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr [[G_ADDR]], align 4
2388 // CHECK12-NEXT:    store volatile i32 [[TMP0]], ptr [[BLOCK_CAPTURED]], align 128
2389 // CHECK12-NEXT:    [[BLOCK_CAPTURED1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 5
2390 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4
2391 // CHECK12-NEXT:    store i32 [[TMP1]], ptr [[BLOCK_CAPTURED1]], align 32
2392 // CHECK12-NEXT:    [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3
2393 // CHECK12-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
2394 // CHECK12-NEXT:    call void [[TMP3]](ptr [[BLOCK]])
2395 // CHECK12-NEXT:    ret void
2396 //
2397 //
2398 // CHECK12-LABEL: define {{[^@]+}}@g_block_invoke
2399 // CHECK12-SAME: (ptr [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {
2400 // CHECK12-NEXT:  entry:
2401 // CHECK12-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8
2402 // CHECK12-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 8
2403 // CHECK12-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
2404 // CHECK12-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8
2405 // CHECK12-NEXT:    [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7
2406 // CHECK12-NEXT:    store i32 2, ptr [[BLOCK_CAPTURE_ADDR]], align 128
2407 // CHECK12-NEXT:    [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5
2408 // CHECK12-NEXT:    store i32 4, ptr [[BLOCK_CAPTURE_ADDR1]], align 32
2409 // CHECK12-NEXT:    ret void
2410 //
2411 //
2412 // CHECK12-LABEL: define {{[^@]+}}@_ZN2SSC2ERi
2413 // CHECK12-SAME: (ptr nonnull align 8 dereferenceable(32) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2414 // CHECK12-NEXT:  entry:
2415 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2416 // CHECK12-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2417 // CHECK12-NEXT:    [[A2:%.*]] = alloca ptr, align 8
2418 // CHECK12-NEXT:    [[B4:%.*]] = alloca i32, align 4
2419 // CHECK12-NEXT:    [[C7:%.*]] = alloca ptr, align 8
2420 // CHECK12-NEXT:    [[E:%.*]] = alloca ptr, align 8
2421 // CHECK12-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2422 // CHECK12-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
2423 // CHECK12-NEXT:    [[C_CASTED:%.*]] = alloca i64, align 8
2424 // CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2425 // CHECK12-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2426 // CHECK12-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2427 // CHECK12-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0
2428 // CHECK12-NEXT:    store i32 0, ptr [[A]], align 8
2429 // CHECK12-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1
2430 // CHECK12-NEXT:    [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 4
2431 // CHECK12-NEXT:    [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16
2432 // CHECK12-NEXT:    [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0
2433 // CHECK12-NEXT:    store i8 [[BF_SET]], ptr [[B]], align 4
2434 // CHECK12-NEXT:    [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2
2435 // CHECK12-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2436 // CHECK12-NEXT:    store ptr [[TMP0]], ptr [[C]], align 8
2437 // CHECK12-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0
2438 // CHECK12-NEXT:    store ptr [[A3]], ptr [[A2]], align 8
2439 // CHECK12-NEXT:    [[B5:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1
2440 // CHECK12-NEXT:    [[BF_LOAD6:%.*]] = load i8, ptr [[B5]], align 4
2441 // CHECK12-NEXT:    [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4
2442 // CHECK12-NEXT:    [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4
2443 // CHECK12-NEXT:    [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32
2444 // CHECK12-NEXT:    store i32 [[BF_CAST]], ptr [[B4]], align 4
2445 // CHECK12-NEXT:    [[C8:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2
2446 // CHECK12-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[C8]], align 8
2447 // CHECK12-NEXT:    store ptr [[TMP1]], ptr [[C7]], align 8
2448 // CHECK12-NEXT:    [[E9:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3
2449 // CHECK12-NEXT:    store ptr [[E9]], ptr [[E]], align 8
2450 // CHECK12-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8
2451 // CHECK12-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
2452 // CHECK12-NEXT:    store i32 [[TMP3]], ptr [[A_CASTED]], align 4
2453 // CHECK12-NEXT:    [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8
2454 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B4]], align 4
2455 // CHECK12-NEXT:    store i32 [[TMP5]], ptr [[B_CASTED]], align 4
2456 // CHECK12-NEXT:    [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
2457 // CHECK12-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[C7]], align 8
2458 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
2459 // CHECK12-NEXT:    store i32 [[TMP8]], ptr [[C_CASTED]], align 4
2460 // CHECK12-NEXT:    [[TMP9:%.*]] = load i64, ptr [[C_CASTED]], align 8
2461 // CHECK12-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[E]], align 8
2462 // CHECK12-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]], ptr [[TMP10]])
2463 // CHECK12-NEXT:    ret void
2464 //
2465 //
2466 // CHECK12-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined
2467 // CHECK12-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]], ptr nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3]] {
2468 // CHECK12-NEXT:  entry:
2469 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2470 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2471 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2472 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2473 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
2474 // CHECK12-NEXT:    [[C_ADDR:%.*]] = alloca i64, align 8
2475 // CHECK12-NEXT:    [[E_ADDR:%.*]] = alloca ptr, align 8
2476 // CHECK12-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
2477 // CHECK12-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
2478 // CHECK12-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 8
2479 // CHECK12-NEXT:    [[E3:%.*]] = alloca [4 x i32], align 16
2480 // CHECK12-NEXT:    [[_TMP4:%.*]] = alloca ptr, align 8
2481 // CHECK12-NEXT:    [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, align 8
2482 // CHECK12-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2483 // CHECK12-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2484 // CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2485 // CHECK12-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
2486 // CHECK12-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
2487 // CHECK12-NEXT:    store i64 [[C]], ptr [[C_ADDR]], align 8
2488 // CHECK12-NEXT:    store ptr [[E]], ptr [[E_ADDR]], align 8
2489 // CHECK12-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2490 // CHECK12-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[E_ADDR]], align 8
2491 // CHECK12-NEXT:    store ptr [[A_ADDR]], ptr [[TMP]], align 8
2492 // CHECK12-NEXT:    store ptr [[C_ADDR]], ptr [[_TMP1]], align 8
2493 // CHECK12-NEXT:    store ptr [[TMP1]], ptr [[_TMP2]], align 8
2494 // CHECK12-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[_TMP2]], align 8
2495 // CHECK12-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[E3]], ptr align 4 [[TMP2]], i64 16, i1 false)
2496 // CHECK12-NEXT:    store ptr [[E3]], ptr [[_TMP4]], align 8
2497 // CHECK12-NEXT:    [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 0
2498 // CHECK12-NEXT:    store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8
2499 // CHECK12-NEXT:    [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 1
2500 // CHECK12-NEXT:    store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8
2501 // CHECK12-NEXT:    [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 2
2502 // CHECK12-NEXT:    store i32 0, ptr [[BLOCK_RESERVED]], align 4
2503 // CHECK12-NEXT:    [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 3
2504 // CHECK12-NEXT:    store ptr @g_block_invoke_2, ptr [[BLOCK_INVOKE]], align 8
2505 // CHECK12-NEXT:    [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 4
2506 // CHECK12-NEXT:    store ptr @__block_descriptor_tmp.2, ptr [[BLOCK_DESCRIPTOR]], align 8
2507 // CHECK12-NEXT:    [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 5
2508 // CHECK12-NEXT:    store ptr [[TMP0]], ptr [[BLOCK_CAPTURED_THIS_ADDR]], align 8
2509 // CHECK12-NEXT:    [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 6
2510 // CHECK12-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8
2511 // CHECK12-NEXT:    store ptr [[TMP3]], ptr [[BLOCK_CAPTURED]], align 8
2512 // CHECK12-NEXT:    [[BLOCK_CAPTURED5:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 8
2513 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
2514 // CHECK12-NEXT:    store i32 [[TMP4]], ptr [[BLOCK_CAPTURED5]], align 8
2515 // CHECK12-NEXT:    [[BLOCK_CAPTURED6:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 7
2516 // CHECK12-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8
2517 // CHECK12-NEXT:    store ptr [[TMP5]], ptr [[BLOCK_CAPTURED6]], align 8
2518 // CHECK12-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3
2519 // CHECK12-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
2520 // CHECK12-NEXT:    call void [[TMP7]](ptr [[BLOCK]])
2521 // CHECK12-NEXT:    ret void
2522 //
2523 //
2524 // CHECK12-LABEL: define {{[^@]+}}@g_block_invoke_2
2525 // CHECK12-SAME: (ptr [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {
2526 // CHECK12-NEXT:  entry:
2527 // CHECK12-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8
2528 // CHECK12-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 8
2529 // CHECK12-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2530 // CHECK12-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
2531 // CHECK12-NEXT:    [[C_CASTED:%.*]] = alloca i64, align 8
2532 // CHECK12-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
2533 // CHECK12-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8
2534 // CHECK12-NEXT:    [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5
2535 // CHECK12-NEXT:    [[THIS:%.*]] = load ptr, ptr [[BLOCK_CAPTURED_THIS]], align 8
2536 // CHECK12-NEXT:    [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6
2537 // CHECK12-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR]], align 8
2538 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
2539 // CHECK12-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP1]], 1
2540 // CHECK12-NEXT:    store i32 [[INC]], ptr [[TMP0]], align 4
2541 // CHECK12-NEXT:    [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 8
2542 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, ptr [[BLOCK_CAPTURE_ADDR1]], align 8
2543 // CHECK12-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP2]], -1
2544 // CHECK12-NEXT:    store i32 [[DEC]], ptr [[BLOCK_CAPTURE_ADDR1]], align 8
2545 // CHECK12-NEXT:    [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7
2546 // CHECK12-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR2]], align 8
2547 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
2548 // CHECK12-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP4]], 1
2549 // CHECK12-NEXT:    store i32 [[DIV]], ptr [[TMP3]], align 4
2550 // CHECK12-NEXT:    [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6
2551 // CHECK12-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR3]], align 8
2552 // CHECK12-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
2553 // CHECK12-NEXT:    store i32 [[TMP6]], ptr [[A_CASTED]], align 4
2554 // CHECK12-NEXT:    [[TMP7:%.*]] = load i64, ptr [[A_CASTED]], align 8
2555 // CHECK12-NEXT:    [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 8
2556 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, ptr [[BLOCK_CAPTURE_ADDR4]], align 8
2557 // CHECK12-NEXT:    store i32 [[TMP8]], ptr [[B_CASTED]], align 4
2558 // CHECK12-NEXT:    [[TMP9:%.*]] = load i64, ptr [[B_CASTED]], align 8
2559 // CHECK12-NEXT:    [[BLOCK_CAPTURE_ADDR5:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7
2560 // CHECK12-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR5]], align 8
2561 // CHECK12-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
2562 // CHECK12-NEXT:    store i32 [[TMP11]], ptr [[C_CASTED]], align 4
2563 // CHECK12-NEXT:    [[TMP12:%.*]] = load i64, ptr [[C_CASTED]], align 8
2564 // CHECK12-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @g_block_invoke_2.omp_outlined, ptr [[THIS]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP12]])
2565 // CHECK12-NEXT:    ret void
2566 //
2567 //
2568 // CHECK12-LABEL: define {{[^@]+}}@g_block_invoke_2.omp_outlined
2569 // CHECK12-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR3]] {
2570 // CHECK12-NEXT:  entry:
2571 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2572 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2573 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2574 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2575 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
2576 // CHECK12-NEXT:    [[C_ADDR:%.*]] = alloca i64, align 8
2577 // CHECK12-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
2578 // CHECK12-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
2579 // CHECK12-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2580 // CHECK12-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2581 // CHECK12-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2582 // CHECK12-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
2583 // CHECK12-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
2584 // CHECK12-NEXT:    store i64 [[C]], ptr [[C_ADDR]], align 8
2585 // CHECK12-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2586 // CHECK12-NEXT:    store ptr [[A_ADDR]], ptr [[TMP]], align 8
2587 // CHECK12-NEXT:    store ptr [[C_ADDR]], ptr [[_TMP1]], align 8
2588 // CHECK12-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8
2589 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
2590 // CHECK12-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP2]], 1
2591 // CHECK12-NEXT:    store i32 [[INC]], ptr [[TMP1]], align 4
2592 // CHECK12-NEXT:    [[TMP3:%.*]] = load i32, ptr [[B_ADDR]], align 4
2593 // CHECK12-NEXT:    [[DEC:%.*]] = add nsw i32 [[TMP3]], -1
2594 // CHECK12-NEXT:    store i32 [[DEC]], ptr [[B_ADDR]], align 4
2595 // CHECK12-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8
2596 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
2597 // CHECK12-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP5]], 1
2598 // CHECK12-NEXT:    store i32 [[DIV]], ptr [[TMP4]], align 4
2599 // CHECK12-NEXT:    ret void
2600 //
2601 //
2602 // CHECK17-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe
2603 // CHECK17-SAME: (ptr [[A:%.*]], ptr [[S:%.*]], i32 [[N:%.*]], ptr [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] {
2604 // CHECK17-NEXT:  entry:
2605 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2606 // CHECK17-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
2607 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2608 // CHECK17-NEXT:    [[VLA1_ADDR:%.*]] = alloca ptr, align 8
2609 // CHECK17-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
2610 // CHECK17-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
2611 // CHECK17-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
2612 // CHECK17-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2613 // CHECK17-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
2614 // CHECK17-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
2615 // CHECK17-NEXT:    store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8
2616 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
2617 // CHECK17-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
2618 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
2619 // CHECK17-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
2620 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
2621 // CHECK17-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
2622 // CHECK17-NEXT:    [[TMP6:%.*]] = call ptr @llvm.stacksave.p0()
2623 // CHECK17-NEXT:    store ptr [[TMP6]], ptr [[SAVED_STACK]], align 8
2624 // CHECK17-NEXT:    [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]]
2625 // CHECK17-NEXT:    [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128
2626 // CHECK17-NEXT:    store i64 [[TMP3]], ptr [[__VLA_EXPR0]], align 8
2627 // CHECK17-NEXT:    store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8
2628 // CHECK17-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[S_ADDR]], align 8
2629 // CHECK17-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8
2630 // CHECK17-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2631 // CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 8, ptr @_Z10array_funcPfP2StiPe.omp_outlined, ptr [[TMP8]], ptr [[N_ADDR]], i64 [[TMP1]], ptr [[TMP9]], ptr [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], ptr [[VLA]])
2632 // CHECK17-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
2633 // CHECK17-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP11]])
2634 // CHECK17-NEXT:    ret void
2635 //
2636 //
2637 // CHECK17-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe.omp_outlined
2638 // CHECK17-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[S:%.*]], ptr nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], ptr [[VLA1:%.*]], ptr [[A:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], ptr nonnull align 8 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2:[0-9]+]] {
2639 // CHECK17-NEXT:  entry:
2640 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2641 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2642 // CHECK17-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
2643 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca ptr, align 8
2644 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
2645 // CHECK17-NEXT:    [[VLA1_ADDR:%.*]] = alloca ptr, align 8
2646 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2647 // CHECK17-NEXT:    [[VLA_ADDR3:%.*]] = alloca i64, align 8
2648 // CHECK17-NEXT:    [[VLA_ADDR5:%.*]] = alloca i64, align 8
2649 // CHECK17-NEXT:    [[VLA2_ADDR:%.*]] = alloca ptr, align 8
2650 // CHECK17-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
2651 // CHECK17-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
2652 // CHECK17-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
2653 // CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2654 // CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2655 // CHECK17-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
2656 // CHECK17-NEXT:    store ptr [[N]], ptr [[N_ADDR]], align 8
2657 // CHECK17-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
2658 // CHECK17-NEXT:    store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8
2659 // CHECK17-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2660 // CHECK17-NEXT:    store i64 [[VLA2]], ptr [[VLA_ADDR3]], align 8
2661 // CHECK17-NEXT:    store i64 [[VLA4]], ptr [[VLA_ADDR5]], align 8
2662 // CHECK17-NEXT:    store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 8
2663 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 8
2664 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
2665 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR3]], align 8
2666 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR5]], align 8
2667 // CHECK17-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 8
2668 // CHECK17-NEXT:    [[TMP5:%.*]] = call ptr @llvm.stacksave.p0()
2669 // CHECK17-NEXT:    store ptr [[TMP5]], ptr [[SAVED_STACK]], align 8
2670 // CHECK17-NEXT:    [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]]
2671 // CHECK17-NEXT:    [[VLA7:%.*]] = alloca double, i64 [[TMP6]], align 128
2672 // CHECK17-NEXT:    store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
2673 // CHECK17-NEXT:    store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8
2674 // CHECK17-NEXT:    [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]]
2675 // CHECK17-NEXT:    [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 8
2676 // CHECK17-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VLA7]], ptr align 128 [[TMP4]], i64 [[TMP8]], i1 false)
2677 // CHECK17-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[S_ADDR]], align 8
2678 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP9]], i64 0
2679 // CHECK17-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[S_ADDR]], align 8
2680 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP0]], align 4
2681 // CHECK17-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8
2682 // CHECK17-NEXT:    call void @_ZN2St7St_funcEPS_iPe(ptr nonnull align 4 dereferenceable(8) [[ARRAYIDX]], ptr [[TMP10]], i32 [[TMP11]], ptr [[TMP12]])
2683 // CHECK17-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
2684 // CHECK17-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP13]])
2685 // CHECK17-NEXT:    ret void
2686 //
2687 //
2688 // CHECK17-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe
2689 // CHECK17-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr [[S:%.*]], i32 [[N:%.*]], ptr [[VLA1:%.*]]) #[[ATTR0]] align 2 {
2690 // CHECK17-NEXT:  entry:
2691 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2692 // CHECK17-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
2693 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2694 // CHECK17-NEXT:    [[VLA1_ADDR:%.*]] = alloca ptr, align 8
2695 // CHECK17-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
2696 // CHECK17-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
2697 // CHECK17-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
2698 // CHECK17-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2699 // CHECK17-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
2700 // CHECK17-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
2701 // CHECK17-NEXT:    store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8
2702 // CHECK17-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2703 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
2704 // CHECK17-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
2705 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
2706 // CHECK17-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
2707 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
2708 // CHECK17-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
2709 // CHECK17-NEXT:    [[TMP6:%.*]] = call ptr @llvm.stacksave.p0()
2710 // CHECK17-NEXT:    store ptr [[TMP6]], ptr [[SAVED_STACK]], align 8
2711 // CHECK17-NEXT:    [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]]
2712 // CHECK17-NEXT:    [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128
2713 // CHECK17-NEXT:    store i64 [[TMP3]], ptr [[__VLA_EXPR0]], align 8
2714 // CHECK17-NEXT:    store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8
2715 // CHECK17-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 1
2716 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, ptr [[B]], align 4
2717 // CHECK17-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0
2718 // CHECK17-NEXT:    store i32 [[TMP8]], ptr [[A]], align 4
2719 // CHECK17-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8
2720 // CHECK17-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[S_ADDR]], align 8
2721 // CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 8, ptr @_ZN2St7St_funcEPS_iPe.omp_outlined, i64 [[TMP1]], ptr [[TMP9]], ptr [[THIS1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[VLA]], ptr [[N_ADDR]], ptr [[TMP10]])
2722 // CHECK17-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
2723 // CHECK17-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP11]])
2724 // CHECK17-NEXT:    ret void
2725 //
2726 //
2727 // CHECK17-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe.omp_outlined
2728 // CHECK17-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], ptr [[VLA1:%.*]], ptr [[THIS:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], ptr nonnull align 8 dereferenceable(8) [[VLA26:%.*]], ptr nonnull align 4 dereferenceable(4) [[N:%.*]], ptr [[S:%.*]]) #[[ATTR2]] {
2729 // CHECK17-NEXT:  entry:
2730 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2731 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2732 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
2733 // CHECK17-NEXT:    [[VLA1_ADDR:%.*]] = alloca ptr, align 8
2734 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2735 // CHECK17-NEXT:    [[VLA_ADDR3:%.*]] = alloca i64, align 8
2736 // CHECK17-NEXT:    [[VLA_ADDR5:%.*]] = alloca i64, align 8
2737 // CHECK17-NEXT:    [[VLA2_ADDR:%.*]] = alloca ptr, align 8
2738 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca ptr, align 8
2739 // CHECK17-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
2740 // CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2741 // CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2742 // CHECK17-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
2743 // CHECK17-NEXT:    store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8
2744 // CHECK17-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2745 // CHECK17-NEXT:    store i64 [[VLA2]], ptr [[VLA_ADDR3]], align 8
2746 // CHECK17-NEXT:    store i64 [[VLA4]], ptr [[VLA_ADDR5]], align 8
2747 // CHECK17-NEXT:    store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 8
2748 // CHECK17-NEXT:    store ptr [[N]], ptr [[N_ADDR]], align 8
2749 // CHECK17-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
2750 // CHECK17-NEXT:    [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
2751 // CHECK17-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2752 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR3]], align 8
2753 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR5]], align 8
2754 // CHECK17-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 8
2755 // CHECK17-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[N_ADDR]], align 8
2756 // CHECK17-NEXT:    [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]]
2757 // CHECK17-NEXT:    [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 8
2758 // CHECK17-NEXT:    [[TMP8:%.*]] = add nuw i64 [[TMP7]], 127
2759 // CHECK17-NEXT:    [[TMP9:%.*]] = udiv i64 [[TMP8]], 128
2760 // CHECK17-NEXT:    [[TMP10:%.*]] = mul nuw i64 [[TMP9]], 128
2761 // CHECK17-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2762 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
2763 // CHECK17-NEXT:    [[DOTVLA2__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP12]], i64 [[TMP10]], ptr inttoptr (i64 8 to ptr))
2764 // CHECK17-NEXT:    [[TMP13:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]]
2765 // CHECK17-NEXT:    [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8
2766 // CHECK17-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[DOTVLA2__VOID_ADDR]], ptr align 128 [[TMP4]], i64 [[TMP14]], i1 false)
2767 // CHECK17-NEXT:    [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_ST:%.*]], ptr [[TMP1]], i32 0, i32 1
2768 // CHECK17-NEXT:    [[TMP15:%.*]] = load i32, ptr [[B]], align 4
2769 // CHECK17-NEXT:    [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[TMP1]], i32 0, i32 0
2770 // CHECK17-NEXT:    store i32 [[TMP15]], ptr [[A]], align 4
2771 // CHECK17-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP15]] to double
2772 // CHECK17-NEXT:    [[TMP16:%.*]] = mul nsw i64 1, [[TMP3]]
2773 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[DOTVLA2__VOID_ADDR]], i64 [[TMP16]]
2774 // CHECK17-NEXT:    [[TMP17:%.*]] = load i32, ptr [[TMP5]], align 4
2775 // CHECK17-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP17]], 1
2776 // CHECK17-NEXT:    [[IDXPROM:%.*]] = sext i32 [[SUB]] to i64
2777 // CHECK17-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX]], i64 [[IDXPROM]]
2778 // CHECK17-NEXT:    store double [[CONV]], ptr [[ARRAYIDX7]], align 8
2779 // CHECK17-NEXT:    [[CONV8:%.*]] = fpext double [[CONV]] to x86_fp80
2780 // CHECK17-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8
2781 // CHECK17-NEXT:    [[B9:%.*]] = getelementptr inbounds nuw [[STRUCT_ST]], ptr [[TMP1]], i32 0, i32 1
2782 // CHECK17-NEXT:    [[TMP19:%.*]] = load i32, ptr [[B9]], align 4
2783 // CHECK17-NEXT:    [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64
2784 // CHECK17-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds x86_fp80, ptr [[TMP18]], i64 [[IDXPROM10]]
2785 // CHECK17-NEXT:    store x86_fp80 [[CONV8]], ptr [[ARRAYIDX11]], align 16
2786 // CHECK17-NEXT:    call void @__kmpc_free(i32 [[TMP12]], ptr [[DOTVLA2__VOID_ADDR]], ptr inttoptr (i64 8 to ptr))
2787 // CHECK17-NEXT:    ret void
2788 //