[AMDGPU] Mark AGPR tuple implicit in the first instr of AGPR spills. (#115285)
[llvm-project.git] / clang / test / SemaHLSL / Semantics / valid_entry_parameter.hlsl
blob6781f9241df2406a99a5141dc7c6acf5da63534b
1 // RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-compute -x hlsl  -finclude-default-header -ast-dump  -o - %s | FileCheck %s
3 [numthreads(8,8,1)]
4 void CSMain(uint ID : SV_DispatchThreadID) {
5 // CHECK: FunctionDecl 0x{{[0-9a-fA-F]+}} <{{.*}}> line:[[@LINE-1]]:6 CSMain 'void (uint)'
6 // CHECK-NEXT: ParmVarDecl 0x{{[0-9a-fA-F]+}} <{{.*}}> col:18 ID 'uint'
7 // CHECK-NEXT: HLSLSV_DispatchThreadIDAttr
9 [numthreads(8,8,1)]
10 void CSMain1(uint2 ID : SV_DispatchThreadID) {
11 // CHECK: FunctionDecl 0x{{[0-9a-fA-F]+}} <{{.*}}> line:[[@LINE-1]]:6 CSMain1 'void (uint2)'
12 // CHECK-NEXT: ParmVarDecl 0x{{[0-9a-fA-F]+}} <{{.*}}> col:20 ID 'uint2'
13 // CHECK-NEXT: HLSLSV_DispatchThreadIDAttr
15 [numthreads(8,8,1)]
16 void CSMain2(uint3 ID : SV_DispatchThreadID) {
17 // CHECK: FunctionDecl 0x{{[0-9a-fA-F]+}} <{{.*}}> line:[[@LINE-1]]:6 CSMain2 'void (uint3)'
18 // CHECK-NEXT: ParmVarDecl 0x{{[0-9a-fA-F]+}} <{{.*}}> col:20 ID 'uint3'
19 // CHECK-NEXT: HLSLSV_DispatchThreadIDAttr
21 [numthreads(8,8,1)]
22 void CSMain3(uint3 : SV_DispatchThreadID) {
23 // CHECK: FunctionDecl 0x{{[0-9a-fA-F]+}} <{{.*}}> line:[[@LINE-1]]:6 CSMain3 'void (uint3)'
24 // CHECK-NEXT: ParmVarDecl 0x{{[0-9a-fA-F]+}} <{{.*}}> col:20 'uint3'
25 // CHECK-NEXT: HLSLSV_DispatchThreadIDAttr
28 [numthreads(8,8,1)]
29 void CSMain_GID(uint ID : SV_GroupID) {
30 // CHECK: FunctionDecl 0x{{[0-9a-fA-F]+}} <{{.*}}> line:[[@LINE-1]]:6 CSMain_GID 'void (uint)'
31 // CHECK-NEXT: ParmVarDecl 0x{{[0-9a-fA-F]+}} <{{.*}}> col:22 ID 'uint'
32 // CHECK-NEXT: HLSLSV_GroupIDAttr
34 [numthreads(8,8,1)]
35 void CSMain1_GID(uint2 ID : SV_GroupID) {
36 // CHECK: FunctionDecl 0x{{[0-9a-fA-F]+}} <{{.*}}> line:[[@LINE-1]]:6 CSMain1_GID 'void (uint2)'
37 // CHECK-NEXT: ParmVarDecl 0x{{[0-9a-fA-F]+}} <{{.*}}> col:24 ID 'uint2'
38 // CHECK-NEXT: HLSLSV_GroupIDAttr
40 [numthreads(8,8,1)]
41 void CSMain2_GID(uint3 ID : SV_GroupID) {
42 // CHECK: FunctionDecl 0x{{[0-9a-fA-F]+}} <{{.*}}> line:[[@LINE-1]]:6 CSMain2_GID 'void (uint3)'
43 // CHECK-NEXT: ParmVarDecl 0x{{[0-9a-fA-F]+}} <{{.*}}> col:24 ID 'uint3'
44 // CHECK-NEXT: HLSLSV_GroupIDAttr
46 [numthreads(8,8,1)]
47 void CSMain3_GID(uint3 : SV_GroupID) {
48 // CHECK: FunctionDecl 0x{{[0-9a-fA-F]+}} <{{.*}}> line:[[@LINE-1]]:6 CSMain3_GID 'void (uint3)'
49 // CHECK-NEXT: ParmVarDecl 0x{{[0-9a-fA-F]+}} <{{.*}}> col:24 'uint3'
50 // CHECK-NEXT: HLSLSV_GroupIDAttr
53 [numthreads(8,8,1)]
54 void CSMain_GThreadID(uint ID : SV_GroupThreadID) {
55 // CHECK: FunctionDecl 0x{{[0-9a-fA-F]+}} <{{.*}}> line:[[@LINE-1]]:6 CSMain_GThreadID 'void (uint)'
56 // CHECK-NEXT: ParmVarDecl 0x{{[0-9a-fA-F]+}} <{{.*}}> col:28 ID 'uint'
57 // CHECK-NEXT: HLSLSV_GroupThreadIDAttr
59 [numthreads(8,8,1)]
60 void CSMain1_GThreadID(uint2 ID : SV_GroupThreadID) {
61 // CHECK: FunctionDecl 0x{{[0-9a-fA-F]+}} <{{.*}}> line:[[@LINE-1]]:6 CSMain1_GThreadID 'void (uint2)'
62 // CHECK-NEXT: ParmVarDecl 0x{{[0-9a-fA-F]+}} <{{.*}}> col:30 ID 'uint2'
63 // CHECK-NEXT: HLSLSV_GroupThreadIDAttr
65 [numthreads(8,8,1)]
66 void CSMain2_GThreadID(uint3 ID : SV_GroupThreadID) {
67 // CHECK: FunctionDecl 0x{{[0-9a-fA-F]+}} <{{.*}}> line:[[@LINE-1]]:6 CSMain2_GThreadID 'void (uint3)'
68 // CHECK-NEXT: ParmVarDecl 0x{{[0-9a-fA-F]+}} <{{.*}}> col:30 ID 'uint3'
69 // CHECK-NEXT: HLSLSV_GroupThreadIDAttr
71 [numthreads(8,8,1)]
72 void CSMain3_GThreadID(uint3 : SV_GroupThreadID) {
73 // CHECK: FunctionDecl 0x{{[0-9a-fA-F]+}} <{{.*}}> line:[[@LINE-1]]:6 CSMain3_GThreadID 'void (uint3)'
74 // CHECK-NEXT: ParmVarDecl 0x{{[0-9a-fA-F]+}} <{{.*}}> col:30 'uint3'
75 // CHECK-NEXT: HLSLSV_GroupThreadIDAttr