flang/test/Lower/PowerPC/ppc-mma-outer-product-1.f90

   1 ! RUN: %flang_fc1 -flang-experimental-hlfir -triple powerpc64le-unknown-unknown -target-cpu pwr10 -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR" %s
   2 ! REQUIRES: target=powerpc{{.*}}
   3
   4       subroutine test_pmxvbf16ger2_def()
   5       use, intrinsic :: mma
   6       implicit none
   7       vector(unsigned(1)) vu10, vu11
   8       __vector_quad :: cq
   9       call mma_pmxvbf16ger2(cq, vu10, vu11, 7, 7, 2)
  10       end subroutine test_pmxvbf16ger2_def
  11
  12 !CHECK-LABEL: @test_pmxvbf16ger2_def_
  13 ! LLVMIR:         %[[VAL_0:.*]] = alloca <16 x i8>, i64 1, align 16
  14 ! LLVMIR:         %[[VAL_1:.*]] = alloca <16 x i8>, i64 1, align 16
  15 ! LLVMIR:         %[[VAL_2:.*]] = alloca <512 x i1>, i64 1, align 64
  16 ! LLVMIR:         %[[VAL_3:.*]] = load <16 x i8>, ptr %[[VAL_1]], align 16
  17 ! LLVMIR:         %[[VAL_4:.*]] = load <16 x i8>, ptr %[[VAL_0]], align 16
  18 ! LLVMIR:         %[[VAL_5:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvbf16ger2(<16 x i8> %[[VAL_3]], <16 x i8> %[[VAL_4]], i32 7, i32 7, i32 2)
  19 ! LLVMIR:         store <512 x i1> %[[VAL_5]], ptr %[[VAL_2]], align 64
  20
  21
  22       subroutine test_pmxvbf16ger2_non_def()
  23       use, intrinsic :: mma
  24       implicit none
  25       vector(unsigned(1)) vu10, vu11
  26       __vector_quad :: cq
  27       call mma_pmxvbf16ger2(cq, vu10, vu11, 7_2, 7_1, 2_8)
  28       end subroutine test_pmxvbf16ger2_non_def
  29
  30 !CHECK-LABEL: @test_pmxvbf16ger2_non_def_
  31 ! LLVMIR:         %[[VAL_6:.*]] = alloca <16 x i8>, i64 1, align 16
  32 ! LLVMIR:         %[[VAL_7:.*]] = alloca <16 x i8>, i64 1, align 16
  33 ! LLVMIR:         %[[VAL_8:.*]] = alloca <512 x i1>, i64 1, align 64
  34 ! LLVMIR:         %[[VAL_9:.*]] = load <16 x i8>, ptr %[[VAL_7]], align 16
  35 ! LLVMIR:         %[[VAL_10:.*]] = load <16 x i8>, ptr %[[VAL_6]], align 16
  36 ! LLVMIR:         %[[VAL_11:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvbf16ger2(<16 x i8> %[[VAL_9]], <16 x i8> %[[VAL_10]], i32 7, i32 7, i32 2)
  37 ! LLVMIR:         store <512 x i1> %[[VAL_11]], ptr %[[VAL_8]], align 64
  38
  39
  40       subroutine test_pmxvbf16ger2nn_def()
  41       use, intrinsic :: mma
  42       implicit none
  43       vector(unsigned(1)) vu10, vu11
  44       __vector_quad :: cq
  45       call mma_pmxvbf16ger2nn(cq, vu10, vu11, 7, 7, 2)
  46       end subroutine test_pmxvbf16ger2nn_def
  47
  48 !CHECK-LABEL: @test_pmxvbf16ger2nn_def_
  49 ! LLVMIR:         %[[VAL_12:.*]] = alloca <16 x i8>, i64 1, align 16
  50 ! LLVMIR:         %[[VAL_13:.*]] = alloca <16 x i8>, i64 1, align 16
  51 ! LLVMIR:         %[[VAL_14:.*]] = alloca <512 x i1>, i64 1, align 64
  52 ! LLVMIR:         %[[VAL_15:.*]] = load <16 x i8>, ptr %[[VAL_13]], align 16
  53 ! LLVMIR:         %[[VAL_16:.*]] = load <16 x i8>, ptr %[[VAL_12]], align 16
  54 ! LLVMIR:         %[[VAL_17:.*]] = load <512 x i1>, ptr %[[VAL_14]], align 64
  55 ! LLVMIR:         %[[VAL_18:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvbf16ger2nn(<512 x i1> %[[VAL_17]], <16 x i8> %[[VAL_15]], <16 x i8> %[[VAL_16]], i32 7, i32 7, i32 2)
  56 ! LLVMIR:         store <512 x i1> %[[VAL_18]], ptr %[[VAL_14]], align 64
  57
  58       subroutine test_pmxvbf16ger2nn_non_def()
  59       use, intrinsic :: mma
  60       implicit none
  61       vector(unsigned(1)) vu10, vu11
  62       __vector_quad :: cq
  63       call mma_pmxvbf16ger2nn(cq, vu10, vu11, 7_2, 7_1, 2_8)
  64       end subroutine test_pmxvbf16ger2nn_non_def
  65
  66 !CHECK-LABEL: @test_pmxvbf16ger2nn_non_def_
  67 ! LLVMIR:         %[[VAL_19:.*]] = alloca <16 x i8>, i64 1, align 16
  68 ! LLVMIR:         %[[VAL_20:.*]] = alloca <16 x i8>, i64 1, align 16
  69 ! LLVMIR:         %[[VAL_21:.*]] = alloca <512 x i1>, i64 1, align 64
  70 ! LLVMIR:         %[[VAL_22:.*]] = load <16 x i8>, ptr %[[VAL_20]], align 16
  71 ! LLVMIR:         %[[VAL_23:.*]] = load <16 x i8>, ptr %[[VAL_19]], align 16
  72 ! LLVMIR:         %[[VAL_24:.*]] = load <512 x i1>, ptr %[[VAL_21]], align 64
  73 ! LLVMIR:         %[[VAL_25:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvbf16ger2nn(<512 x i1> %[[VAL_24]], <16 x i8> %[[VAL_22]], <16 x i8> %[[VAL_23]], i32 7, i32 7, i32 2)
  74 ! LLVMIR:         store <512 x i1> %[[VAL_25]], ptr %[[VAL_21]], align 64
  75
  76       subroutine test_pmxvbf16ger2np_def()
  77       use, intrinsic :: mma
  78       implicit none
  79       vector(unsigned(1)) vu10, vu11
  80       __vector_quad :: cq
  81       call mma_pmxvbf16ger2np(cq, vu10, vu11, 7, 7, 2)
  82       end subroutine test_pmxvbf16ger2np_def
  83
  84 !CHECK-LABEL: @test_pmxvbf16ger2np_def_
  85 ! LLVMIR:         %[[VAL_26:.*]] = alloca <16 x i8>, i64 1, align 16
  86 ! LLVMIR:         %[[VAL_27:.*]] = alloca <16 x i8>, i64 1, align 16
  87 ! LLVMIR:         %[[VAL_28:.*]] = alloca <512 x i1>, i64 1, align 64
  88 ! LLVMIR:         %[[VAL_29:.*]] = load <16 x i8>, ptr %[[VAL_27]], align 16
  89 ! LLVMIR:         %[[VAL_30:.*]] = load <16 x i8>, ptr %[[VAL_26]], align 16
  90 ! LLVMIR:         %[[VAL_31:.*]] = load <512 x i1>, ptr %[[VAL_28]], align 64
  91 ! LLVMIR:         %[[VAL_32:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvbf16ger2np(<512 x i1> %[[VAL_31]], <16 x i8> %[[VAL_29]], <16 x i8> %[[VAL_30]], i32 7, i32 7, i32 2)
  92 ! LLVMIR:         store <512 x i1> %[[VAL_32]], ptr %[[VAL_28]], align 64
  93
  94       subroutine test_pmxvbf16ger2np_non_def()
  95       use, intrinsic :: mma
  96       implicit none
  97       vector(unsigned(1)) vu10, vu11
  98       __vector_quad :: cq
  99       call mma_pmxvbf16ger2np(cq, vu10, vu11, 7_2, 7_1, 2_8)
 100       end subroutine test_pmxvbf16ger2np_non_def
 101
 102 !CHECK-LABEL: @test_pmxvbf16ger2np_non_def_
 103 ! LLVMIR:         %[[VAL_33:.*]] = alloca <16 x i8>, i64 1, align 16
 104 ! LLVMIR:         %[[VAL_34:.*]] = alloca <16 x i8>, i64 1, align 16
 105 ! LLVMIR:         %[[VAL_35:.*]] = alloca <512 x i1>, i64 1, align 64
 106 ! LLVMIR:         %[[VAL_36:.*]] = load <16 x i8>, ptr %[[VAL_34]], align 16
 107 ! LLVMIR:         %[[VAL_37:.*]] = load <16 x i8>, ptr %[[VAL_33]], align 16
 108 ! LLVMIR:         %[[VAL_38:.*]] = load <512 x i1>, ptr %[[VAL_35]], align 64
 109 ! LLVMIR:         %[[VAL_39:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvbf16ger2np(<512 x i1> %[[VAL_38]], <16 x i8> %[[VAL_36]], <16 x i8> %[[VAL_37]], i32 7, i32 7, i32 2)
 110 ! LLVMIR:         store <512 x i1> %[[VAL_39]], ptr %[[VAL_35]], align 64
 111
 112       subroutine test_pmxvbf16ger2pn_def()
 113       use, intrinsic :: mma
 114       implicit none
 115       vector(unsigned(1)) vu10, vu11
 116       __vector_quad :: cq
 117       call mma_pmxvbf16ger2pn(cq, vu10, vu11, 7, 7, 2)
 118       end subroutine test_pmxvbf16ger2pn_def
 119
 120 !CHECK-LABEL: @test_pmxvbf16ger2pn_def_
 121 ! LLVMIR:         %[[VAL_40:.*]] = alloca <16 x i8>, i64 1, align 16
 122 ! LLVMIR:         %[[VAL_41:.*]] = alloca <16 x i8>, i64 1, align 16
 123 ! LLVMIR:         %[[VAL_42:.*]] = alloca <512 x i1>, i64 1, align 64
 124 ! LLVMIR:         %[[VAL_43:.*]] = load <16 x i8>, ptr %[[VAL_41]], align 16
 125 ! LLVMIR:         %[[VAL_44:.*]] = load <16 x i8>, ptr %[[VAL_40]], align 16
 126 ! LLVMIR:         %[[VAL_45:.*]] = load <512 x i1>, ptr %[[VAL_42]], align 64
 127 ! LLVMIR:         %[[VAL_46:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvbf16ger2pn(<512 x i1> %[[VAL_45]], <16 x i8> %[[VAL_43]], <16 x i8> %[[VAL_44]], i32 7, i32 7, i32 2)
 128 ! LLVMIR:         store <512 x i1> %[[VAL_46]], ptr %[[VAL_42]], align 64
 129
 130       subroutine test_pmxvbf16ger2pn_non_def()
 131       use, intrinsic :: mma
 132       implicit none
 133       vector(unsigned(1)) vu10, vu11
 134       __vector_quad :: cq
 135       call mma_pmxvbf16ger2pn(cq, vu10, vu11, 7_2, 7_1, 2_8)
 136       end subroutine test_pmxvbf16ger2pn_non_def
 137
 138 !CHECK-LABEL: @test_pmxvbf16ger2pn_non_def_
 139 ! LLVMIR:         %[[VAL_47:.*]] = alloca <16 x i8>, i64 1, align 16
 140 ! LLVMIR:         %[[VAL_48:.*]] = alloca <16 x i8>, i64 1, align 16
 141 ! LLVMIR:         %[[VAL_49:.*]] = alloca <512 x i1>, i64 1, align 64
 142 ! LLVMIR:         %[[VAL_50:.*]] = load <16 x i8>, ptr %[[VAL_48]], align 16
 143 ! LLVMIR:         %[[VAL_51:.*]] = load <16 x i8>, ptr %[[VAL_47]], align 16
 144 ! LLVMIR:         %[[VAL_52:.*]] = load <512 x i1>, ptr %[[VAL_49]], align 64
 145 ! LLVMIR:         %[[VAL_53:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvbf16ger2pn(<512 x i1> %[[VAL_52]], <16 x i8> %[[VAL_50]], <16 x i8> %[[VAL_51]], i32 7, i32 7, i32 2)
 146 ! LLVMIR:         store <512 x i1> %[[VAL_53]], ptr %[[VAL_49]], align 64
 147
 148       subroutine test_pmxvbf16ger2pp_def()
 149       use, intrinsic :: mma
 150       implicit none
 151       vector(unsigned(1)) vu10, vu11
 152       __vector_quad :: cq
 153       call mma_pmxvbf16ger2pp(cq, vu10, vu11, 7, 7, 2)
 154       end subroutine test_pmxvbf16ger2pp_def
 155
 156 !CHECK-LABEL: @test_pmxvbf16ger2pp_def_
 157 ! LLVMIR:         %[[VAL_54:.*]] = alloca <16 x i8>, i64 1, align 16
 158 ! LLVMIR:         %[[VAL_55:.*]] = alloca <16 x i8>, i64 1, align 16
 159 ! LLVMIR:         %[[VAL_56:.*]] = alloca <512 x i1>, i64 1, align 64
 160 ! LLVMIR:         %[[VAL_57:.*]] = load <16 x i8>, ptr %[[VAL_55]], align 16
 161 ! LLVMIR:         %[[VAL_58:.*]] = load <16 x i8>, ptr %[[VAL_54]], align 16
 162 ! LLVMIR:         %[[VAL_59:.*]] = load <512 x i1>, ptr %[[VAL_56]], align 64
 163 ! LLVMIR:         %[[VAL_60:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvbf16ger2pp(<512 x i1> %[[VAL_59]], <16 x i8> %[[VAL_57]], <16 x i8> %[[VAL_58]], i32 7, i32 7, i32 2)
 164 ! LLVMIR:         store <512 x i1> %[[VAL_60]], ptr %[[VAL_56]], align 64
 165
 166       subroutine test_pmxvbf16ger2pp_non_def()
 167       use, intrinsic :: mma
 168       implicit none
 169       vector(unsigned(1)) vu10, vu11
 170       __vector_quad :: cq
 171       call mma_pmxvbf16ger2pp(cq, vu10, vu11, 7_2, 7_1, 2_8)
 172       end subroutine test_pmxvbf16ger2pp_non_def
 173
 174 !CHECK-LABEL: @test_pmxvbf16ger2pp_non_def_
 175 ! LLVMIR:         %[[VAL_61:.*]] = alloca <16 x i8>, i64 1, align 16
 176 ! LLVMIR:         %[[VAL_62:.*]] = alloca <16 x i8>, i64 1, align 16
 177 ! LLVMIR:         %[[VAL_63:.*]] = alloca <512 x i1>, i64 1, align 64
 178 ! LLVMIR:         %[[VAL_64:.*]] = load <16 x i8>, ptr %[[VAL_62]], align 16
 179 ! LLVMIR:         %[[VAL_65:.*]] = load <16 x i8>, ptr %[[VAL_61]], align 16
 180 ! LLVMIR:         %[[VAL_66:.*]] = load <512 x i1>, ptr %[[VAL_63]], align 64
 181 ! LLVMIR:         %[[VAL_67:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvbf16ger2pp(<512 x i1> %[[VAL_66]], <16 x i8> %[[VAL_64]], <16 x i8> %[[VAL_65]], i32 7, i32 7, i32 2)
 182 ! LLVMIR:         store <512 x i1> %[[VAL_67]], ptr %[[VAL_63]], align 64
 183
 184       subroutine test_pmxvf16ger2_def()
 185       use, intrinsic :: mma
 186       implicit none
 187       vector(unsigned(1)) vu10, vu11
 188       __vector_quad :: cq
 189       call mma_pmxvf16ger2(cq, vu10, vu11, 7, 7, 2)
 190       end subroutine test_pmxvf16ger2_def
 191
 192 !CHECK-LABEL: @test_pmxvf16ger2_def_
 193 ! LLVMIR:         %[[VAL_68:.*]] = alloca <16 x i8>, i64 1, align 16
 194 ! LLVMIR:         %[[VAL_69:.*]] = alloca <16 x i8>, i64 1, align 16
 195 ! LLVMIR:         %[[VAL_70:.*]] = alloca <512 x i1>, i64 1, align 64
 196 ! LLVMIR:         %[[VAL_71:.*]] = load <16 x i8>, ptr %[[VAL_69]], align 16
 197 ! LLVMIR:         %[[VAL_72:.*]] = load <16 x i8>, ptr %[[VAL_68]], align 16
 198 ! LLVMIR:         %[[VAL_73:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf16ger2(<16 x i8> %[[VAL_71]], <16 x i8> %[[VAL_72]], i32 7, i32 7, i32 2)
 199 ! LLVMIR:         store <512 x i1> %[[VAL_73]], ptr %[[VAL_70]], align 64
 200
 201       subroutine test_pmxvf16ger2_non_def()
 202       use, intrinsic :: mma
 203       implicit none
 204       vector(unsigned(1)) vu10, vu11
 205       __vector_quad :: cq
 206       call mma_pmxvf16ger2(cq, vu10, vu11, 7_2, 7_1, 2_8)
 207       end subroutine test_pmxvf16ger2_non_def
 208
 209 !CHECK-LABEL: @test_pmxvf16ger2_non_def_
 210 ! LLVMIR:         %[[VAL_74:.*]] = alloca <16 x i8>, i64 1, align 16
 211 ! LLVMIR:         %[[VAL_75:.*]] = alloca <16 x i8>, i64 1, align 16
 212 ! LLVMIR:         %[[VAL_76:.*]] = alloca <512 x i1>, i64 1, align 64
 213 ! LLVMIR:         %[[VAL_77:.*]] = load <16 x i8>, ptr %[[VAL_75]], align 16
 214 ! LLVMIR:         %[[VAL_78:.*]] = load <16 x i8>, ptr %[[VAL_74]], align 16
 215 ! LLVMIR:         %[[VAL_79:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf16ger2(<16 x i8> %[[VAL_77]], <16 x i8> %[[VAL_78]], i32 7, i32 7, i32 2)
 216 ! LLVMIR:         store <512 x i1> %[[VAL_79]], ptr %[[VAL_76]], align 64
 217
 218       subroutine test_pmxvf16ger2nn_def()
 219       use, intrinsic :: mma
 220       implicit none
 221       vector(unsigned(1)) vu10, vu11
 222       __vector_quad :: cq
 223       call mma_pmxvf16ger2nn(cq, vu10, vu11, 7, 7, 2)
 224       end subroutine test_pmxvf16ger2nn_def
 225
 226 !CHECK-LABEL: @test_pmxvf16ger2nn_def_
 227 ! LLVMIR:         %[[VAL_80:.*]] = alloca <16 x i8>, i64 1, align 16
 228 ! LLVMIR:         %[[VAL_81:.*]] = alloca <16 x i8>, i64 1, align 16
 229 ! LLVMIR:         %[[VAL_82:.*]] = alloca <512 x i1>, i64 1, align 64
 230 ! LLVMIR:         %[[VAL_83:.*]] = load <16 x i8>, ptr %[[VAL_81]], align 16
 231 ! LLVMIR:         %[[VAL_84:.*]] = load <16 x i8>, ptr %[[VAL_80]], align 16
 232 ! LLVMIR:         %[[VAL_85:.*]] = load <512 x i1>, ptr %[[VAL_82]], align 64
 233 ! LLVMIR:         %[[VAL_86:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf16ger2nn(<512 x i1> %[[VAL_85]], <16 x i8> %[[VAL_83]], <16 x i8> %[[VAL_84]], i32 7, i32 7, i32 2)
 234 ! LLVMIR:         store <512 x i1> %[[VAL_86]], ptr %[[VAL_82]], align 64
 235
 236       subroutine test_pmxvf16ger2nn_non_def()
 237       use, intrinsic :: mma
 238       implicit none
 239       vector(unsigned(1)) vu10, vu11
 240       __vector_quad :: cq
 241       call mma_pmxvf16ger2nn(cq, vu10, vu11, 7_2, 7_1, 2_8)
 242       end subroutine test_pmxvf16ger2nn_non_def
 243
 244 !CHECK-LABEL: @test_pmxvf16ger2nn_non_def_
 245 ! LLVMIR:         %[[VAL_87:.*]] = alloca <16 x i8>, i64 1, align 16
 246 ! LLVMIR:         %[[VAL_88:.*]] = alloca <16 x i8>, i64 1, align 16
 247 ! LLVMIR:         %[[VAL_89:.*]] = alloca <512 x i1>, i64 1, align 64
 248 ! LLVMIR:         %[[VAL_90:.*]] = load <16 x i8>, ptr %[[VAL_88]], align 16
 249 ! LLVMIR:         %[[VAL_91:.*]] = load <16 x i8>, ptr %[[VAL_87]], align 16
 250 ! LLVMIR:         %[[VAL_92:.*]] = load <512 x i1>, ptr %[[VAL_89]], align 64
 251 ! LLVMIR:         %[[VAL_93:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf16ger2nn(<512 x i1> %[[VAL_92]], <16 x i8> %[[VAL_90]], <16 x i8> %[[VAL_91]], i32 7, i32 7, i32 2)
 252 ! LLVMIR:         store <512 x i1> %[[VAL_93]], ptr %[[VAL_89]], align 64
 253
 254       subroutine test_pmxvf16ger2np_def()
 255       use, intrinsic :: mma
 256       implicit none
 257       vector(unsigned(1)) vu10, vu11
 258       __vector_quad :: cq
 259       call mma_pmxvf16ger2np(cq, vu10, vu11, 7, 7, 2)
 260       end subroutine test_pmxvf16ger2np_def
 261
 262 !CHECK-LABEL: @test_pmxvf16ger2np_def_
 263 ! LLVMIR:         %[[VAL_94:.*]] = alloca <16 x i8>, i64 1, align 16
 264 ! LLVMIR:         %[[VAL_95:.*]] = alloca <16 x i8>, i64 1, align 16
 265 ! LLVMIR:         %[[VAL_96:.*]] = alloca <512 x i1>, i64 1, align 64
 266 ! LLVMIR:         %[[VAL_97:.*]] = load <16 x i8>, ptr %[[VAL_95]], align 16
 267 ! LLVMIR:         %[[VAL_98:.*]] = load <16 x i8>, ptr %[[VAL_94]], align 16
 268 ! LLVMIR:         %[[VAL_99:.*]] = load <512 x i1>, ptr %[[VAL_96]], align 64
 269 ! LLVMIR:         %[[VAL_100:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf16ger2np(<512 x i1> %[[VAL_99]], <16 x i8> %[[VAL_97]], <16 x i8> %[[VAL_98]], i32 7, i32 7, i32 2)
 270 ! LLVMIR:         store <512 x i1> %[[VAL_100]], ptr %[[VAL_96]], align 64
 271
 272       subroutine test_pmxvf16ger2np_non_def()
 273       use, intrinsic :: mma
 274       implicit none
 275       vector(unsigned(1)) vu10, vu11
 276       __vector_quad :: cq
 277       call mma_pmxvf16ger2np(cq, vu10, vu11, 7_2, 7_1, 2_8)
 278       end subroutine test_pmxvf16ger2np_non_def
 279
 280 !CHECK-LABEL: @test_pmxvf16ger2np_non_def_
 281 ! LLVMIR:         %[[VAL_101:.*]] = alloca <16 x i8>, i64 1, align 16
 282 ! LLVMIR:         %[[VAL_102:.*]] = alloca <16 x i8>, i64 1, align 16
 283 ! LLVMIR:         %[[VAL_103:.*]] = alloca <512 x i1>, i64 1, align 64
 284 ! LLVMIR:         %[[VAL_104:.*]] = load <16 x i8>, ptr %[[VAL_102]], align 16
 285 ! LLVMIR:         %[[VAL_105:.*]] = load <16 x i8>, ptr %[[VAL_101]], align 16
 286 ! LLVMIR:         %[[VAL_106:.*]] = load <512 x i1>, ptr %[[VAL_103]], align 64
 287 ! LLVMIR:         %[[VAL_107:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf16ger2np(<512 x i1> %[[VAL_106]], <16 x i8> %[[VAL_104]], <16 x i8> %[[VAL_105]], i32 7, i32 7, i32 2)
 288 ! LLVMIR:         store <512 x i1> %[[VAL_107]], ptr %[[VAL_103]], align 64
 289
 290       subroutine test_pmxvf16ger2pn_def()
 291       use, intrinsic :: mma
 292       implicit none
 293       vector(unsigned(1)) vu10, vu11
 294       __vector_quad :: cq
 295       call mma_pmxvf16ger2pn(cq, vu10, vu11, 7, 7, 2)
 296       end subroutine test_pmxvf16ger2pn_def
 297
 298 !CHECK-LABEL: @test_pmxvf16ger2pn_def_
 299 ! LLVMIR:         %[[VAL_108:.*]] = alloca <16 x i8>, i64 1, align 16
 300 ! LLVMIR:         %[[VAL_109:.*]] = alloca <16 x i8>, i64 1, align 16
 301 ! LLVMIR:         %[[VAL_110:.*]] = alloca <512 x i1>, i64 1, align 64
 302 ! LLVMIR:         %[[VAL_111:.*]] = load <16 x i8>, ptr %[[VAL_109]], align 16
 303 ! LLVMIR:         %[[VAL_112:.*]] = load <16 x i8>, ptr %[[VAL_108]], align 16
 304 ! LLVMIR:         %[[VAL_113:.*]] = load <512 x i1>, ptr %[[VAL_110]], align 64
 305 ! LLVMIR:         %[[VAL_114:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf16ger2pn(<512 x i1> %[[VAL_113]], <16 x i8> %[[VAL_111]], <16 x i8> %[[VAL_112]], i32 7, i32 7, i32 2)
 306 ! LLVMIR:         store <512 x i1> %[[VAL_114]], ptr %[[VAL_110]], align 64
 307
 308       subroutine test_pmxvf16ger2pn_non_def()
 309       use, intrinsic :: mma
 310       implicit none
 311       vector(unsigned(1)) vu10, vu11
 312       __vector_quad :: cq
 313       call mma_pmxvf16ger2pn(cq, vu10, vu11, 7_2, 7_1, 2_8)
 314       end subroutine test_pmxvf16ger2pn_non_def
 315
 316 !CHECK-LABEL: @test_pmxvf16ger2pn_non_def_
 317 ! LLVMIR:         %[[VAL_115:.*]] = alloca <16 x i8>, i64 1, align 16
 318 ! LLVMIR:         %[[VAL_116:.*]] = alloca <16 x i8>, i64 1, align 16
 319 ! LLVMIR:         %[[VAL_117:.*]] = alloca <512 x i1>, i64 1, align 64
 320 ! LLVMIR:         %[[VAL_118:.*]] = load <16 x i8>, ptr %[[VAL_116]], align 16
 321 ! LLVMIR:         %[[VAL_119:.*]] = load <16 x i8>, ptr %[[VAL_115]], align 16
 322 ! LLVMIR:         %[[VAL_120:.*]] = load <512 x i1>, ptr %[[VAL_117]], align 64
 323 ! LLVMIR:         %[[VAL_121:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf16ger2pn(<512 x i1> %[[VAL_120]], <16 x i8> %[[VAL_118]], <16 x i8> %[[VAL_119]], i32 7, i32 7, i32 2)
 324 ! LLVMIR:         store <512 x i1> %[[VAL_121]], ptr %[[VAL_117]], align 64
 325
 326       subroutine test_pmxvf16ger2pp_def()
 327       use, intrinsic :: mma
 328       implicit none
 329       vector(unsigned(1)) vu10, vu11
 330       __vector_quad :: cq
 331       call mma_pmxvf16ger2pp(cq, vu10, vu11, 7, 7, 2)
 332       end subroutine test_pmxvf16ger2pp_def
 333
 334 !CHECK-LABEL: @test_pmxvf16ger2pp_def_
 335 ! LLVMIR:         %[[VAL_122:.*]] = alloca <16 x i8>, i64 1, align 16
 336 ! LLVMIR:         %[[VAL_123:.*]] = alloca <16 x i8>, i64 1, align 16
 337 ! LLVMIR:         %[[VAL_124:.*]] = alloca <512 x i1>, i64 1, align 64
 338 ! LLVMIR:         %[[VAL_125:.*]] = load <16 x i8>, ptr %[[VAL_123]], align 16
 339 ! LLVMIR:         %[[VAL_126:.*]] = load <16 x i8>, ptr %[[VAL_122]], align 16
 340 ! LLVMIR:         %[[VAL_127:.*]] = load <512 x i1>, ptr %[[VAL_124]], align 64
 341 ! LLVMIR:         %[[VAL_128:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf16ger2pp(<512 x i1> %[[VAL_127]], <16 x i8> %[[VAL_125]], <16 x i8> %[[VAL_126]], i32 7, i32 7, i32 2)
 342 ! LLVMIR:         store <512 x i1> %[[VAL_128]], ptr %[[VAL_124]], align 64
 343
 344       subroutine test_pmxvf16ger2pp_non_def()
 345       use, intrinsic :: mma
 346       implicit none
 347       vector(unsigned(1)) vu10, vu11
 348       __vector_quad :: cq
 349       call mma_pmxvf16ger2pp(cq, vu10, vu11, 7_2, 7_1, 2_8)
 350       end subroutine test_pmxvf16ger2pp_non_def
 351
 352 !CHECK-LABEL: @test_pmxvf16ger2pp_non_def_
 353 ! LLVMIR:         %[[VAL_129:.*]] = alloca <16 x i8>, i64 1, align 16
 354 ! LLVMIR:         %[[VAL_130:.*]] = alloca <16 x i8>, i64 1, align 16
 355 ! LLVMIR:         %[[VAL_131:.*]] = alloca <512 x i1>, i64 1, align 64
 356 ! LLVMIR:         %[[VAL_132:.*]] = load <16 x i8>, ptr %[[VAL_130]], align 16
 357 ! LLVMIR:         %[[VAL_133:.*]] = load <16 x i8>, ptr %[[VAL_129]], align 16
 358 ! LLVMIR:         %[[VAL_134:.*]] = load <512 x i1>, ptr %[[VAL_131]], align 64
 359 ! LLVMIR:         %[[VAL_135:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf16ger2pp(<512 x i1> %[[VAL_134]], <16 x i8> %[[VAL_132]], <16 x i8> %[[VAL_133]], i32 7, i32 7, i32 2)
 360 ! LLVMIR:         store <512 x i1> %[[VAL_135]], ptr %[[VAL_131]], align 64
 361
 362       subroutine test_pmxvf32ger_u1_def()
 363       use, intrinsic :: mma
 364       implicit none
 365       vector(unsigned(1)) vu10, vu11
 366       __vector_quad :: cq
 367       call mma_pmxvf32ger(cq, vu10, vu11, 7, 2)
 368       end subroutine test_pmxvf32ger_u1_def
 369
 370 !CHECK-LABEL: @test_pmxvf32ger_u1_def_
 371 ! LLVMIR:         %[[VAL_136:.*]] = alloca <16 x i8>, i64 1, align 16
 372 ! LLVMIR:         %[[VAL_137:.*]] = alloca <16 x i8>, i64 1, align 16
 373 ! LLVMIR:         %[[VAL_138:.*]] = alloca <512 x i1>, i64 1, align 64
 374 ! LLVMIR:         %[[VAL_139:.*]] = load <16 x i8>, ptr %[[VAL_137]], align 16
 375 ! LLVMIR:         %[[VAL_140:.*]] = load <16 x i8>, ptr %[[VAL_136]], align 16
 376 ! LLVMIR:         %[[VAL_141:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf32ger(<16 x i8> %[[VAL_139]], <16 x i8> %[[VAL_140]], i32 7, i32 2)
 377 ! LLVMIR:         store <512 x i1> %[[VAL_141]], ptr %[[VAL_138]], align 64
 378
 379       subroutine test_pmxvf32ger_u1_non_def()
 380       use, intrinsic :: mma
 381       implicit none
 382       vector(unsigned(1)) vu10, vu11
 383       __vector_quad :: cq
 384       call mma_pmxvf32ger(cq, vu10, vu11, 7_2, 2_1)
 385       end subroutine test_pmxvf32ger_u1_non_def
 386
 387 !CHECK-LABEL: @test_pmxvf32ger_u1_non_def_
 388 ! LLVMIR:         %[[VAL_142:.*]] = alloca <16 x i8>, i64 1, align 16
 389 ! LLVMIR:         %[[VAL_143:.*]] = alloca <16 x i8>, i64 1, align 16
 390 ! LLVMIR:         %[[VAL_144:.*]] = alloca <512 x i1>, i64 1, align 64
 391 ! LLVMIR:         %[[VAL_145:.*]] = load <16 x i8>, ptr %[[VAL_143]], align 16
 392 ! LLVMIR:         %[[VAL_146:.*]] = load <16 x i8>, ptr %[[VAL_142]], align 16
 393 ! LLVMIR:         %[[VAL_147:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf32ger(<16 x i8> %[[VAL_145]], <16 x i8> %[[VAL_146]], i32 7, i32 2)
 394 ! LLVMIR:         store <512 x i1> %[[VAL_147]], ptr %[[VAL_144]], align 64
 395
 396       subroutine test_pmxvf32ger_r4_def()
 397       use, intrinsic :: mma
 398       implicit none
 399       vector(real(4)) vr40, vr41
 400       __vector_quad :: cq
 401       call mma_pmxvf32ger(cq, vr40, vr41, 7, 2)
 402       end subroutine test_pmxvf32ger_r4_def
 403
 404 !CHECK-LABEL: @test_pmxvf32ger_r4_def_
 405 ! LLVMIR:         %[[VAL_148:.*]] = alloca <4 x float>, i64 1, align 16
 406 ! LLVMIR:         %[[VAL_149:.*]] = alloca <4 x float>, i64 1, align 16
 407 ! LLVMIR:         %[[VAL_150:.*]] = alloca <512 x i1>, i64 1, align 64
 408 ! LLVMIR:         %[[VAL_151:.*]] = load <4 x float>, ptr %[[VAL_149]], align 16
 409 ! LLVMIR:         %[[VAL_152:.*]] = load <4 x float>, ptr %[[VAL_148]], align 16
 410 ! LLVMIR:         %[[VAL_153:.*]] = bitcast <4 x float> %[[VAL_151]] to <16 x i8>
 411 ! LLVMIR:         %[[VAL_154:.*]] = bitcast <4 x float> %[[VAL_152]] to <16 x i8>
 412 ! LLVMIR:         %[[VAL_155:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf32ger(<16 x i8> %[[VAL_153]], <16 x i8> %[[VAL_154]], i32 7, i32 2)
 413 ! LLVMIR:         store <512 x i1> %[[VAL_155]], ptr %[[VAL_150]], align 64
 414
 415       subroutine test_pmxvf32ger_r4_non_def()
 416       use, intrinsic :: mma
 417       implicit none
 418       vector(real(4)) vr40, vr41
 419       __vector_quad :: cq
 420       call mma_pmxvf32ger(cq, vr40, vr41, 7_2, 2_1)
 421       end subroutine test_pmxvf32ger_r4_non_def
 422
 423 !CHECK-LABEL: @test_pmxvf32ger_r4_non_def_
 424 ! LLVMIR:         %[[VAL_156:.*]] = alloca <4 x float>, i64 1, align 16
 425 ! LLVMIR:         %[[VAL_157:.*]] = alloca <4 x float>, i64 1, align 16
 426 ! LLVMIR:         %[[VAL_158:.*]] = alloca <512 x i1>, i64 1, align 64
 427 ! LLVMIR:         %[[VAL_159:.*]] = load <4 x float>, ptr %[[VAL_157]], align 16
 428 ! LLVMIR:         %[[VAL_160:.*]] = load <4 x float>, ptr %[[VAL_156]], align 16
 429 ! LLVMIR:         %[[VAL_161:.*]] = bitcast <4 x float> %[[VAL_159]] to <16 x i8>
 430 ! LLVMIR:         %[[VAL_162:.*]] = bitcast <4 x float> %[[VAL_160]] to <16 x i8>
 431 ! LLVMIR:         %[[VAL_163:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf32ger(<16 x i8> %[[VAL_161]], <16 x i8> %[[VAL_162]], i32 7, i32 2)
 432 ! LLVMIR:         store <512 x i1> %[[VAL_163]], ptr %[[VAL_158]], align 64
 433
 434       subroutine test_pmxvf32gernn_u1_def()
 435       use, intrinsic :: mma
 436       implicit none
 437       vector(unsigned(1)) vu10, vu11
 438       __vector_quad :: cq
 439       call mma_pmxvf32gernn(cq, vu10, vu11, 7, 2)
 440       end subroutine test_pmxvf32gernn_u1_def
 441
 442 !CHECK-LABEL: @test_pmxvf32gernn_u1_def_
 443 ! LLVMIR:         %[[VAL_164:.*]] = alloca <16 x i8>, i64 1, align 16
 444 ! LLVMIR:         %[[VAL_165:.*]] = alloca <16 x i8>, i64 1, align 16
 445 ! LLVMIR:         %[[VAL_166:.*]] = alloca <512 x i1>, i64 1, align 64
 446 ! LLVMIR:         %[[VAL_167:.*]] = load <16 x i8>, ptr %[[VAL_165]], align 16
 447 ! LLVMIR:         %[[VAL_168:.*]] = load <16 x i8>, ptr %[[VAL_164]], align 16
 448 ! LLVMIR:         %[[VAL_169:.*]] = load <512 x i1>, ptr %[[VAL_166]], align 64
 449 ! LLVMIR:         %[[VAL_170:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf32gernn(<512 x i1> %[[VAL_169]], <16 x i8> %[[VAL_167]], <16 x i8> %[[VAL_168]], i32 7, i32 2)
 450 ! LLVMIR:         store <512 x i1> %[[VAL_170]], ptr %[[VAL_166]], align 64
 451
 452       subroutine test_pmxvf32gernn_u1_non_def()
 453       use, intrinsic :: mma
 454       implicit none
 455       vector(unsigned(1)) vu10, vu11
 456       __vector_quad :: cq
 457       call mma_pmxvf32gernn(cq, vu10, vu11, 7_2, 2_1)
 458       end subroutine test_pmxvf32gernn_u1_non_def
 459
 460 !CHECK-LABEL: @test_pmxvf32gernn_u1_non_def_
 461 ! LLVMIR:         %[[VAL_171:.*]] = alloca <16 x i8>, i64 1, align 16
 462 ! LLVMIR:         %[[VAL_172:.*]] = alloca <16 x i8>, i64 1, align 16
 463 ! LLVMIR:         %[[VAL_173:.*]] = alloca <512 x i1>, i64 1, align 64
 464 ! LLVMIR:         %[[VAL_174:.*]] = load <16 x i8>, ptr %[[VAL_172]], align 16
 465 ! LLVMIR:         %[[VAL_175:.*]] = load <16 x i8>, ptr %[[VAL_171]], align 16
 466 ! LLVMIR:         %[[VAL_176:.*]] = load <512 x i1>, ptr %[[VAL_173]], align 64
 467 ! LLVMIR:         %[[VAL_177:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf32gernn(<512 x i1> %[[VAL_176]], <16 x i8> %[[VAL_174]], <16 x i8> %[[VAL_175]], i32 7, i32 2)
 468 ! LLVMIR:         store <512 x i1> %[[VAL_177]], ptr %[[VAL_173]], align 64
 469
 470       subroutine test_pmxvf32gernn_r4_def()
 471       use, intrinsic :: mma
 472       implicit none
 473       vector(real(4)) vr40, vr41
 474       __vector_quad :: cq
 475       call mma_pmxvf32gernn(cq, vr40, vr41, 7, 2)
 476       end subroutine test_pmxvf32gernn_r4_def
 477
 478 !CHECK-LABEL: @test_pmxvf32gernn_r4_def_
 479 ! LLVMIR:         %[[VAL_178:.*]] = alloca <4 x float>, i64 1, align 16
 480 ! LLVMIR:         %[[VAL_179:.*]] = alloca <4 x float>, i64 1, align 16
 481 ! LLVMIR:         %[[VAL_180:.*]] = alloca <512 x i1>, i64 1, align 64
 482 ! LLVMIR:         %[[VAL_181:.*]] = load <4 x float>, ptr %[[VAL_179]], align 16
 483 ! LLVMIR:         %[[VAL_182:.*]] = load <4 x float>, ptr %[[VAL_178]], align 16
 484 ! LLVMIR:         %[[VAL_183:.*]] = load <512 x i1>, ptr %[[VAL_180]], align 64
 485 ! LLVMIR:         %[[VAL_184:.*]] = bitcast <4 x float> %[[VAL_181]] to <16 x i8>
 486 ! LLVMIR:         %[[VAL_185:.*]] = bitcast <4 x float> %[[VAL_182]] to <16 x i8>
 487 ! LLVMIR:         %[[VAL_186:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf32gernn(<512 x i1> %[[VAL_183]], <16 x i8> %[[VAL_184]], <16 x i8> %[[VAL_185]], i32 7, i32 2)
 488 ! LLVMIR:         store <512 x i1> %[[VAL_186]], ptr %[[VAL_180]], align 64
 489
 490       subroutine test_pmxvf32gernn_r4_non_def()
 491       use, intrinsic :: mma
 492       implicit none
 493       vector(real(4)) vr40, vr41
 494       __vector_quad :: cq
 495       call mma_pmxvf32gernn(cq, vr40, vr41, 7_2, 2_1)
 496       end subroutine test_pmxvf32gernn_r4_non_def
 497
 498 !CHECK-LABEL: @test_pmxvf32gernn_r4_non_def_
 499 ! LLVMIR:         %[[VAL_187:.*]] = alloca <4 x float>, i64 1, align 16
 500 ! LLVMIR:         %[[VAL_188:.*]] = alloca <4 x float>, i64 1, align 16
 501 ! LLVMIR:         %[[VAL_189:.*]] = alloca <512 x i1>, i64 1, align 64
 502 ! LLVMIR:         %[[VAL_190:.*]] = load <4 x float>, ptr %[[VAL_188]], align 16
 503 ! LLVMIR:         %[[VAL_191:.*]] = load <4 x float>, ptr %[[VAL_187]], align 16
 504 ! LLVMIR:         %[[VAL_192:.*]] = load <512 x i1>, ptr %[[VAL_189]], align 64
 505 ! LLVMIR:         %[[VAL_193:.*]] = bitcast <4 x float> %[[VAL_190]] to <16 x i8>
 506 ! LLVMIR:         %[[VAL_194:.*]] = bitcast <4 x float> %[[VAL_191]] to <16 x i8>
 507 ! LLVMIR:         %[[VAL_195:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf32gernn(<512 x i1> %[[VAL_192]], <16 x i8> %[[VAL_193]], <16 x i8> %[[VAL_194]], i32 7, i32 2)
 508 ! LLVMIR:         store <512 x i1> %[[VAL_195]], ptr %[[VAL_189]], align 64
 509
 510       subroutine test_pmxvf32gernp_u1_def()
 511       use, intrinsic :: mma
 512       implicit none
 513       vector(unsigned(1)) vu10, vu11
 514       __vector_quad :: cq
 515       call mma_pmxvf32gernp(cq, vu10, vu11, 7, 2)
 516       end subroutine test_pmxvf32gernp_u1_def
 517
 518 !CHECK-LABEL: @test_pmxvf32gernp_u1_def_
 519 ! LLVMIR:         %[[VAL_196:.*]] = alloca <16 x i8>, i64 1, align 16
 520 ! LLVMIR:         %[[VAL_197:.*]] = alloca <16 x i8>, i64 1, align 16
 521 ! LLVMIR:         %[[VAL_198:.*]] = alloca <512 x i1>, i64 1, align 64
 522 ! LLVMIR:         %[[VAL_199:.*]] = load <16 x i8>, ptr %[[VAL_197]], align 16
 523 ! LLVMIR:         %[[VAL_200:.*]] = load <16 x i8>, ptr %[[VAL_196]], align 16
 524 ! LLVMIR:         %[[VAL_201:.*]] = load <512 x i1>, ptr %[[VAL_198]], align 64
 525 ! LLVMIR:         %[[VAL_202:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf32gernp(<512 x i1> %[[VAL_201]], <16 x i8> %[[VAL_199]], <16 x i8> %[[VAL_200]], i32 7, i32 2)
 526 ! LLVMIR:         store <512 x i1> %[[VAL_202]], ptr %[[VAL_198]], align 64
 527
 528       subroutine test_pmxvf32gernp_u1_non_def()
 529       use, intrinsic :: mma
 530       implicit none
 531       vector(unsigned(1)) vu10, vu11
 532       __vector_quad :: cq
 533       call mma_pmxvf32gernp(cq, vu10, vu11, 7_2, 2_1)
 534       end subroutine test_pmxvf32gernp_u1_non_def
 535
 536 !CHECK-LABEL: @test_pmxvf32gernp_u1_non_def_
 537 ! LLVMIR:         %[[VAL_203:.*]] = alloca <16 x i8>, i64 1, align 16
 538 ! LLVMIR:         %[[VAL_204:.*]] = alloca <16 x i8>, i64 1, align 16
 539 ! LLVMIR:         %[[VAL_205:.*]] = alloca <512 x i1>, i64 1, align 64
 540 ! LLVMIR:         %[[VAL_206:.*]] = load <16 x i8>, ptr %[[VAL_204]], align 16
 541 ! LLVMIR:         %[[VAL_207:.*]] = load <16 x i8>, ptr %[[VAL_203]], align 16
 542 ! LLVMIR:         %[[VAL_208:.*]] = load <512 x i1>, ptr %[[VAL_205]], align 64
 543 ! LLVMIR:         %[[VAL_209:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf32gernp(<512 x i1> %[[VAL_208]], <16 x i8> %[[VAL_206]], <16 x i8> %[[VAL_207]], i32 7, i32 2)
 544 ! LLVMIR:         store <512 x i1> %[[VAL_209]], ptr %[[VAL_205]], align 64
 545
 546       subroutine test_pmxvf32gernp_r4_def()
 547       use, intrinsic :: mma
 548       implicit none
 549       vector(real(4)) vr40, vr41
 550       __vector_quad :: cq
 551       call mma_pmxvf32gernp(cq, vr40, vr41, 7, 2)
 552       end subroutine test_pmxvf32gernp_r4_def
 553
 554 !CHECK-LABEL: @test_pmxvf32gernp_r4_def_
 555 ! LLVMIR:         %[[VAL_210:.*]] = alloca <4 x float>, i64 1, align 16
 556 ! LLVMIR:         %[[VAL_211:.*]] = alloca <4 x float>, i64 1, align 16
 557 ! LLVMIR:         %[[VAL_212:.*]] = alloca <512 x i1>, i64 1, align 64
 558 ! LLVMIR:         %[[VAL_213:.*]] = load <4 x float>, ptr %[[VAL_211]], align 16
 559 ! LLVMIR:         %[[VAL_214:.*]] = load <4 x float>, ptr %[[VAL_210]], align 16
 560 ! LLVMIR:         %[[VAL_215:.*]] = load <512 x i1>, ptr %[[VAL_212]], align 64
 561 ! LLVMIR:         %[[VAL_216:.*]] = bitcast <4 x float> %[[VAL_213]] to <16 x i8>
 562 ! LLVMIR:         %[[VAL_217:.*]] = bitcast <4 x float> %[[VAL_214]] to <16 x i8>
 563 ! LLVMIR:         %[[VAL_218:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf32gernp(<512 x i1> %[[VAL_215]], <16 x i8> %[[VAL_216]], <16 x i8> %[[VAL_217]], i32 7, i32 2)
 564 ! LLVMIR:         store <512 x i1> %[[VAL_218]], ptr %[[VAL_212]], align 64
 565
 566       subroutine test_pmxvf32gernp_r4_non_def()
 567       use, intrinsic :: mma
 568       implicit none
 569       vector(real(4)) vr40, vr41
 570       __vector_quad :: cq
 571       call mma_pmxvf32gernp(cq, vr40, vr41, 7_2, 2_1)
 572       end subroutine test_pmxvf32gernp_r4_non_def
 573
 574 !CHECK-LABEL: @test_pmxvf32gernp_r4_non_def_
 575 ! LLVMIR:         %[[VAL_219:.*]] = alloca <4 x float>, i64 1, align 16
 576 ! LLVMIR:         %[[VAL_220:.*]] = alloca <4 x float>, i64 1, align 16
 577 ! LLVMIR:         %[[VAL_221:.*]] = alloca <512 x i1>, i64 1, align 64
 578 ! LLVMIR:         %[[VAL_222:.*]] = load <4 x float>, ptr %[[VAL_220]], align 16
 579 ! LLVMIR:         %[[VAL_223:.*]] = load <4 x float>, ptr %[[VAL_219]], align 16
 580 ! LLVMIR:         %[[VAL_224:.*]] = load <512 x i1>, ptr %[[VAL_221]], align 64
 581 ! LLVMIR:         %[[VAL_225:.*]] = bitcast <4 x float> %[[VAL_222]] to <16 x i8>
 582 ! LLVMIR:         %[[VAL_226:.*]] = bitcast <4 x float> %[[VAL_223]] to <16 x i8>
 583 ! LLVMIR:         %[[VAL_227:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf32gernp(<512 x i1> %[[VAL_224]], <16 x i8> %[[VAL_225]], <16 x i8> %[[VAL_226]], i32 7, i32 2)
 584 ! LLVMIR:         store <512 x i1> %[[VAL_227]], ptr %[[VAL_221]], align 64
 585
 586       subroutine test_pmxvf32gerpn_u1_def()
 587       use, intrinsic :: mma
 588       implicit none
 589       vector(unsigned(1)) vu10, vu11
 590       __vector_quad :: cq
 591       call mma_pmxvf32gerpn(cq, vu10, vu11, 7, 2)
 592       end subroutine test_pmxvf32gerpn_u1_def
 593
 594 !CHECK-LABEL: @test_pmxvf32gerpn_u1_def_
 595 ! LLVMIR:         %[[VAL_228:.*]] = alloca <16 x i8>, i64 1, align 16
 596 ! LLVMIR:         %[[VAL_229:.*]] = alloca <16 x i8>, i64 1, align 16
 597 ! LLVMIR:         %[[VAL_230:.*]] = alloca <512 x i1>, i64 1, align 64
 598 ! LLVMIR:         %[[VAL_231:.*]] = load <16 x i8>, ptr %[[VAL_229]], align 16
 599 ! LLVMIR:         %[[VAL_232:.*]] = load <16 x i8>, ptr %[[VAL_228]], align 16
 600 ! LLVMIR:         %[[VAL_233:.*]] = load <512 x i1>, ptr %[[VAL_230]], align 64
 601 ! LLVMIR:         %[[VAL_234:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf32gerpn(<512 x i1> %[[VAL_233]], <16 x i8> %[[VAL_231]], <16 x i8> %[[VAL_232]], i32 7, i32 2)
 602 ! LLVMIR:         store <512 x i1> %[[VAL_234]], ptr %[[VAL_230]], align 64
 603
 604       subroutine test_pmxvf32gerpn_u1_non_def()
 605       use, intrinsic :: mma
 606       implicit none
 607       vector(unsigned(1)) vu10, vu11
 608       __vector_quad :: cq
 609       call mma_pmxvf32gerpn(cq, vu10, vu11, 7_2, 2_1)
 610       end subroutine test_pmxvf32gerpn_u1_non_def
 611
 612 !CHECK-LABEL: @test_pmxvf32gerpn_u1_non_def_
 613 ! LLVMIR:         %[[VAL_235:.*]] = alloca <16 x i8>, i64 1, align 16
 614 ! LLVMIR:         %[[VAL_236:.*]] = alloca <16 x i8>, i64 1, align 16
 615 ! LLVMIR:         %[[VAL_237:.*]] = alloca <512 x i1>, i64 1, align 64
 616 ! LLVMIR:         %[[VAL_238:.*]] = load <16 x i8>, ptr %[[VAL_236]], align 16
 617 ! LLVMIR:         %[[VAL_239:.*]] = load <16 x i8>, ptr %[[VAL_235]], align 16
 618 ! LLVMIR:         %[[VAL_240:.*]] = load <512 x i1>, ptr %[[VAL_237]], align 64
 619 ! LLVMIR:         %[[VAL_241:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf32gerpn(<512 x i1> %[[VAL_240]], <16 x i8> %[[VAL_238]], <16 x i8> %[[VAL_239]], i32 7, i32 2)
 620 ! LLVMIR:         store <512 x i1> %[[VAL_241]], ptr %[[VAL_237]], align 64
 621
 622       subroutine test_pmxvf32gerpn_r4_def()
 623       use, intrinsic :: mma
 624       implicit none
 625       vector(real(4)) vr40, vr41
 626       __vector_quad :: cq
 627       call mma_pmxvf32gerpn(cq, vr40, vr41, 7, 2)
 628       end subroutine test_pmxvf32gerpn_r4_def
 629
 630 !CHECK-LABEL: @test_pmxvf32gerpn_r4_def_
 631 ! LLVMIR:         %[[VAL_242:.*]] = alloca <4 x float>, i64 1, align 16
 632 ! LLVMIR:         %[[VAL_243:.*]] = alloca <4 x float>, i64 1, align 16
 633 ! LLVMIR:         %[[VAL_244:.*]] = alloca <512 x i1>, i64 1, align 64
 634 ! LLVMIR:         %[[VAL_245:.*]] = load <4 x float>, ptr %[[VAL_243]], align 16
 635 ! LLVMIR:         %[[VAL_246:.*]] = load <4 x float>, ptr %[[VAL_242]], align 16
 636 ! LLVMIR:         %[[VAL_247:.*]] = load <512 x i1>, ptr %[[VAL_244]], align 64
 637 ! LLVMIR:         %[[VAL_248:.*]] = bitcast <4 x float> %[[VAL_245]] to <16 x i8>
 638 ! LLVMIR:         %[[VAL_249:.*]] = bitcast <4 x float> %[[VAL_246]] to <16 x i8>
 639 ! LLVMIR:         %[[VAL_250:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf32gerpn(<512 x i1> %[[VAL_247]], <16 x i8> %[[VAL_248]], <16 x i8> %[[VAL_249]], i32 7, i32 2)
 640 ! LLVMIR:         store <512 x i1> %[[VAL_250]], ptr %[[VAL_244]], align 64
 641
 642       subroutine test_pmxvf32gerpn_r4_non_def()
 643       use, intrinsic :: mma
 644       implicit none
 645       vector(real(4)) vr40, vr41
 646       __vector_quad :: cq
 647       call mma_pmxvf32gerpn(cq, vr40, vr41, 7_2, 2_1)
 648       end subroutine test_pmxvf32gerpn_r4_non_def
 649
 650 !CHECK-LABEL: @test_pmxvf32gerpn_r4_non_def_
 651 ! LLVMIR:         %[[VAL_251:.*]] = alloca <4 x float>, i64 1, align 16
 652 ! LLVMIR:         %[[VAL_252:.*]] = alloca <4 x float>, i64 1, align 16
 653 ! LLVMIR:         %[[VAL_253:.*]] = alloca <512 x i1>, i64 1, align 64
 654 ! LLVMIR:         %[[VAL_254:.*]] = load <4 x float>, ptr %[[VAL_252]], align 16
 655 ! LLVMIR:         %[[VAL_255:.*]] = load <4 x float>, ptr %[[VAL_251]], align 16
 656 ! LLVMIR:         %[[VAL_256:.*]] = load <512 x i1>, ptr %[[VAL_253]], align 64
 657 ! LLVMIR:         %[[VAL_257:.*]] = bitcast <4 x float> %[[VAL_254]] to <16 x i8>
 658 ! LLVMIR:         %[[VAL_258:.*]] = bitcast <4 x float> %[[VAL_255]] to <16 x i8>
 659 ! LLVMIR:         %[[VAL_259:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf32gerpn(<512 x i1> %[[VAL_256]], <16 x i8> %[[VAL_257]], <16 x i8> %[[VAL_258]], i32 7, i32 2)
 660 ! LLVMIR:         store <512 x i1> %[[VAL_259]], ptr %[[VAL_253]], align 64
 661
 662       subroutine test_pmxvf32gerpp_u1_def()
 663       use, intrinsic :: mma
 664       implicit none
 665       vector(unsigned(1)) vu10, vu11
 666       __vector_quad :: cq
 667       call mma_pmxvf32gerpp(cq, vu10, vu11, 7, 2)
 668       end subroutine test_pmxvf32gerpp_u1_def
 669
 670 !CHECK-LABEL: @test_pmxvf32gerpp_u1_def_
 671 ! LLVMIR:         %[[VAL_260:.*]] = alloca <16 x i8>, i64 1, align 16
 672 ! LLVMIR:         %[[VAL_261:.*]] = alloca <16 x i8>, i64 1, align 16
 673 ! LLVMIR:         %[[VAL_262:.*]] = alloca <512 x i1>, i64 1, align 64
 674 ! LLVMIR:         %[[VAL_263:.*]] = load <16 x i8>, ptr %[[VAL_261]], align 16
 675 ! LLVMIR:         %[[VAL_264:.*]] = load <16 x i8>, ptr %[[VAL_260]], align 16
 676 ! LLVMIR:         %[[VAL_265:.*]] = load <512 x i1>, ptr %[[VAL_262]], align 64
 677 ! LLVMIR:         %[[VAL_266:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf32gerpp(<512 x i1> %[[VAL_265]], <16 x i8> %[[VAL_263]], <16 x i8> %[[VAL_264]], i32 7, i32 2)
 678 ! LLVMIR:         store <512 x i1> %[[VAL_266]], ptr %[[VAL_262]], align 64
 679
 680       subroutine test_pmxvf32gerpp_u1_non_def()
 681       use, intrinsic :: mma
 682       implicit none
 683       vector(unsigned(1)) vu10, vu11
 684       __vector_quad :: cq
 685       call mma_pmxvf32gerpp(cq, vu10, vu11, 7_2, 2_1)
 686       end subroutine test_pmxvf32gerpp_u1_non_def
 687
 688 !CHECK-LABEL: @test_pmxvf32gerpp_u1_non_def_
 689 ! LLVMIR:         %[[VAL_267:.*]] = alloca <16 x i8>, i64 1, align 16
 690 ! LLVMIR:         %[[VAL_268:.*]] = alloca <16 x i8>, i64 1, align 16
 691 ! LLVMIR:         %[[VAL_269:.*]] = alloca <512 x i1>, i64 1, align 64
 692 ! LLVMIR:         %[[VAL_270:.*]] = load <16 x i8>, ptr %[[VAL_268]], align 16
 693 ! LLVMIR:         %[[VAL_271:.*]] = load <16 x i8>, ptr %[[VAL_267]], align 16
 694 ! LLVMIR:         %[[VAL_272:.*]] = load <512 x i1>, ptr %[[VAL_269]], align 64
 695 ! LLVMIR:         %[[VAL_273:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf32gerpp(<512 x i1> %[[VAL_272]], <16 x i8> %[[VAL_270]], <16 x i8> %[[VAL_271]], i32 7, i32 2)
 696 ! LLVMIR:         store <512 x i1> %[[VAL_273]], ptr %[[VAL_269]], align 64
 697
 698       subroutine test_pmxvf32gerpp_r4_def()
 699       use, intrinsic :: mma
 700       implicit none
 701       vector(real(4)) vr40, vr41
 702       __vector_quad :: cq
 703       call mma_pmxvf32gerpp(cq, vr40, vr41, 7, 2)
 704       end subroutine test_pmxvf32gerpp_r4_def
 705
 706 !CHECK-LABEL: @test_pmxvf32gerpp_r4_def_
 707 ! LLVMIR:         %[[VAL_274:.*]] = alloca <4 x float>, i64 1, align 16
 708 ! LLVMIR:         %[[VAL_275:.*]] = alloca <4 x float>, i64 1, align 16
 709 ! LLVMIR:         %[[VAL_276:.*]] = alloca <512 x i1>, i64 1, align 64
 710 ! LLVMIR:         %[[VAL_277:.*]] = load <4 x float>, ptr %[[VAL_275]], align 16
 711 ! LLVMIR:         %[[VAL_278:.*]] = load <4 x float>, ptr %[[VAL_274]], align 16
 712 ! LLVMIR:         %[[VAL_279:.*]] = load <512 x i1>, ptr %[[VAL_276]], align 64
 713 ! LLVMIR:         %[[VAL_280:.*]] = bitcast <4 x float> %[[VAL_277]] to <16 x i8>
 714 ! LLVMIR:         %[[VAL_281:.*]] = bitcast <4 x float> %[[VAL_278]] to <16 x i8>
 715 ! LLVMIR:         %[[VAL_282:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf32gerpp(<512 x i1> %[[VAL_279]], <16 x i8> %[[VAL_280]], <16 x i8> %[[VAL_281]], i32 7, i32 2)
 716 ! LLVMIR:         store <512 x i1> %[[VAL_282]], ptr %[[VAL_276]], align 64
 717
 718       subroutine test_pmxvf32gerpp_r4_non_def()
 719       use, intrinsic :: mma
 720       implicit none
 721       vector(real(4)) vr40, vr41
 722       __vector_quad :: cq
 723       call mma_pmxvf32gerpp(cq, vr40, vr41, 7_2, 2_1)
 724       end subroutine test_pmxvf32gerpp_r4_non_def
 725
 726 !CHECK-LABEL: @test_pmxvf32gerpp_r4_non_def_
 727 ! LLVMIR:         %[[VAL_283:.*]] = alloca <4 x float>, i64 1, align 16
 728 ! LLVMIR:         %[[VAL_284:.*]] = alloca <4 x float>, i64 1, align 16
 729 ! LLVMIR:         %[[VAL_285:.*]] = alloca <512 x i1>, i64 1, align 64
 730 ! LLVMIR:         %[[VAL_286:.*]] = load <4 x float>, ptr %[[VAL_284]], align 16
 731 ! LLVMIR:         %[[VAL_287:.*]] = load <4 x float>, ptr %[[VAL_283]], align 16
 732 ! LLVMIR:         %[[VAL_288:.*]] = load <512 x i1>, ptr %[[VAL_285]], align 64
 733 ! LLVMIR:         %[[VAL_289:.*]] = bitcast <4 x float> %[[VAL_286]] to <16 x i8>
 734 ! LLVMIR:         %[[VAL_290:.*]] = bitcast <4 x float> %[[VAL_287]] to <16 x i8>
 735 ! LLVMIR:         %[[VAL_291:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf32gerpp(<512 x i1> %[[VAL_288]], <16 x i8> %[[VAL_289]], <16 x i8> %[[VAL_290]], i32 7, i32 2)
 736 ! LLVMIR:         store <512 x i1> %[[VAL_291]], ptr %[[VAL_285]], align 64
 737
 738       subroutine test_pmxvf64ger_u1_def()
 739       use, intrinsic :: mma
 740       implicit none
 741       vector(unsigned(1)) vu10
 742       __vector_pair :: cp
 743       __vector_quad :: cq
 744       call mma_pmxvf64ger(cq, cp, vu10, 7, 2)
 745       end subroutine test_pmxvf64ger_u1_def
 746
 747 !CHECK-LABEL: @test_pmxvf64ger_u1_def_
 748 ! LLVMIR:         %[[VAL_292:.*]] = alloca <16 x i8>, i64 1, align 16
 749 ! LLVMIR:         %[[VAL_293:.*]] = alloca <512 x i1>, i64 1, align 64
 750 ! LLVMIR:         %[[VAL_294:.*]] = alloca <256 x i1>, i64 1, align 32
 751 ! LLVMIR:         %[[VAL_295:.*]] = load <256 x i1>, ptr %[[VAL_294]], align 32
 752 ! LLVMIR:         %[[VAL_296:.*]] = load <16 x i8>, ptr %[[VAL_292]], align 16
 753 ! LLVMIR:         %[[VAL_297:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf64ger(<256 x i1> %[[VAL_295]], <16 x i8> %[[VAL_296]], i32 7, i32 2)
 754 ! LLVMIR:         store <512 x i1> %[[VAL_297]], ptr %[[VAL_293]], align 64
 755
 756       subroutine test_pmxvf64ger_u1_non_def()
 757       use, intrinsic :: mma
 758       implicit none
 759       vector(unsigned(1)) vu10
 760       __vector_pair :: cp
 761       __vector_quad :: cq
 762       call mma_pmxvf64ger(cq, cp, vu10, 7_2, 2_1)
 763       end subroutine test_pmxvf64ger_u1_non_def
 764
 765 !CHECK-LABEL: @test_pmxvf64ger_u1_non_def_
 766 ! LLVMIR:         %[[VAL_298:.*]] = alloca <16 x i8>, i64 1, align 16
 767 ! LLVMIR:         %[[VAL_299:.*]] = alloca <512 x i1>, i64 1, align 64
 768 ! LLVMIR:         %[[VAL_300:.*]] = alloca <256 x i1>, i64 1, align 32
 769 ! LLVMIR:         %[[VAL_301:.*]] = load <256 x i1>, ptr %[[VAL_300]], align 32
 770 ! LLVMIR:         %[[VAL_302:.*]] = load <16 x i8>, ptr %[[VAL_298]], align 16
 771 ! LLVMIR:         %[[VAL_303:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf64ger(<256 x i1> %[[VAL_301]], <16 x i8> %[[VAL_302]], i32 7, i32 2)
 772 ! LLVMIR:         store <512 x i1> %[[VAL_303]], ptr %[[VAL_299]], align 64
 773
 774       subroutine test_pmxvf64ger_r8_def()
 775       use, intrinsic :: mma
 776       implicit none
 777       vector(real(8)) vr80
 778       __vector_pair :: cp
 779       __vector_quad :: cq
 780       call mma_pmxvf64ger(cq, cp, vr80, 7, 2)
 781       end subroutine test_pmxvf64ger_r8_def
 782
 783 !CHECK-LABEL: @test_pmxvf64ger_r8_def_
 784 ! LLVMIR:         %[[VAL_304:.*]] = alloca <2 x double>, i64 1, align 16
 785 ! LLVMIR:         %[[VAL_305:.*]] = alloca <512 x i1>, i64 1, align 64
 786 ! LLVMIR:         %[[VAL_306:.*]] = alloca <256 x i1>, i64 1, align 32
 787 ! LLVMIR:         %[[VAL_307:.*]] = load <256 x i1>, ptr %[[VAL_306]], align 32
 788 ! LLVMIR:         %[[VAL_308:.*]] = load <2 x double>, ptr %[[VAL_304]], align 16
 789 ! LLVMIR:         %[[VAL_309:.*]] = bitcast <2 x double> %[[VAL_308]] to <16 x i8>
 790 ! LLVMIR:         %[[VAL_310:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf64ger(<256 x i1> %[[VAL_307]], <16 x i8> %[[VAL_309]], i32 7, i32 2)
 791 ! LLVMIR:         store <512 x i1> %[[VAL_310]], ptr %[[VAL_305]], align 64
 792
 793       subroutine test_pmxvf64ger_r8_non_def()
 794       use, intrinsic :: mma
 795       implicit none
 796       vector(real(8)) vr80
 797       __vector_pair :: cp
 798       __vector_quad :: cq
 799       call mma_pmxvf64ger(cq, cp, vr80, 7_2, 2_1)
 800       end subroutine test_pmxvf64ger_r8_non_def
 801
 802 !CHECK-LABEL: @test_pmxvf64ger_r8_non_def_
 803 ! LLVMIR:         %[[VAL_311:.*]] = alloca <2 x double>, i64 1, align 16
 804 ! LLVMIR:         %[[VAL_312:.*]] = alloca <512 x i1>, i64 1, align 64
 805 ! LLVMIR:         %[[VAL_313:.*]] = alloca <256 x i1>, i64 1, align 32
 806 ! LLVMIR:         %[[VAL_314:.*]] = load <256 x i1>, ptr %[[VAL_313]], align 32
 807 ! LLVMIR:         %[[VAL_315:.*]] = load <2 x double>, ptr %[[VAL_311]], align 16
 808 ! LLVMIR:         %[[VAL_316:.*]] = bitcast <2 x double> %[[VAL_315]] to <16 x i8>
 809 ! LLVMIR:         %[[VAL_317:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf64ger(<256 x i1> %[[VAL_314]], <16 x i8> %[[VAL_316]], i32 7, i32 2)
 810 ! LLVMIR:         store <512 x i1> %[[VAL_317]], ptr %[[VAL_312]], align 64
 811
 812       subroutine test_pmxvf64gernn_u1_def()
 813       use, intrinsic :: mma
 814       implicit none
 815       vector(unsigned(1)) vu10
 816       __vector_pair :: cp
 817       __vector_quad :: cq
 818       call mma_pmxvf64gernn(cq, cp, vu10, 7, 2)
 819       end subroutine test_pmxvf64gernn_u1_def
 820
 821 !CHECK-LABEL: @test_pmxvf64gernn_u1_def_
 822 ! LLVMIR:         %[[VAL_318:.*]] = alloca <16 x i8>, i64 1, align 16
 823 ! LLVMIR:         %[[VAL_319:.*]] = alloca <512 x i1>, i64 1, align 64
 824 ! LLVMIR:         %[[VAL_320:.*]] = alloca <256 x i1>, i64 1, align 32
 825 ! LLVMIR:         %[[VAL_321:.*]] = load <256 x i1>, ptr %[[VAL_320]], align 32
 826 ! LLVMIR:         %[[VAL_322:.*]] = load <16 x i8>, ptr %[[VAL_318]], align 16
 827 ! LLVMIR:         %[[VAL_323:.*]] = load <512 x i1>, ptr %[[VAL_319]], align 64
 828 ! LLVMIR:         %[[VAL_324:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> %[[VAL_323]], <256 x i1> %[[VAL_321]], <16 x i8> %[[VAL_322]], i32 7, i32 2)
 829 ! LLVMIR:         store <512 x i1> %[[VAL_324]], ptr %[[VAL_319]], align 64
 830
 831       subroutine test_pmxvf64gernn_u1_non_def()
 832       use, intrinsic :: mma
 833       implicit none
 834       vector(unsigned(1)) vu10
 835       __vector_pair :: cp
 836       __vector_quad :: cq
 837       call mma_pmxvf64gernn(cq, cp, vu10, 7_2, 2_1)
 838       end subroutine test_pmxvf64gernn_u1_non_def
 839
 840 !CHECK-LABEL: @test_pmxvf64gernn_u1_non_def_
 841 ! LLVMIR:         %[[VAL_325:.*]] = alloca <16 x i8>, i64 1, align 16
 842 ! LLVMIR:         %[[VAL_326:.*]] = alloca <512 x i1>, i64 1, align 64
 843 ! LLVMIR:         %[[VAL_327:.*]] = alloca <256 x i1>, i64 1, align 32
 844 ! LLVMIR:         %[[VAL_328:.*]] = load <256 x i1>, ptr %[[VAL_327]], align 32
 845 ! LLVMIR:         %[[VAL_329:.*]] = load <16 x i8>, ptr %[[VAL_325]], align 16
 846 ! LLVMIR:         %[[VAL_330:.*]] = load <512 x i1>, ptr %[[VAL_326]], align 64
 847 ! LLVMIR:         %[[VAL_331:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> %[[VAL_330]], <256 x i1> %[[VAL_328]], <16 x i8> %[[VAL_329]], i32 7, i32 2)
 848 ! LLVMIR:         store <512 x i1> %[[VAL_331]], ptr %[[VAL_326]], align 64
 849
 850       subroutine test_pmxvf64gernn_r8_def()
 851       use, intrinsic :: mma
 852       implicit none
 853       vector(real(8)) vr80
 854       __vector_pair :: cp
 855       __vector_quad :: cq
 856       call mma_pmxvf64gernn(cq, cp, vr80, 7, 2)
 857       end subroutine test_pmxvf64gernn_r8_def
 858
 859 !CHECK-LABEL: @test_pmxvf64gernn_r8_def_
 860 ! LLVMIR:         %[[VAL_332:.*]] = alloca <2 x double>, i64 1, align 16
 861 ! LLVMIR:         %[[VAL_333:.*]] = alloca <512 x i1>, i64 1, align 64
 862 ! LLVMIR:         %[[VAL_334:.*]] = alloca <256 x i1>, i64 1, align 32
 863 ! LLVMIR:         %[[VAL_335:.*]] = load <256 x i1>, ptr %[[VAL_334]], align 32
 864 ! LLVMIR:         %[[VAL_336:.*]] = load <2 x double>, ptr %[[VAL_332]], align 16
 865 ! LLVMIR:         %[[VAL_337:.*]] = load <512 x i1>, ptr %[[VAL_333]], align 64
 866 ! LLVMIR:         %[[VAL_338:.*]] = bitcast <2 x double> %[[VAL_336]] to <16 x i8>
 867 ! LLVMIR:         %[[VAL_339:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> %[[VAL_337]], <256 x i1> %[[VAL_335]], <16 x i8> %[[VAL_338]], i32 7, i32 2)
 868 ! LLVMIR:         store <512 x i1> %[[VAL_339]], ptr %[[VAL_333]], align 64
 869
 870       subroutine test_pmxvf64gernn_r8_non_def()
 871       use, intrinsic :: mma
 872       implicit none
 873       vector(real(8)) vr80
 874       __vector_pair :: cp
 875       __vector_quad :: cq
 876       call mma_pmxvf64gernn(cq, cp, vr80, 7_2, 2_1)
 877       end subroutine test_pmxvf64gernn_r8_non_def
 878
 879 !CHECK-LABEL: @test_pmxvf64gernn_r8_non_def_
 880 ! LLVMIR:         %[[VAL_340:.*]] = alloca <2 x double>, i64 1, align 16
 881 ! LLVMIR:         %[[VAL_341:.*]] = alloca <512 x i1>, i64 1, align 64
 882 ! LLVMIR:         %[[VAL_342:.*]] = alloca <256 x i1>, i64 1, align 32
 883 ! LLVMIR:         %[[VAL_343:.*]] = load <256 x i1>, ptr %[[VAL_342]], align 32
 884 ! LLVMIR:         %[[VAL_344:.*]] = load <2 x double>, ptr %[[VAL_340]], align 16
 885 ! LLVMIR:         %[[VAL_345:.*]] = load <512 x i1>, ptr %[[VAL_341]], align 64
 886 ! LLVMIR:         %[[VAL_346:.*]] = bitcast <2 x double> %[[VAL_344]] to <16 x i8>
 887 ! LLVMIR:         %[[VAL_347:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> %[[VAL_345]], <256 x i1> %[[VAL_343]], <16 x i8> %[[VAL_346]], i32 7, i32 2)
 888 ! LLVMIR:         store <512 x i1> %[[VAL_347]], ptr %[[VAL_341]], align 64
 889
 890       subroutine test_pmxvf64gernp_u1_def()
 891       use, intrinsic :: mma
 892       implicit none
 893       vector(unsigned(1)) vu10
 894       __vector_pair :: cp
 895       __vector_quad :: cq
 896       call mma_pmxvf64gernp(cq, cp, vu10, 7, 2)
 897       end subroutine test_pmxvf64gernp_u1_def
 898
 899 !CHECK-LABEL: @test_pmxvf64gernp_u1_def_
 900 ! LLVMIR:         %[[VAL_348:.*]] = alloca <16 x i8>, i64 1, align 16
 901 ! LLVMIR:         %[[VAL_349:.*]] = alloca <512 x i1>, i64 1, align 64
 902 ! LLVMIR:         %[[VAL_350:.*]] = alloca <256 x i1>, i64 1, align 32
 903 ! LLVMIR:         %[[VAL_351:.*]] = load <256 x i1>, ptr %[[VAL_350]], align 32
 904 ! LLVMIR:         %[[VAL_352:.*]] = load <16 x i8>, ptr %[[VAL_348]], align 16
 905 ! LLVMIR:         %[[VAL_353:.*]] = load <512 x i1>, ptr %[[VAL_349]], align 64
 906 ! LLVMIR:         %[[VAL_354:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf64gernp(<512 x i1> %[[VAL_353]], <256 x i1> %[[VAL_351]], <16 x i8> %[[VAL_352]], i32 7, i32 2)
 907 ! LLVMIR:         store <512 x i1> %[[VAL_354]], ptr %[[VAL_349]], align 64
 908
 909       subroutine test_pmxvf64gernp_u1_non_def()
 910       use, intrinsic :: mma
 911       implicit none
 912       vector(unsigned(1)) vu10
 913       __vector_pair :: cp
 914       __vector_quad :: cq
 915       call mma_pmxvf64gernp(cq, cp, vu10, 7_2, 2_1)
 916       end subroutine test_pmxvf64gernp_u1_non_def
 917
 918 !CHECK-LABEL: @test_pmxvf64gernp_u1_non_def_
 919 ! LLVMIR:         %[[VAL_355:.*]] = alloca <16 x i8>, i64 1, align 16
 920 ! LLVMIR:         %[[VAL_356:.*]] = alloca <512 x i1>, i64 1, align 64
 921 ! LLVMIR:         %[[VAL_357:.*]] = alloca <256 x i1>, i64 1, align 32
 922 ! LLVMIR:         %[[VAL_358:.*]] = load <256 x i1>, ptr %[[VAL_357]], align 32
 923 ! LLVMIR:         %[[VAL_359:.*]] = load <16 x i8>, ptr %[[VAL_355]], align 16
 924 ! LLVMIR:         %[[VAL_360:.*]] = load <512 x i1>, ptr %[[VAL_356]], align 64
 925 ! LLVMIR:         %[[VAL_361:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf64gernp(<512 x i1> %[[VAL_360]], <256 x i1> %[[VAL_358]], <16 x i8> %[[VAL_359]], i32 7, i32 2)
 926 ! LLVMIR:         store <512 x i1> %[[VAL_361]], ptr %[[VAL_356]], align 64
 927
 928       subroutine test_pmxvf64gernp_r8_def()
 929       use, intrinsic :: mma
 930       implicit none
 931       vector(real(8)) vr80
 932       __vector_pair :: cp
 933       __vector_quad :: cq
 934       call mma_pmxvf64gernp(cq, cp, vr80, 7, 2)
 935       end subroutine test_pmxvf64gernp_r8_def
 936
 937 !CHECK-LABEL: @test_pmxvf64gernp_r8_def_
 938 ! LLVMIR:         %[[VAL_362:.*]] = alloca <2 x double>, i64 1, align 16
 939 ! LLVMIR:         %[[VAL_363:.*]] = alloca <512 x i1>, i64 1, align 64
 940 ! LLVMIR:         %[[VAL_364:.*]] = alloca <256 x i1>, i64 1, align 32
 941 ! LLVMIR:         %[[VAL_365:.*]] = load <256 x i1>, ptr %[[VAL_364]], align 32
 942 ! LLVMIR:         %[[VAL_366:.*]] = load <2 x double>, ptr %[[VAL_362]], align 16
 943 ! LLVMIR:         %[[VAL_367:.*]] = load <512 x i1>, ptr %[[VAL_363]], align 64
 944 ! LLVMIR:         %[[VAL_368:.*]] = bitcast <2 x double> %[[VAL_366]] to <16 x i8>
 945 ! LLVMIR:         %[[VAL_369:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf64gernp(<512 x i1> %[[VAL_367]], <256 x i1> %[[VAL_365]], <16 x i8> %[[VAL_368]], i32 7, i32 2)
 946 ! LLVMIR:         store <512 x i1> %[[VAL_369]], ptr %[[VAL_363]], align 64
 947
 948       subroutine test_pmxvf64gernp_r8_non_def()
 949       use, intrinsic :: mma
 950       implicit none
 951       vector(real(8)) vr80
 952       __vector_pair :: cp
 953       __vector_quad :: cq
 954       call mma_pmxvf64gernp(cq, cp, vr80, 7_2, 2_1)
 955       end subroutine test_pmxvf64gernp_r8_non_def
 956
 957 !CHECK-LABEL: @test_pmxvf64gernp_r8_non_def_
 958 ! LLVMIR:         %[[VAL_370:.*]] = alloca <2 x double>, i64 1, align 16
 959 ! LLVMIR:         %[[VAL_371:.*]] = alloca <512 x i1>, i64 1, align 64
 960 ! LLVMIR:         %[[VAL_372:.*]] = alloca <256 x i1>, i64 1, align 32
 961 ! LLVMIR:         %[[VAL_373:.*]] = load <256 x i1>, ptr %[[VAL_372]], align 32
 962 ! LLVMIR:         %[[VAL_374:.*]] = load <2 x double>, ptr %[[VAL_370]], align 16
 963 ! LLVMIR:         %[[VAL_375:.*]] = load <512 x i1>, ptr %[[VAL_371]], align 64
 964 ! LLVMIR:         %[[VAL_376:.*]] = bitcast <2 x double> %[[VAL_374]] to <16 x i8>
 965 ! LLVMIR:         %[[VAL_377:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf64gernp(<512 x i1> %[[VAL_375]], <256 x i1> %[[VAL_373]], <16 x i8> %[[VAL_376]], i32 7, i32 2)
 966 ! LLVMIR:         store <512 x i1> %[[VAL_377]], ptr %[[VAL_371]], align 64
 967
 968       subroutine test_pmxvf64gerpn_u1_def()
 969       use, intrinsic :: mma
 970       implicit none
 971       vector(unsigned(1)) vu10
 972       __vector_pair :: cp
 973       __vector_quad :: cq
 974       call mma_pmxvf64gerpn(cq, cp, vu10, 7, 2)
 975       end subroutine test_pmxvf64gerpn_u1_def
 976
 977 !CHECK-LABEL: @test_pmxvf64gerpn_u1_def_
 978 ! LLVMIR:         %[[VAL_378:.*]] = alloca <16 x i8>, i64 1, align 16
 979 ! LLVMIR:         %[[VAL_379:.*]] = alloca <512 x i1>, i64 1, align 64
 980 ! LLVMIR:         %[[VAL_380:.*]] = alloca <256 x i1>, i64 1, align 32
 981 ! LLVMIR:         %[[VAL_381:.*]] = load <256 x i1>, ptr %[[VAL_380]], align 32
 982 ! LLVMIR:         %[[VAL_382:.*]] = load <16 x i8>, ptr %[[VAL_378]], align 16
 983 ! LLVMIR:         %[[VAL_383:.*]] = load <512 x i1>, ptr %[[VAL_379]], align 64
 984 ! LLVMIR:         %[[VAL_384:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf64gerpn(<512 x i1> %[[VAL_383]], <256 x i1> %[[VAL_381]], <16 x i8> %[[VAL_382]], i32 7, i32 2)
 985 ! LLVMIR:         store <512 x i1> %[[VAL_384]], ptr %[[VAL_379]], align 64
 986
 987       subroutine test_pmxvf64gerpn_u1_non_def()
 988       use, intrinsic :: mma
 989       implicit none
 990       vector(unsigned(1)) vu10
 991       __vector_pair :: cp
 992       __vector_quad :: cq
 993       call mma_pmxvf64gerpn(cq, cp, vu10, 7_2, 2_1)
 994       end subroutine test_pmxvf64gerpn_u1_non_def
 995
 996 !CHECK-LABEL: @test_pmxvf64gerpn_u1_non_def_
 997 ! LLVMIR:         %[[VAL_385:.*]] = alloca <16 x i8>, i64 1, align 16
 998 ! LLVMIR:         %[[VAL_386:.*]] = alloca <512 x i1>, i64 1, align 64
 999 ! LLVMIR:         %[[VAL_387:.*]] = alloca <256 x i1>, i64 1, align 32
1000 ! LLVMIR:         %[[VAL_388:.*]] = load <256 x i1>, ptr %[[VAL_387]], align 32
1001 ! LLVMIR:         %[[VAL_389:.*]] = load <16 x i8>, ptr %[[VAL_385]], align 16
1002 ! LLVMIR:         %[[VAL_390:.*]] = load <512 x i1>, ptr %[[VAL_386]], align 64
1003 ! LLVMIR:         %[[VAL_391:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf64gerpn(<512 x i1> %[[VAL_390]], <256 x i1> %[[VAL_388]], <16 x i8> %[[VAL_389]], i32 7, i32 2)
1004 ! LLVMIR:         store <512 x i1> %[[VAL_391]], ptr %[[VAL_386]], align 64
1005
1006       subroutine test_pmxvf64gerpn_r8_def()
1007       use, intrinsic :: mma
1008       implicit none
1009       vector(real(8)) vr80
1010       __vector_pair :: cp
1011       __vector_quad :: cq
1012       call mma_pmxvf64gerpn(cq, cp, vr80, 7, 2)
1013       end subroutine test_pmxvf64gerpn_r8_def
1014
1015 !CHECK-LABEL: @test_pmxvf64gerpn_r8_def_
1016 ! LLVMIR:         %[[VAL_392:.*]] = alloca <2 x double>, i64 1, align 16
1017 ! LLVMIR:         %[[VAL_393:.*]] = alloca <512 x i1>, i64 1, align 64
1018 ! LLVMIR:         %[[VAL_394:.*]] = alloca <256 x i1>, i64 1, align 32
1019 ! LLVMIR:         %[[VAL_395:.*]] = load <256 x i1>, ptr %[[VAL_394]], align 32
1020 ! LLVMIR:         %[[VAL_396:.*]] = load <2 x double>, ptr %[[VAL_392]], align 16
1021 ! LLVMIR:         %[[VAL_397:.*]] = load <512 x i1>, ptr %[[VAL_393]], align 64
1022 ! LLVMIR:         %[[VAL_398:.*]] = bitcast <2 x double> %[[VAL_396]] to <16 x i8>
1023 ! LLVMIR:         %[[VAL_399:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf64gerpn(<512 x i1> %[[VAL_397]], <256 x i1> %[[VAL_395]], <16 x i8> %[[VAL_398]], i32 7, i32 2)
1024 ! LLVMIR:         store <512 x i1> %[[VAL_399]], ptr %[[VAL_393]], align 64
1025
1026       subroutine test_pmxvf64gerpn_r8_non_def()
1027       use, intrinsic :: mma
1028       implicit none
1029       vector(real(8)) vr80
1030       __vector_pair :: cp
1031       __vector_quad :: cq
1032       call mma_pmxvf64gerpn(cq, cp, vr80, 7_2, 2_1)
1033       end subroutine test_pmxvf64gerpn_r8_non_def
1034
1035 !CHECK-LABEL: @test_pmxvf64gerpn_r8_non_def_
1036 ! LLVMIR:         %[[VAL_400:.*]] = alloca <2 x double>, i64 1, align 16
1037 ! LLVMIR:         %[[VAL_401:.*]] = alloca <512 x i1>, i64 1, align 64
1038 ! LLVMIR:         %[[VAL_402:.*]] = alloca <256 x i1>, i64 1, align 32
1039 ! LLVMIR:         %[[VAL_403:.*]] = load <256 x i1>, ptr %[[VAL_402]], align 32
1040 ! LLVMIR:         %[[VAL_404:.*]] = load <2 x double>, ptr %[[VAL_400]], align 16
1041 ! LLVMIR:         %[[VAL_405:.*]] = load <512 x i1>, ptr %[[VAL_401]], align 64
1042 ! LLVMIR:         %[[VAL_406:.*]] = bitcast <2 x double> %[[VAL_404]] to <16 x i8>
1043 ! LLVMIR:         %[[VAL_407:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf64gerpn(<512 x i1> %[[VAL_405]], <256 x i1> %[[VAL_403]], <16 x i8> %[[VAL_406]], i32 7, i32 2)
1044 ! LLVMIR:         store <512 x i1> %[[VAL_407]], ptr %[[VAL_401]], align 64
1045
1046       subroutine test_pmxvf64gerpp_u1_def()
1047       use, intrinsic :: mma
1048       implicit none
1049       vector(unsigned(1)) vu10
1050       __vector_pair :: cp
1051       __vector_quad :: cq
1052       call mma_pmxvf64gerpp(cq, cp, vu10, 7, 2)
1053       end subroutine test_pmxvf64gerpp_u1_def
1054
1055 !CHECK-LABEL: @test_pmxvf64gerpp_u1_def_
1056 ! LLVMIR:         %[[VAL_408:.*]] = alloca <16 x i8>, i64 1, align 16
1057 ! LLVMIR:         %[[VAL_409:.*]] = alloca <512 x i1>, i64 1, align 64
1058 ! LLVMIR:         %[[VAL_410:.*]] = alloca <256 x i1>, i64 1, align 32
1059 ! LLVMIR:         %[[VAL_411:.*]] = load <256 x i1>, ptr %[[VAL_410]], align 32
1060 ! LLVMIR:         %[[VAL_412:.*]] = load <16 x i8>, ptr %[[VAL_408]], align 16
1061 ! LLVMIR:         %[[VAL_413:.*]] = load <512 x i1>, ptr %[[VAL_409]], align 64
1062 ! LLVMIR:         %[[VAL_414:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf64gerpp(<512 x i1> %[[VAL_413]], <256 x i1> %[[VAL_411]], <16 x i8> %[[VAL_412]], i32 7, i32 2)
1063 ! LLVMIR:         store <512 x i1> %[[VAL_414]], ptr %[[VAL_409]], align 64
1064
1065       subroutine test_pmxvf64gerpp_u1_non_def()
1066       use, intrinsic :: mma
1067       implicit none
1068       vector(unsigned(1)) vu10
1069       __vector_pair :: cp
1070       __vector_quad :: cq
1071       call mma_pmxvf64gerpp(cq, cp, vu10, 7_2, 2_1)
1072       end subroutine test_pmxvf64gerpp_u1_non_def
1073
1074 !CHECK-LABEL: @test_pmxvf64gerpp_u1_non_def_
1075 ! LLVMIR:         %[[VAL_415:.*]] = alloca <16 x i8>, i64 1, align 16
1076 ! LLVMIR:         %[[VAL_416:.*]] = alloca <512 x i1>, i64 1, align 64
1077 ! LLVMIR:         %[[VAL_417:.*]] = alloca <256 x i1>, i64 1, align 32
1078 ! LLVMIR:         %[[VAL_418:.*]] = load <256 x i1>, ptr %[[VAL_417]], align 32
1079 ! LLVMIR:         %[[VAL_419:.*]] = load <16 x i8>, ptr %[[VAL_415]], align 16
1080 ! LLVMIR:         %[[VAL_420:.*]] = load <512 x i1>, ptr %[[VAL_416]], align 64
1081 ! LLVMIR:         %[[VAL_421:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf64gerpp(<512 x i1> %[[VAL_420]], <256 x i1> %[[VAL_418]], <16 x i8> %[[VAL_419]], i32 7, i32 2)
1082 ! LLVMIR:         store <512 x i1> %[[VAL_421]], ptr %[[VAL_416]], align 64
1083
1084       subroutine test_pmxvf64gerpp_r8_def()
1085       use, intrinsic :: mma
1086       implicit none
1087       vector(real(8)) vr80
1088       __vector_pair :: cp
1089       __vector_quad :: cq
1090       call mma_pmxvf64gerpp(cq, cp, vr80, 7, 2)
1091       end subroutine test_pmxvf64gerpp_r8_def
1092
1093 !CHECK-LABEL: @test_pmxvf64gerpp_r8_def_
1094 ! LLVMIR:         %[[VAL_422:.*]] = alloca <2 x double>, i64 1, align 16
1095 ! LLVMIR:         %[[VAL_423:.*]] = alloca <512 x i1>, i64 1, align 64
1096 ! LLVMIR:         %[[VAL_424:.*]] = alloca <256 x i1>, i64 1, align 32
1097 ! LLVMIR:         %[[VAL_425:.*]] = load <256 x i1>, ptr %[[VAL_424]], align 32
1098 ! LLVMIR:         %[[VAL_426:.*]] = load <2 x double>, ptr %[[VAL_422]], align 16
1099 ! LLVMIR:         %[[VAL_427:.*]] = load <512 x i1>, ptr %[[VAL_423]], align 64
1100 ! LLVMIR:         %[[VAL_428:.*]] = bitcast <2 x double> %[[VAL_426]] to <16 x i8>
1101 ! LLVMIR:         %[[VAL_429:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf64gerpp(<512 x i1> %[[VAL_427]], <256 x i1> %[[VAL_425]], <16 x i8> %[[VAL_428]], i32 7, i32 2)
1102 ! LLVMIR:         store <512 x i1> %[[VAL_429]], ptr %[[VAL_423]], align 64
1103
1104       subroutine test_pmxvf64gerpp_r8_non_def()
1105       use, intrinsic :: mma
1106       implicit none
1107       vector(real(8)) vr80
1108       __vector_pair :: cp
1109       __vector_quad :: cq
1110       call mma_pmxvf64gerpp(cq, cp, vr80, 7_2, 2_1)
1111       end subroutine test_pmxvf64gerpp_r8_non_def
1112
1113 !CHECK-LABEL: @test_pmxvf64gerpp_r8_non_def_
1114 ! LLVMIR:         %[[VAL_430:.*]] = alloca <2 x double>, i64 1, align 16
1115 ! LLVMIR:         %[[VAL_431:.*]] = alloca <512 x i1>, i64 1, align 64
1116 ! LLVMIR:         %[[VAL_432:.*]] = alloca <256 x i1>, i64 1, align 32
1117 ! LLVMIR:         %[[VAL_433:.*]] = load <256 x i1>, ptr %[[VAL_432]], align 32
1118 ! LLVMIR:         %[[VAL_434:.*]] = load <2 x double>, ptr %[[VAL_430]], align 16
1119 ! LLVMIR:         %[[VAL_435:.*]] = load <512 x i1>, ptr %[[VAL_431]], align 64
1120 ! LLVMIR:         %[[VAL_436:.*]] = bitcast <2 x double> %[[VAL_434]] to <16 x i8>
1121 ! LLVMIR:         %[[VAL_437:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvf64gerpp(<512 x i1> %[[VAL_435]], <256 x i1> %[[VAL_433]], <16 x i8> %[[VAL_436]], i32 7, i32 2)
1122 ! LLVMIR:         store <512 x i1> %[[VAL_437]], ptr %[[VAL_431]], align 64
1123
1124       subroutine test_pmxvi16ger2_u1_def()
1125       use, intrinsic :: mma
1126       implicit none
1127       vector(unsigned(1)) vu10, vu11
1128       __vector_quad :: cq
1129       call mma_pmxvi16ger2(cq, vu10, vu11, 7, 7, 2)
1130       end subroutine test_pmxvi16ger2_u1_def
1131
1132 !CHECK-LABEL: @test_pmxvi16ger2_u1_def_
1133 ! LLVMIR:         %[[VAL_438:.*]] = alloca <16 x i8>, i64 1, align 16
1134 ! LLVMIR:         %[[VAL_439:.*]] = alloca <16 x i8>, i64 1, align 16
1135 ! LLVMIR:         %[[VAL_440:.*]] = alloca <512 x i1>, i64 1, align 64
1136 ! LLVMIR:         %[[VAL_441:.*]] = load <16 x i8>, ptr %[[VAL_439]], align 16
1137 ! LLVMIR:         %[[VAL_442:.*]] = load <16 x i8>, ptr %[[VAL_438]], align 16
1138 ! LLVMIR:         %[[VAL_443:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi16ger2(<16 x i8> %[[VAL_441]], <16 x i8> %[[VAL_442]], i32 7, i32 7, i32 2)
1139 ! LLVMIR:         store <512 x i1> %[[VAL_443]], ptr %[[VAL_440]], align 64
1140
1141       subroutine test_pmxvi16ger2_u1_non_def()
1142       use, intrinsic :: mma
1143       implicit none
1144       vector(unsigned(1)) vu10, vu11
1145       __vector_quad :: cq
1146       call mma_pmxvi16ger2(cq, vu10, vu11, 7_2, 7_1, 2_8)
1147       end subroutine test_pmxvi16ger2_u1_non_def
1148
1149 !CHECK-LABEL: @test_pmxvi16ger2_u1_non_def_
1150 ! LLVMIR:         %[[VAL_444:.*]] = alloca <16 x i8>, i64 1, align 16
1151 ! LLVMIR:         %[[VAL_445:.*]] = alloca <16 x i8>, i64 1, align 16
1152 ! LLVMIR:         %[[VAL_446:.*]] = alloca <512 x i1>, i64 1, align 64
1153 ! LLVMIR:         %[[VAL_447:.*]] = load <16 x i8>, ptr %[[VAL_445]], align 16
1154 ! LLVMIR:         %[[VAL_448:.*]] = load <16 x i8>, ptr %[[VAL_444]], align 16
1155 ! LLVMIR:         %[[VAL_449:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi16ger2(<16 x i8> %[[VAL_447]], <16 x i8> %[[VAL_448]], i32 7, i32 7, i32 2)
1156 ! LLVMIR:         store <512 x i1> %[[VAL_449]], ptr %[[VAL_446]], align 64
1157
1158       subroutine test_pmxvi16ger2_i2_def()
1159       use, intrinsic :: mma
1160       implicit none
1161       vector(integer(2)) vi20, vi21
1162       __vector_quad :: cq
1163       call mma_pmxvi16ger2(cq, vi20, vi21, 7, 7, 2)
1164       end subroutine test_pmxvi16ger2_i2_def
1165
1166 !CHECK-LABEL: @test_pmxvi16ger2_i2_def_
1167 ! LLVMIR:         %[[VAL_450:.*]] = alloca <8 x i16>, i64 1, align 16
1168 ! LLVMIR:         %[[VAL_451:.*]] = alloca <8 x i16>, i64 1, align 16
1169 ! LLVMIR:         %[[VAL_452:.*]] = alloca <512 x i1>, i64 1, align 64
1170 ! LLVMIR:         %[[VAL_453:.*]] = load <8 x i16>, ptr %[[VAL_451]], align 16
1171 ! LLVMIR:         %[[VAL_454:.*]] = load <8 x i16>, ptr %[[VAL_450]], align 16
1172 ! LLVMIR:         %[[VAL_455:.*]] = bitcast <8 x i16> %[[VAL_453]] to <16 x i8>
1173 ! LLVMIR:         %[[VAL_456:.*]] = bitcast <8 x i16> %[[VAL_454]] to <16 x i8>
1174 ! LLVMIR:         %[[VAL_457:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi16ger2(<16 x i8> %[[VAL_455]], <16 x i8> %[[VAL_456]], i32 7, i32 7, i32 2)
1175 ! LLVMIR:         store <512 x i1> %[[VAL_457]], ptr %[[VAL_452]], align 64
1176
1177       subroutine test_pmxvi16ger2_i2_non_def()
1178       use, intrinsic :: mma
1179       implicit none
1180       vector(integer(2)) vi20, vi21
1181       __vector_quad :: cq
1182       call mma_pmxvi16ger2(cq, vi20, vi21, 7_2, 7_1, 2_8)
1183       end subroutine test_pmxvi16ger2_i2_non_def
1184
1185 !CHECK-LABEL: @test_pmxvi16ger2_i2_non_def_
1186 ! LLVMIR:         %[[VAL_458:.*]] = alloca <8 x i16>, i64 1, align 16
1187 ! LLVMIR:         %[[VAL_459:.*]] = alloca <8 x i16>, i64 1, align 16
1188 ! LLVMIR:         %[[VAL_460:.*]] = alloca <512 x i1>, i64 1, align 64
1189 ! LLVMIR:         %[[VAL_461:.*]] = load <8 x i16>, ptr %[[VAL_459]], align 16
1190 ! LLVMIR:         %[[VAL_462:.*]] = load <8 x i16>, ptr %[[VAL_458]], align 16
1191 ! LLVMIR:         %[[VAL_463:.*]] = bitcast <8 x i16> %[[VAL_461]] to <16 x i8>
1192 ! LLVMIR:         %[[VAL_464:.*]] = bitcast <8 x i16> %[[VAL_462]] to <16 x i8>
1193 ! LLVMIR:         %[[VAL_465:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi16ger2(<16 x i8> %[[VAL_463]], <16 x i8> %[[VAL_464]], i32 7, i32 7, i32 2)
1194 ! LLVMIR:         store <512 x i1> %[[VAL_465]], ptr %[[VAL_460]], align 64
1195
1196       subroutine test_pmxvi16ger2pp_u1_def()
1197       use, intrinsic :: mma
1198       implicit none
1199       vector(unsigned(1)) vu10, vu11
1200       __vector_quad :: cq
1201       call mma_pmxvi16ger2pp(cq, vu10, vu11, 7, 7, 2)
1202       end subroutine test_pmxvi16ger2pp_u1_def
1203
1204 !CHECK-LABEL: @test_pmxvi16ger2pp_u1_def_
1205 ! LLVMIR:         %[[VAL_466:.*]] = alloca <16 x i8>, i64 1, align 16
1206 ! LLVMIR:         %[[VAL_467:.*]] = alloca <16 x i8>, i64 1, align 16
1207 ! LLVMIR:         %[[VAL_468:.*]] = alloca <512 x i1>, i64 1, align 64
1208 ! LLVMIR:         %[[VAL_469:.*]] = load <16 x i8>, ptr %[[VAL_467]], align 16
1209 ! LLVMIR:         %[[VAL_470:.*]] = load <16 x i8>, ptr %[[VAL_466]], align 16
1210 ! LLVMIR:         %[[VAL_471:.*]] = load <512 x i1>, ptr %[[VAL_468]], align 64
1211 ! LLVMIR:         %[[VAL_472:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi16ger2pp(<512 x i1> %[[VAL_471]], <16 x i8> %[[VAL_469]], <16 x i8> %[[VAL_470]], i32 7, i32 7, i32 2)
1212 ! LLVMIR:         store <512 x i1> %[[VAL_472]], ptr %[[VAL_468]], align 64
1213
1214       subroutine test_pmxvi16ger2pp_u1_non_def()
1215       use, intrinsic :: mma
1216       implicit none
1217       vector(unsigned(1)) vu10, vu11
1218       __vector_quad :: cq
1219       call mma_pmxvi16ger2pp(cq, vu10, vu11, 7_2, 7_1, 2_8)
1220       end subroutine test_pmxvi16ger2pp_u1_non_def
1221
1222 !CHECK-LABEL: @test_pmxvi16ger2pp_u1_non_def_
1223 ! LLVMIR:         %[[VAL_473:.*]] = alloca <16 x i8>, i64 1, align 16
1224 ! LLVMIR:         %[[VAL_474:.*]] = alloca <16 x i8>, i64 1, align 16
1225 ! LLVMIR:         %[[VAL_475:.*]] = alloca <512 x i1>, i64 1, align 64
1226 ! LLVMIR:         %[[VAL_476:.*]] = load <16 x i8>, ptr %[[VAL_474]], align 16
1227 ! LLVMIR:         %[[VAL_477:.*]] = load <16 x i8>, ptr %[[VAL_473]], align 16
1228 ! LLVMIR:         %[[VAL_478:.*]] = load <512 x i1>, ptr %[[VAL_475]], align 64
1229 ! LLVMIR:         %[[VAL_479:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi16ger2pp(<512 x i1> %[[VAL_478]], <16 x i8> %[[VAL_476]], <16 x i8> %[[VAL_477]], i32 7, i32 7, i32 2)
1230 ! LLVMIR:         store <512 x i1> %[[VAL_479]], ptr %[[VAL_475]], align 64
1231
1232       subroutine test_pmxvi16ger2pp_i2_def()
1233       use, intrinsic :: mma
1234       implicit none
1235       vector(integer(2)) vi20, vi21
1236       __vector_quad :: cq
1237       call mma_pmxvi16ger2pp(cq, vi20, vi21, 7, 7, 2)
1238       end subroutine test_pmxvi16ger2pp_i2_def
1239
1240 !CHECK-LABEL: @test_pmxvi16ger2pp_i2_def_
1241 ! LLVMIR:         %[[VAL_480:.*]] = alloca <8 x i16>, i64 1, align 16
1242 ! LLVMIR:         %[[VAL_481:.*]] = alloca <8 x i16>, i64 1, align 16
1243 ! LLVMIR:         %[[VAL_482:.*]] = alloca <512 x i1>, i64 1, align 64
1244 ! LLVMIR:         %[[VAL_483:.*]] = load <8 x i16>, ptr %[[VAL_481]], align 16
1245 ! LLVMIR:         %[[VAL_484:.*]] = load <8 x i16>, ptr %[[VAL_480]], align 16
1246 ! LLVMIR:         %[[VAL_485:.*]] = load <512 x i1>, ptr %[[VAL_482]], align 64
1247 ! LLVMIR:         %[[VAL_486:.*]] = bitcast <8 x i16> %[[VAL_483]] to <16 x i8>
1248 ! LLVMIR:         %[[VAL_487:.*]] = bitcast <8 x i16> %[[VAL_484]] to <16 x i8>
1249 ! LLVMIR:         %[[VAL_488:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi16ger2pp(<512 x i1> %[[VAL_485]], <16 x i8> %[[VAL_486]], <16 x i8> %[[VAL_487]], i32 7, i32 7, i32 2)
1250 ! LLVMIR:         store <512 x i1> %[[VAL_488]], ptr %[[VAL_482]], align 64
1251
1252       subroutine test_pmxvi16ger2pp_i2_non_def()
1253       use, intrinsic :: mma
1254       implicit none
1255       vector(integer(2)) vi20, vi21
1256       __vector_quad :: cq
1257       call mma_pmxvi16ger2pp(cq, vi20, vi21, 7_2, 7_1, 2_8)
1258       end subroutine test_pmxvi16ger2pp_i2_non_def
1259
1260 !CHECK-LABEL: @test_pmxvi16ger2pp_i2_non_def_
1261 ! LLVMIR:         %[[VAL_489:.*]] = alloca <8 x i16>, i64 1, align 16
1262 ! LLVMIR:         %[[VAL_490:.*]] = alloca <8 x i16>, i64 1, align 16
1263 ! LLVMIR:         %[[VAL_491:.*]] = alloca <512 x i1>, i64 1, align 64
1264 ! LLVMIR:         %[[VAL_492:.*]] = load <8 x i16>, ptr %[[VAL_490]], align 16
1265 ! LLVMIR:         %[[VAL_493:.*]] = load <8 x i16>, ptr %[[VAL_489]], align 16
1266 ! LLVMIR:         %[[VAL_494:.*]] = load <512 x i1>, ptr %[[VAL_491]], align 64
1267 ! LLVMIR:         %[[VAL_495:.*]] = bitcast <8 x i16> %[[VAL_492]] to <16 x i8>
1268 ! LLVMIR:         %[[VAL_496:.*]] = bitcast <8 x i16> %[[VAL_493]] to <16 x i8>
1269 ! LLVMIR:         %[[VAL_497:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi16ger2pp(<512 x i1> %[[VAL_494]], <16 x i8> %[[VAL_495]], <16 x i8> %[[VAL_496]], i32 7, i32 7, i32 2)
1270 ! LLVMIR:         store <512 x i1> %[[VAL_497]], ptr %[[VAL_491]], align 64
1271
1272       subroutine test_pmxvi16ger2s_u1_def()
1273       use, intrinsic :: mma
1274       implicit none
1275       vector(unsigned(1)) vu10, vu11
1276       __vector_quad :: cq
1277       call mma_pmxvi16ger2s(cq, vu10, vu11, 7, 7, 2)
1278       end subroutine test_pmxvi16ger2s_u1_def
1279
1280 !CHECK-LABEL: @test_pmxvi16ger2s_u1_def_
1281 ! LLVMIR:         %[[VAL_498:.*]] = alloca <16 x i8>, i64 1, align 16
1282 ! LLVMIR:         %[[VAL_499:.*]] = alloca <16 x i8>, i64 1, align 16
1283 ! LLVMIR:         %[[VAL_500:.*]] = alloca <512 x i1>, i64 1, align 64
1284 ! LLVMIR:         %[[VAL_501:.*]] = load <16 x i8>, ptr %[[VAL_499]], align 16
1285 ! LLVMIR:         %[[VAL_502:.*]] = load <16 x i8>, ptr %[[VAL_498]], align 16
1286 ! LLVMIR:         %[[VAL_503:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi16ger2s(<16 x i8> %[[VAL_501]], <16 x i8> %[[VAL_502]], i32 7, i32 7, i32 2)
1287 ! LLVMIR:         store <512 x i1> %[[VAL_503]], ptr %[[VAL_500]], align 64
1288
1289       subroutine test_pmxvi16ger2s_u1_non_def()
1290       use, intrinsic :: mma
1291       implicit none
1292       vector(unsigned(1)) vu10, vu11
1293       __vector_quad :: cq
1294       call mma_pmxvi16ger2s(cq, vu10, vu11, 7_2, 7_1, 2_8)
1295       end subroutine test_pmxvi16ger2s_u1_non_def
1296
1297 !CHECK-LABEL: @test_pmxvi16ger2s_u1_non_def_
1298 ! LLVMIR:         %[[VAL_504:.*]] = alloca <16 x i8>, i64 1, align 16
1299 ! LLVMIR:         %[[VAL_505:.*]] = alloca <16 x i8>, i64 1, align 16
1300 ! LLVMIR:         %[[VAL_506:.*]] = alloca <512 x i1>, i64 1, align 64
1301 ! LLVMIR:         %[[VAL_507:.*]] = load <16 x i8>, ptr %[[VAL_505]], align 16
1302 ! LLVMIR:         %[[VAL_508:.*]] = load <16 x i8>, ptr %[[VAL_504]], align 16
1303 ! LLVMIR:         %[[VAL_509:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi16ger2s(<16 x i8> %[[VAL_507]], <16 x i8> %[[VAL_508]], i32 7, i32 7, i32 2)
1304 ! LLVMIR:         store <512 x i1> %[[VAL_509]], ptr %[[VAL_506]], align 64
1305
1306       subroutine test_pmxvi16ger2s_i2_def()
1307       use, intrinsic :: mma
1308       implicit none
1309       vector(integer(2)) vi20, vi21
1310       __vector_quad :: cq
1311       call mma_pmxvi16ger2s(cq, vi20, vi21, 7, 7, 2)
1312       end subroutine test_pmxvi16ger2s_i2_def
1313
1314 !CHECK-LABEL: @test_pmxvi16ger2s_i2_def_
1315 ! LLVMIR:         %[[VAL_510:.*]] = alloca <8 x i16>, i64 1, align 16
1316 ! LLVMIR:         %[[VAL_511:.*]] = alloca <8 x i16>, i64 1, align 16
1317 ! LLVMIR:         %[[VAL_512:.*]] = alloca <512 x i1>, i64 1, align 64
1318 ! LLVMIR:         %[[VAL_513:.*]] = load <8 x i16>, ptr %[[VAL_511]], align 16
1319 ! LLVMIR:         %[[VAL_514:.*]] = load <8 x i16>, ptr %[[VAL_510]], align 16
1320 ! LLVMIR:         %[[VAL_515:.*]] = bitcast <8 x i16> %[[VAL_513]] to <16 x i8>
1321 ! LLVMIR:         %[[VAL_516:.*]] = bitcast <8 x i16> %[[VAL_514]] to <16 x i8>
1322 ! LLVMIR:         %[[VAL_517:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi16ger2s(<16 x i8> %[[VAL_515]], <16 x i8> %[[VAL_516]], i32 7, i32 7, i32 2)
1323 ! LLVMIR:         store <512 x i1> %[[VAL_517]], ptr %[[VAL_512]], align 64
1324
1325       subroutine test_pmxvi16ger2s_i2_non_def()
1326       use, intrinsic :: mma
1327       implicit none
1328       vector(integer(2)) vi20, vi21
1329       __vector_quad :: cq
1330       call mma_pmxvi16ger2s(cq, vi20, vi21, 7_2, 7_1, 2_8)
1331       end subroutine test_pmxvi16ger2s_i2_non_def
1332
1333 !CHECK-LABEL: @test_pmxvi16ger2s_i2_non_def_
1334 ! LLVMIR:         %[[VAL_518:.*]] = alloca <8 x i16>, i64 1, align 16
1335 ! LLVMIR:         %[[VAL_519:.*]] = alloca <8 x i16>, i64 1, align 16
1336 ! LLVMIR:         %[[VAL_520:.*]] = alloca <512 x i1>, i64 1, align 64
1337 ! LLVMIR:         %[[VAL_521:.*]] = load <8 x i16>, ptr %[[VAL_519]], align 16
1338 ! LLVMIR:         %[[VAL_522:.*]] = load <8 x i16>, ptr %[[VAL_518]], align 16
1339 ! LLVMIR:         %[[VAL_523:.*]] = bitcast <8 x i16> %[[VAL_521]] to <16 x i8>
1340 ! LLVMIR:         %[[VAL_524:.*]] = bitcast <8 x i16> %[[VAL_522]] to <16 x i8>
1341 ! LLVMIR:         %[[VAL_525:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi16ger2s(<16 x i8> %[[VAL_523]], <16 x i8> %[[VAL_524]], i32 7, i32 7, i32 2)
1342 ! LLVMIR:         store <512 x i1> %[[VAL_525]], ptr %[[VAL_520]], align 64
1343
1344       subroutine test_pmxvi16ger2spp_u1_def()
1345       use, intrinsic :: mma
1346       implicit none
1347       vector(unsigned(1)) vu10, vu11
1348       __vector_quad :: cq
1349       call mma_pmxvi16ger2spp(cq, vu10, vu11, 7, 7, 2)
1350       end subroutine test_pmxvi16ger2spp_u1_def
1351
1352 !CHECK-LABEL: @test_pmxvi16ger2spp_u1_def_
1353 ! LLVMIR:         %[[VAL_526:.*]] = alloca <16 x i8>, i64 1, align 16
1354 ! LLVMIR:         %[[VAL_527:.*]] = alloca <16 x i8>, i64 1, align 16
1355 ! LLVMIR:         %[[VAL_528:.*]] = alloca <512 x i1>, i64 1, align 64
1356 ! LLVMIR:         %[[VAL_529:.*]] = load <16 x i8>, ptr %[[VAL_527]], align 16
1357 ! LLVMIR:         %[[VAL_530:.*]] = load <16 x i8>, ptr %[[VAL_526]], align 16
1358 ! LLVMIR:         %[[VAL_531:.*]] = load <512 x i1>, ptr %[[VAL_528]], align 64
1359 ! LLVMIR:         %[[VAL_532:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi16ger2spp(<512 x i1> %[[VAL_531]], <16 x i8> %[[VAL_529]], <16 x i8> %[[VAL_530]], i32 7, i32 7, i32 2)
1360 ! LLVMIR:         store <512 x i1> %[[VAL_532]], ptr %[[VAL_528]], align 64
1361
1362       subroutine test_pmxvi16ger2spp_u1_non_def()
1363       use, intrinsic :: mma
1364       implicit none
1365       vector(unsigned(1)) vu10, vu11
1366       __vector_quad :: cq
1367       call mma_pmxvi16ger2spp(cq, vu10, vu11, 7_2, 7_1, 2_8)
1368       end subroutine test_pmxvi16ger2spp_u1_non_def
1369
1370 !CHECK-LABEL: @test_pmxvi16ger2spp_u1_non_def_
1371 ! LLVMIR:         %[[VAL_533:.*]] = alloca <16 x i8>, i64 1, align 16
1372 ! LLVMIR:         %[[VAL_534:.*]] = alloca <16 x i8>, i64 1, align 16
1373 ! LLVMIR:         %[[VAL_535:.*]] = alloca <512 x i1>, i64 1, align 64
1374 ! LLVMIR:         %[[VAL_536:.*]] = load <16 x i8>, ptr %[[VAL_534]], align 16
1375 ! LLVMIR:         %[[VAL_537:.*]] = load <16 x i8>, ptr %[[VAL_533]], align 16
1376 ! LLVMIR:         %[[VAL_538:.*]] = load <512 x i1>, ptr %[[VAL_535]], align 64
1377 ! LLVMIR:         %[[VAL_539:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi16ger2spp(<512 x i1> %[[VAL_538]], <16 x i8> %[[VAL_536]], <16 x i8> %[[VAL_537]], i32 7, i32 7, i32 2)
1378 ! LLVMIR:         store <512 x i1> %[[VAL_539]], ptr %[[VAL_535]], align 64
1379
1380       subroutine test_pmxvi16ger2spp_i2_def()
1381       use, intrinsic :: mma
1382       implicit none
1383       vector(integer(2)) vi20, vi21
1384       __vector_quad :: cq
1385       call mma_pmxvi16ger2spp(cq, vi20, vi21, 7, 7, 2)
1386       end subroutine test_pmxvi16ger2spp_i2_def
1387
1388 !CHECK-LABEL: @test_pmxvi16ger2spp_i2_def_
1389 ! LLVMIR:         %[[VAL_540:.*]] = alloca <8 x i16>, i64 1, align 16
1390 ! LLVMIR:         %[[VAL_541:.*]] = alloca <8 x i16>, i64 1, align 16
1391 ! LLVMIR:         %[[VAL_542:.*]] = alloca <512 x i1>, i64 1, align 64
1392 ! LLVMIR:         %[[VAL_543:.*]] = load <8 x i16>, ptr %[[VAL_541]], align 16
1393 ! LLVMIR:         %[[VAL_544:.*]] = load <8 x i16>, ptr %[[VAL_540]], align 16
1394 ! LLVMIR:         %[[VAL_545:.*]] = load <512 x i1>, ptr %[[VAL_542]], align 64
1395 ! LLVMIR:         %[[VAL_546:.*]] = bitcast <8 x i16> %[[VAL_543]] to <16 x i8>
1396 ! LLVMIR:         %[[VAL_547:.*]] = bitcast <8 x i16> %[[VAL_544]] to <16 x i8>
1397 ! LLVMIR:         %[[VAL_548:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi16ger2spp(<512 x i1> %[[VAL_545]], <16 x i8> %[[VAL_546]], <16 x i8> %[[VAL_547]], i32 7, i32 7, i32 2)
1398 ! LLVMIR:         store <512 x i1> %[[VAL_548]], ptr %[[VAL_542]], align 64
1399
1400       subroutine test_pmxvi16ger2spp_i2_non_def()
1401       use, intrinsic :: mma
1402       implicit none
1403       vector(integer(2)) vi20, vi21
1404       __vector_quad :: cq
1405       call mma_pmxvi16ger2spp(cq, vi20, vi21, 7_2, 7_1, 2_8)
1406       end subroutine test_pmxvi16ger2spp_i2_non_def
1407
1408 !CHECK-LABEL: @test_pmxvi16ger2spp_i2_non_def_
1409 ! LLVMIR:         %[[VAL_549:.*]] = alloca <8 x i16>, i64 1, align 16
1410 ! LLVMIR:         %[[VAL_550:.*]] = alloca <8 x i16>, i64 1, align 16
1411 ! LLVMIR:         %[[VAL_551:.*]] = alloca <512 x i1>, i64 1, align 64
1412 ! LLVMIR:         %[[VAL_552:.*]] = load <8 x i16>, ptr %[[VAL_550]], align 16
1413 ! LLVMIR:         %[[VAL_553:.*]] = load <8 x i16>, ptr %[[VAL_549]], align 16
1414 ! LLVMIR:         %[[VAL_554:.*]] = load <512 x i1>, ptr %[[VAL_551]], align 64
1415 ! LLVMIR:         %[[VAL_555:.*]] = bitcast <8 x i16> %[[VAL_552]] to <16 x i8>
1416 ! LLVMIR:         %[[VAL_556:.*]] = bitcast <8 x i16> %[[VAL_553]] to <16 x i8>
1417 ! LLVMIR:         %[[VAL_557:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi16ger2spp(<512 x i1> %[[VAL_554]], <16 x i8> %[[VAL_555]], <16 x i8> %[[VAL_556]], i32 7, i32 7, i32 2)
1418 ! LLVMIR:         store <512 x i1> %[[VAL_557]], ptr %[[VAL_551]], align 64
1419
1420
1421       subroutine test_pmxvi4ger8_def()
1422       use, intrinsic :: mma
1423       implicit none
1424       vector(unsigned(1)) vu10, vu11
1425       __vector_quad :: cq
1426       call mma_pmxvi4ger8(cq, vu10, vu11, 7, 7, 2)
1427       end subroutine test_pmxvi4ger8_def
1428
1429 !CHECK-LABEL: @test_pmxvi4ger8_def_
1430 ! LLVMIR:         %[[VAL_558:.*]] = alloca <16 x i8>, i64 1, align 16
1431 ! LLVMIR:         %[[VAL_559:.*]] = alloca <16 x i8>, i64 1, align 16
1432 ! LLVMIR:         %[[VAL_560:.*]] = alloca <512 x i1>, i64 1, align 64
1433 ! LLVMIR:         %[[VAL_561:.*]] = load <16 x i8>, ptr %[[VAL_559]], align 16
1434 ! LLVMIR:         %[[VAL_562:.*]] = load <16 x i8>, ptr %[[VAL_558]], align 16
1435 ! LLVMIR:         %[[VAL_563:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi4ger8(<16 x i8> %[[VAL_561]], <16 x i8> %[[VAL_562]], i32 7, i32 7, i32 2)
1436 ! LLVMIR:         store <512 x i1> %[[VAL_563]], ptr %[[VAL_560]], align 64
1437
1438       subroutine test_pmxvi4ger8_non_def()
1439       use, intrinsic :: mma
1440       implicit none
1441       vector(unsigned(1)) vu10, vu11
1442       __vector_quad :: cq
1443       call mma_pmxvi4ger8(cq, vu10, vu11, 7_2, 7_1, 2_8)
1444       end subroutine test_pmxvi4ger8_non_def
1445
1446 !CHECK-LABEL: @test_pmxvi4ger8_non_def_
1447 ! LLVMIR:         %[[VAL_564:.*]] = alloca <16 x i8>, i64 1, align 16
1448 ! LLVMIR:         %[[VAL_565:.*]] = alloca <16 x i8>, i64 1, align 16
1449 ! LLVMIR:         %[[VAL_566:.*]] = alloca <512 x i1>, i64 1, align 64
1450 ! LLVMIR:         %[[VAL_567:.*]] = load <16 x i8>, ptr %[[VAL_565]], align 16
1451 ! LLVMIR:         %[[VAL_568:.*]] = load <16 x i8>, ptr %[[VAL_564]], align 16
1452 ! LLVMIR:         %[[VAL_569:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi4ger8(<16 x i8> %[[VAL_567]], <16 x i8> %[[VAL_568]], i32 7, i32 7, i32 2)
1453 ! LLVMIR:         store <512 x i1> %[[VAL_569]], ptr %[[VAL_566]], align 64
1454
1455       subroutine test_pmxvi4ger8pp_def()
1456       use, intrinsic :: mma
1457       implicit none
1458       vector(unsigned(1)) vu10, vu11
1459       __vector_quad :: cq
1460       call mma_pmxvi4ger8pp(cq, vu10, vu11, 7, 7, 2)
1461       end subroutine test_pmxvi4ger8pp_def
1462
1463 !CHECK-LABEL: @test_pmxvi4ger8pp_def_
1464 ! LLVMIR:         %[[VAL_570:.*]] = alloca <16 x i8>, i64 1, align 16
1465 ! LLVMIR:         %[[VAL_571:.*]] = alloca <16 x i8>, i64 1, align 16
1466 ! LLVMIR:         %[[VAL_572:.*]] = alloca <512 x i1>, i64 1, align 64
1467 ! LLVMIR:         %[[VAL_573:.*]] = load <16 x i8>, ptr %[[VAL_571]], align 16
1468 ! LLVMIR:         %[[VAL_574:.*]] = load <16 x i8>, ptr %[[VAL_570]], align 16
1469 ! LLVMIR:         %[[VAL_575:.*]] = load <512 x i1>, ptr %[[VAL_572]], align 64
1470 ! LLVMIR:         %[[VAL_576:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi4ger8pp(<512 x i1> %[[VAL_575]], <16 x i8> %[[VAL_573]], <16 x i8> %[[VAL_574]], i32 7, i32 7, i32 2)
1471 ! LLVMIR:         store <512 x i1> %[[VAL_576]], ptr %[[VAL_572]], align 64
1472
1473       subroutine test_pmxvi4ger8pp_non_def()
1474       use, intrinsic :: mma
1475       implicit none
1476       vector(unsigned(1)) vu10, vu11
1477       __vector_quad :: cq
1478       call mma_pmxvi4ger8pp(cq, vu10, vu11, 7_2, 7_1, 2_8)
1479       end subroutine test_pmxvi4ger8pp_non_def
1480
1481 !CHECK-LABEL: @test_pmxvi4ger8pp_non_def_
1482 ! LLVMIR:         %[[VAL_577:.*]] = alloca <16 x i8>, i64 1, align 16
1483 ! LLVMIR:         %[[VAL_578:.*]] = alloca <16 x i8>, i64 1, align 16
1484 ! LLVMIR:         %[[VAL_579:.*]] = alloca <512 x i1>, i64 1, align 64
1485 ! LLVMIR:         %[[VAL_580:.*]] = load <16 x i8>, ptr %[[VAL_578]], align 16
1486 ! LLVMIR:         %[[VAL_581:.*]] = load <16 x i8>, ptr %[[VAL_577]], align 16
1487 ! LLVMIR:         %[[VAL_582:.*]] = load <512 x i1>, ptr %[[VAL_579]], align 64
1488 ! LLVMIR:         %[[VAL_583:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi4ger8pp(<512 x i1> %[[VAL_582]], <16 x i8> %[[VAL_580]], <16 x i8> %[[VAL_581]], i32 7, i32 7, i32 2)
1489 ! LLVMIR:         store <512 x i1> %[[VAL_583]], ptr %[[VAL_579]], align 64
1490
1491       subroutine test_pmxvi8ger4_u1_def()
1492       use, intrinsic :: mma
1493       implicit none
1494       vector(unsigned(1)) vu10, vu11
1495       __vector_quad :: cq
1496       call mma_pmxvi8ger4(cq, vu10, vu11, 7, 7, 2)
1497       end subroutine test_pmxvi8ger4_u1_def
1498
1499 !CHECK-LABEL: @test_pmxvi8ger4_u1_def_
1500 ! LLVMIR:         %[[VAL_584:.*]] = alloca <16 x i8>, i64 1, align 16
1501 ! LLVMIR:         %[[VAL_585:.*]] = alloca <16 x i8>, i64 1, align 16
1502 ! LLVMIR:         %[[VAL_586:.*]] = alloca <512 x i1>, i64 1, align 64
1503 ! LLVMIR:         %[[VAL_587:.*]] = load <16 x i8>, ptr %[[VAL_585]], align 16
1504 ! LLVMIR:         %[[VAL_588:.*]] = load <16 x i8>, ptr %[[VAL_584]], align 16
1505 ! LLVMIR:         %[[VAL_589:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi8ger4(<16 x i8> %[[VAL_587]], <16 x i8> %[[VAL_588]], i32 7, i32 7, i32 2)
1506 ! LLVMIR:         store <512 x i1> %[[VAL_589]], ptr %[[VAL_586]], align 64
1507
1508       subroutine test_pmxvi8ger4_u1_non_def()
1509       use, intrinsic :: mma
1510       implicit none
1511       vector(unsigned(1)) vu10, vu11
1512       __vector_quad :: cq
1513       call mma_pmxvi8ger4(cq, vu10, vu11, 7_2, 7_1, 2_8)
1514       end subroutine test_pmxvi8ger4_u1_non_def
1515
1516 !CHECK-LABEL: @test_pmxvi8ger4_u1_non_def_
1517 ! LLVMIR:         %[[VAL_590:.*]] = alloca <16 x i8>, i64 1, align 16
1518 ! LLVMIR:         %[[VAL_591:.*]] = alloca <16 x i8>, i64 1, align 16
1519 ! LLVMIR:         %[[VAL_592:.*]] = alloca <512 x i1>, i64 1, align 64
1520 ! LLVMIR:         %[[VAL_593:.*]] = load <16 x i8>, ptr %[[VAL_591]], align 16
1521 ! LLVMIR:         %[[VAL_594:.*]] = load <16 x i8>, ptr %[[VAL_590]], align 16
1522 ! LLVMIR:         %[[VAL_595:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi8ger4(<16 x i8> %[[VAL_593]], <16 x i8> %[[VAL_594]], i32 7, i32 7, i32 2)
1523 ! LLVMIR:         store <512 x i1> %[[VAL_595]], ptr %[[VAL_592]], align 64
1524
1525       subroutine test_pmxvi8ger4_i1_def()
1526       use, intrinsic :: mma
1527       implicit none
1528       vector(integer(1)) vi10, vi11
1529       __vector_quad :: cq
1530       call mma_pmxvi8ger4(cq, vi10, vi11, 7, 7, 2)
1531       end subroutine test_pmxvi8ger4_i1_def
1532
1533 !CHECK-LABEL: @test_pmxvi8ger4_i1_def_
1534 ! LLVMIR:         %[[VAL_596:.*]] = alloca <16 x i8>, i64 1, align 16
1535 ! LLVMIR:         %[[VAL_597:.*]] = alloca <16 x i8>, i64 1, align 16
1536 ! LLVMIR:         %[[VAL_598:.*]] = alloca <512 x i1>, i64 1, align 64
1537 ! LLVMIR:         %[[VAL_599:.*]] = load <16 x i8>, ptr %[[VAL_597]], align 16
1538 ! LLVMIR:         %[[VAL_600:.*]] = load <16 x i8>, ptr %[[VAL_596]], align 16
1539 ! LLVMIR:         %[[VAL_601:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi8ger4(<16 x i8> %[[VAL_599]], <16 x i8> %[[VAL_600]], i32 7, i32 7, i32 2)
1540 ! LLVMIR:         store <512 x i1> %[[VAL_601]], ptr %[[VAL_598]], align 64
1541
1542       subroutine test_pmxvi8ger4_i1_non_def()
1543       use, intrinsic :: mma
1544       implicit none
1545       vector(integer(1)) vi10, vi11
1546       __vector_quad :: cq
1547       call mma_pmxvi8ger4(cq, vi10, vi11, 7_2, 7_1, 2_8)
1548       end subroutine test_pmxvi8ger4_i1_non_def
1549
1550 !CHECK-LABEL: @test_pmxvi8ger4_i1_non_def_
1551 ! LLVMIR:         %[[VAL_602:.*]] = alloca <16 x i8>, i64 1, align 16
1552 ! LLVMIR:         %[[VAL_603:.*]] = alloca <16 x i8>, i64 1, align 16
1553 ! LLVMIR:         %[[VAL_604:.*]] = alloca <512 x i1>, i64 1, align 64
1554 ! LLVMIR:         %[[VAL_605:.*]] = load <16 x i8>, ptr %[[VAL_603]], align 16
1555 ! LLVMIR:         %[[VAL_606:.*]] = load <16 x i8>, ptr %[[VAL_602]], align 16
1556 ! LLVMIR:         %[[VAL_607:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi8ger4(<16 x i8> %[[VAL_605]], <16 x i8> %[[VAL_606]], i32 7, i32 7, i32 2)
1557 ! LLVMIR:         store <512 x i1> %[[VAL_607]], ptr %[[VAL_604]], align 64
1558
1559       subroutine test_pmxvi8ger4pp_u1_def()
1560       use, intrinsic :: mma
1561       implicit none
1562       vector(unsigned(1)) vu10, vu11
1563       __vector_quad :: cq
1564       call mma_pmxvi8ger4pp(cq, vu10, vu11, 7, 7, 2)
1565       end subroutine test_pmxvi8ger4pp_u1_def
1566
1567 !CHECK-LABEL: @test_pmxvi8ger4pp_u1_def_
1568 ! LLVMIR:         %[[VAL_608:.*]] = alloca <16 x i8>, i64 1, align 16
1569 ! LLVMIR:         %[[VAL_609:.*]] = alloca <16 x i8>, i64 1, align 16
1570 ! LLVMIR:         %[[VAL_610:.*]] = alloca <512 x i1>, i64 1, align 64
1571 ! LLVMIR:         %[[VAL_611:.*]] = load <16 x i8>, ptr %[[VAL_609]], align 16
1572 ! LLVMIR:         %[[VAL_612:.*]] = load <16 x i8>, ptr %[[VAL_608]], align 16
1573 ! LLVMIR:         %[[VAL_613:.*]] = load <512 x i1>, ptr %[[VAL_610]], align 64
1574 ! LLVMIR:         %[[VAL_614:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi8ger4pp(<512 x i1> %[[VAL_613]], <16 x i8> %[[VAL_611]], <16 x i8> %[[VAL_612]], i32 7, i32 7, i32 2)
1575 ! LLVMIR:         store <512 x i1> %[[VAL_614]], ptr %[[VAL_610]], align 64
1576
1577       subroutine test_pmxvi8ger4pp_u1_non_def()
1578       use, intrinsic :: mma
1579       implicit none
1580       vector(unsigned(1)) vu10, vu11
1581       __vector_quad :: cq
1582       call mma_pmxvi8ger4pp(cq, vu10, vu11, 7_2, 7_1, 2_8)
1583       end subroutine test_pmxvi8ger4pp_u1_non_def
1584
1585 !CHECK-LABEL: @test_pmxvi8ger4pp_u1_non_def_
1586 ! LLVMIR:         %[[VAL_615:.*]] = alloca <16 x i8>, i64 1, align 16
1587 ! LLVMIR:         %[[VAL_616:.*]] = alloca <16 x i8>, i64 1, align 16
1588 ! LLVMIR:         %[[VAL_617:.*]] = alloca <512 x i1>, i64 1, align 64
1589 ! LLVMIR:         %[[VAL_618:.*]] = load <16 x i8>, ptr %[[VAL_616]], align 16
1590 ! LLVMIR:         %[[VAL_619:.*]] = load <16 x i8>, ptr %[[VAL_615]], align 16
1591 ! LLVMIR:         %[[VAL_620:.*]] = load <512 x i1>, ptr %[[VAL_617]], align 64
1592 ! LLVMIR:         %[[VAL_621:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi8ger4pp(<512 x i1> %[[VAL_620]], <16 x i8> %[[VAL_618]], <16 x i8> %[[VAL_619]], i32 7, i32 7, i32 2)
1593 ! LLVMIR:         store <512 x i1> %[[VAL_621]], ptr %[[VAL_617]], align 64
1594
1595       subroutine test_pmxvi8ger4pp_i1_def()
1596       use, intrinsic :: mma
1597       implicit none
1598       vector(integer(1)) vi10, vi11
1599       __vector_quad :: cq
1600       call mma_pmxvi8ger4pp(cq, vi10, vi11, 7, 7, 2)
1601       end subroutine test_pmxvi8ger4pp_i1_def
1602
1603 !CHECK-LABEL: @test_pmxvi8ger4pp_i1_def_
1604 ! LLVMIR:         %[[VAL_622:.*]] = alloca <16 x i8>, i64 1, align 16
1605 ! LLVMIR:         %[[VAL_623:.*]] = alloca <16 x i8>, i64 1, align 16
1606 ! LLVMIR:         %[[VAL_624:.*]] = alloca <512 x i1>, i64 1, align 64
1607 ! LLVMIR:         %[[VAL_625:.*]] = load <16 x i8>, ptr %[[VAL_623]], align 16
1608 ! LLVMIR:         %[[VAL_626:.*]] = load <16 x i8>, ptr %[[VAL_622]], align 16
1609 ! LLVMIR:         %[[VAL_627:.*]] = load <512 x i1>, ptr %[[VAL_624]], align 64
1610 ! LLVMIR:         %[[VAL_628:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi8ger4pp(<512 x i1> %[[VAL_627]], <16 x i8> %[[VAL_625]], <16 x i8> %[[VAL_626]], i32 7, i32 7, i32 2)
1611 ! LLVMIR:         store <512 x i1> %[[VAL_628]], ptr %[[VAL_624]], align 64
1612
1613       subroutine test_pmxvi8ger4pp_i1_non_def()
1614       use, intrinsic :: mma
1615       implicit none
1616       vector(integer(1)) vi10, vi11
1617       __vector_quad :: cq
1618       call mma_pmxvi8ger4pp(cq, vi10, vi11, 7_2, 7_1, 2_8)
1619       end subroutine test_pmxvi8ger4pp_i1_non_def
1620
1621 !CHECK-LABEL: @test_pmxvi8ger4pp_i1_non_def_
1622 ! LLVMIR:         %[[VAL_629:.*]] = alloca <16 x i8>, i64 1, align 16
1623 ! LLVMIR:         %[[VAL_630:.*]] = alloca <16 x i8>, i64 1, align 16
1624 ! LLVMIR:         %[[VAL_631:.*]] = alloca <512 x i1>, i64 1, align 64
1625 ! LLVMIR:         %[[VAL_632:.*]] = load <16 x i8>, ptr %[[VAL_630]], align 16
1626 ! LLVMIR:         %[[VAL_633:.*]] = load <16 x i8>, ptr %[[VAL_629]], align 16
1627 ! LLVMIR:         %[[VAL_634:.*]] = load <512 x i1>, ptr %[[VAL_631]], align 64
1628 ! LLVMIR:         %[[VAL_635:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi8ger4pp(<512 x i1> %[[VAL_634]], <16 x i8> %[[VAL_632]], <16 x i8> %[[VAL_633]], i32 7, i32 7, i32 2)
1629 ! LLVMIR:         store <512 x i1> %[[VAL_635]], ptr %[[VAL_631]], align 64
1630
1631       subroutine test_pmxvi8ger4spp_u1_def()
1632       use, intrinsic :: mma
1633       implicit none
1634       vector(unsigned(1)) vu10, vu11
1635       __vector_quad :: cq
1636       call mma_pmxvi8ger4spp(cq, vu10, vu11, 7, 7, 2)
1637       end subroutine test_pmxvi8ger4spp_u1_def
1638
1639 !CHECK-LABEL: @test_pmxvi8ger4spp_u1_def_
1640 ! LLVMIR:         %[[VAL_636:.*]] = alloca <16 x i8>, i64 1, align 16
1641 ! LLVMIR:         %[[VAL_637:.*]] = alloca <16 x i8>, i64 1, align 16
1642 ! LLVMIR:         %[[VAL_638:.*]] = alloca <512 x i1>, i64 1, align 64
1643 ! LLVMIR:         %[[VAL_639:.*]] = load <16 x i8>, ptr %[[VAL_637]], align 16
1644 ! LLVMIR:         %[[VAL_640:.*]] = load <16 x i8>, ptr %[[VAL_636]], align 16
1645 ! LLVMIR:         %[[VAL_641:.*]] = load <512 x i1>, ptr %[[VAL_638]], align 64
1646 ! LLVMIR:         %[[VAL_642:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi8ger4spp(<512 x i1> %[[VAL_641]], <16 x i8> %[[VAL_639]], <16 x i8> %[[VAL_640]], i32 7, i32 7, i32 2)
1647 ! LLVMIR:         store <512 x i1> %[[VAL_642]], ptr %[[VAL_638]], align 64
1648
1649       subroutine test_pmxvi8ger4spp_u1_non_def()
1650       use, intrinsic :: mma
1651       implicit none
1652       vector(unsigned(1)) vu10, vu11
1653       __vector_quad :: cq
1654       call mma_pmxvi8ger4spp(cq, vu10, vu11, 7_2, 7_1, 2_8)
1655       end subroutine test_pmxvi8ger4spp_u1_non_def
1656
1657 !CHECK-LABEL: @test_pmxvi8ger4spp_u1_non_def_
1658 ! LLVMIR:         %[[VAL_643:.*]] = alloca <16 x i8>, i64 1, align 16
1659 ! LLVMIR:         %[[VAL_644:.*]] = alloca <16 x i8>, i64 1, align 16
1660 ! LLVMIR:         %[[VAL_645:.*]] = alloca <512 x i1>, i64 1, align 64
1661 ! LLVMIR:         %[[VAL_646:.*]] = load <16 x i8>, ptr %[[VAL_644]], align 16
1662 ! LLVMIR:         %[[VAL_647:.*]] = load <16 x i8>, ptr %[[VAL_643]], align 16
1663 ! LLVMIR:         %[[VAL_648:.*]] = load <512 x i1>, ptr %[[VAL_645]], align 64
1664 ! LLVMIR:         %[[VAL_649:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi8ger4spp(<512 x i1> %[[VAL_648]], <16 x i8> %[[VAL_646]], <16 x i8> %[[VAL_647]], i32 7, i32 7, i32 2)
1665 ! LLVMIR:         store <512 x i1> %[[VAL_649]], ptr %[[VAL_645]], align 64
1666
1667       subroutine test_pmxvi8ger4spp_i1_def()
1668       use, intrinsic :: mma
1669       implicit none
1670       vector(integer(1)) vi10, vi11
1671       __vector_quad :: cq
1672       call mma_pmxvi8ger4spp(cq, vi10, vi11, 7, 7, 2)
1673       end subroutine test_pmxvi8ger4spp_i1_def
1674
1675 !CHECK-LABEL: @test_pmxvi8ger4spp_i1_def_
1676 ! LLVMIR:         %[[VAL_650:.*]] = alloca <16 x i8>, i64 1, align 16
1677 ! LLVMIR:         %[[VAL_651:.*]] = alloca <16 x i8>, i64 1, align 16
1678 ! LLVMIR:         %[[VAL_652:.*]] = alloca <512 x i1>, i64 1, align 64
1679 ! LLVMIR:         %[[VAL_653:.*]] = load <16 x i8>, ptr %[[VAL_651]], align 16
1680 ! LLVMIR:         %[[VAL_654:.*]] = load <16 x i8>, ptr %[[VAL_650]], align 16
1681 ! LLVMIR:         %[[VAL_655:.*]] = load <512 x i1>, ptr %[[VAL_652]], align 64
1682 ! LLVMIR:         %[[VAL_656:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi8ger4spp(<512 x i1> %[[VAL_655]], <16 x i8> %[[VAL_653]], <16 x i8> %[[VAL_654]], i32 7, i32 7, i32 2)
1683 ! LLVMIR:         store <512 x i1> %[[VAL_656]], ptr %[[VAL_652]], align 64
1684
1685       subroutine test_pmxvi8ger4spp_i1_non_def()
1686       use, intrinsic :: mma
1687       implicit none
1688       vector(integer(1)) vi10, vi11
1689       __vector_quad :: cq
1690       call mma_pmxvi8ger4spp(cq, vi10, vi11, 7_2, 7_1, 2_8)
1691       end subroutine test_pmxvi8ger4spp_i1_non_def
1692
1693 !CHECK-LABEL: @test_pmxvi8ger4spp_i1_non_def_
1694 ! LLVMIR:         %[[VAL_657:.*]] = alloca <16 x i8>, i64 1, align 16
1695 ! LLVMIR:         %[[VAL_658:.*]] = alloca <16 x i8>, i64 1, align 16
1696 ! LLVMIR:         %[[VAL_659:.*]] = alloca <512 x i1>, i64 1, align 64
1697 ! LLVMIR:         %[[VAL_660:.*]] = load <16 x i8>, ptr %[[VAL_658]], align 16
1698 ! LLVMIR:         %[[VAL_661:.*]] = load <16 x i8>, ptr %[[VAL_657]], align 16
1699 ! LLVMIR:         %[[VAL_662:.*]] = load <512 x i1>, ptr %[[VAL_659]], align 64
1700 ! LLVMIR:         %[[VAL_663:.*]] = call <512 x i1> @llvm.ppc.mma.pmxvi8ger4spp(<512 x i1> %[[VAL_662]], <16 x i8> %[[VAL_660]], <16 x i8> %[[VAL_661]], i32 7, i32 7, i32 2)
1701 ! LLVMIR:         store <512 x i1> %[[VAL_663]], ptr %[[VAL_659]], align 64