flang/test/Lower/PowerPC/ppc-mma-outer-product-2.f90

   1 ! RUN: %flang_fc1 -flang-experimental-hlfir -triple powerpc64le-unknown-unknown -target-cpu pwr10 -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR" %s
   2 ! REQUIRES: target=powerpc{{.*}}
   3
   4       subroutine test_xvbf16ger2()
   5       use, intrinsic :: mma
   6       implicit none
   7       vector(unsigned(1)) vu10, vu11
   8       __vector_quad :: cq
   9       call mma_xvbf16ger2(cq, vu10, vu11)
  10       end subroutine test_xvbf16ger2
  11
  12 !CHECK-LABEL: @test_xvbf16ger2_
  13 ! LLVMIR:         %[[VAL_0:.*]] = alloca <16 x i8>, i64 1, align 16
  14 ! LLVMIR:         %[[VAL_1:.*]] = alloca <16 x i8>, i64 1, align 16
  15 ! LLVMIR:         %[[VAL_2:.*]] = alloca <512 x i1>, i64 1, align 64
  16 ! LLVMIR:         %[[VAL_3:.*]] = load <16 x i8>, ptr %[[VAL_1]], align 16
  17 ! LLVMIR:         %[[VAL_4:.*]] = load <16 x i8>, ptr %[[VAL_0]], align 16
  18 ! LLVMIR:         %[[VAL_5:.*]] = call <512 x i1> @llvm.ppc.mma.xvbf16ger2(<16 x i8> %[[VAL_3]], <16 x i8> %[[VAL_4]])
  19 ! LLVMIR:         store <512 x i1> %[[VAL_5]], ptr %[[VAL_2]], align 64
  20
  21
  22       subroutine test_xvbf16ger2nn()
  23       use, intrinsic :: mma
  24       implicit none
  25       vector(unsigned(1)) vu10, vu11
  26       __vector_quad :: cq
  27       call mma_xvbf16ger2nn(cq, vu10, vu11)
  28       end subroutine test_xvbf16ger2nn
  29
  30 !CHECK-LABEL: @test_xvbf16ger2nn_
  31 ! LLVMIR:         %[[VAL_6:.*]] = alloca <16 x i8>, i64 1, align 16
  32 ! LLVMIR:         %[[VAL_7:.*]] = alloca <16 x i8>, i64 1, align 16
  33 ! LLVMIR:         %[[VAL_8:.*]] = alloca <512 x i1>, i64 1, align 64
  34 ! LLVMIR:         %[[VAL_9:.*]] = load <16 x i8>, ptr %[[VAL_7]], align 16
  35 ! LLVMIR:         %[[VAL_10:.*]] = load <16 x i8>, ptr %[[VAL_6]], align 16
  36 ! LLVMIR:         %[[VAL_11:.*]] = load <512 x i1>, ptr %[[VAL_8]], align 64
  37 ! LLVMIR:         %[[VAL_12:.*]] = call <512 x i1> @llvm.ppc.mma.xvbf16ger2nn(<512 x i1> %[[VAL_11]], <16 x i8> %[[VAL_9]], <16 x i8> %[[VAL_10]])
  38 ! LLVMIR:         store <512 x i1> %[[VAL_12]], ptr %[[VAL_8]], align 64
  39
  40       subroutine test_xvbf16ger2np()
  41       use, intrinsic :: mma
  42       implicit none
  43       vector(unsigned(1)) vu10, vu11
  44       __vector_quad :: cq
  45       call mma_xvbf16ger2np(cq, vu10, vu11)
  46       end subroutine test_xvbf16ger2np
  47
  48 !CHECK-LABEL: @test_xvbf16ger2np_
  49 ! LLVMIR:         %[[VAL_13:.*]] = alloca <16 x i8>, i64 1, align 16
  50 ! LLVMIR:         %[[VAL_14:.*]] = alloca <16 x i8>, i64 1, align 16
  51 ! LLVMIR:         %[[VAL_15:.*]] = alloca <512 x i1>, i64 1, align 64
  52 ! LLVMIR:         %[[VAL_16:.*]] = load <16 x i8>, ptr %[[VAL_14]], align 16
  53 ! LLVMIR:         %[[VAL_17:.*]] = load <16 x i8>, ptr %[[VAL_13]], align 16
  54 ! LLVMIR:         %[[VAL_18:.*]] = load <512 x i1>, ptr %[[VAL_15]], align 64
  55 ! LLVMIR:         %[[VAL_19:.*]] = call <512 x i1> @llvm.ppc.mma.xvbf16ger2np(<512 x i1> %[[VAL_18]], <16 x i8> %[[VAL_16]], <16 x i8> %[[VAL_17]])
  56 ! LLVMIR:         store <512 x i1> %[[VAL_19]], ptr %[[VAL_15]], align 64
  57
  58       subroutine test_xvbf16ger2pn()
  59       use, intrinsic :: mma
  60       implicit none
  61       vector(unsigned(1)) vu10, vu11
  62       __vector_quad :: cq
  63       call mma_xvbf16ger2pn(cq, vu10, vu11)
  64       end subroutine test_xvbf16ger2pn
  65
  66 !CHECK-LABEL: @test_xvbf16ger2pn_
  67 ! LLVMIR:         %[[VAL_20:.*]] = alloca <16 x i8>, i64 1, align 16
  68 ! LLVMIR:         %[[VAL_21:.*]] = alloca <16 x i8>, i64 1, align 16
  69 ! LLVMIR:         %[[VAL_22:.*]] = alloca <512 x i1>, i64 1, align 64
  70 ! LLVMIR:         %[[VAL_23:.*]] = load <16 x i8>, ptr %[[VAL_21]], align 16
  71 ! LLVMIR:         %[[VAL_24:.*]] = load <16 x i8>, ptr %[[VAL_20]], align 16
  72 ! LLVMIR:         %[[VAL_25:.*]] = load <512 x i1>, ptr %[[VAL_22]], align 64
  73 ! LLVMIR:         %[[VAL_26:.*]] = call <512 x i1> @llvm.ppc.mma.xvbf16ger2pn(<512 x i1> %[[VAL_25]], <16 x i8> %[[VAL_23]], <16 x i8> %[[VAL_24]])
  74 ! LLVMIR:         store <512 x i1> %[[VAL_26]], ptr %[[VAL_22]], align 64
  75
  76       subroutine test_xvbf16ger2pp()
  77       use, intrinsic :: mma
  78       implicit none
  79       vector(unsigned(1)) vu10, vu11
  80       __vector_quad :: cq
  81       call mma_xvbf16ger2pp(cq, vu10, vu11)
  82       end subroutine test_xvbf16ger2pp
  83
  84 !CHECK-LABEL: @test_xvbf16ger2pp_
  85 ! LLVMIR:         %[[VAL_27:.*]] = alloca <16 x i8>, i64 1, align 16
  86 ! LLVMIR:         %[[VAL_28:.*]] = alloca <16 x i8>, i64 1, align 16
  87 ! LLVMIR:         %[[VAL_29:.*]] = alloca <512 x i1>, i64 1, align 64
  88 ! LLVMIR:         %[[VAL_30:.*]] = load <16 x i8>, ptr %[[VAL_28]], align 16
  89 ! LLVMIR:         %[[VAL_31:.*]] = load <16 x i8>, ptr %[[VAL_27]], align 16
  90 ! LLVMIR:         %[[VAL_32:.*]] = load <512 x i1>, ptr %[[VAL_29]], align 64
  91 ! LLVMIR:         %[[VAL_33:.*]] = call <512 x i1> @llvm.ppc.mma.xvbf16ger2pp(<512 x i1> %[[VAL_32]], <16 x i8> %[[VAL_30]], <16 x i8> %[[VAL_31]])
  92 ! LLVMIR:         store <512 x i1> %[[VAL_33]], ptr %[[VAL_29]], align 64
  93
  94       subroutine test_xvf16ger2()
  95       use, intrinsic :: mma
  96       implicit none
  97       vector(unsigned(1)) vu10, vu11
  98       __vector_quad :: cq
  99       call mma_xvf16ger2(cq, vu10, vu11)
 100       end subroutine test_xvf16ger2
 101
 102 !CHECK-LABEL: @test_xvf16ger2_
 103 ! LLVMIR:         %[[VAL_34:.*]] = alloca <16 x i8>, i64 1, align 16
 104 ! LLVMIR:         %[[VAL_35:.*]] = alloca <16 x i8>, i64 1, align 16
 105 ! LLVMIR:         %[[VAL_36:.*]] = alloca <512 x i1>, i64 1, align 64
 106 ! LLVMIR:         %[[VAL_37:.*]] = load <16 x i8>, ptr %[[VAL_35]], align 16
 107 ! LLVMIR:         %[[VAL_38:.*]] = load <16 x i8>, ptr %[[VAL_34]], align 16
 108 ! LLVMIR:         %[[VAL_39:.*]] = call <512 x i1> @llvm.ppc.mma.xvf16ger2(<16 x i8> %[[VAL_37]], <16 x i8> %[[VAL_38]])
 109 ! LLVMIR:         store <512 x i1> %[[VAL_39]], ptr %[[VAL_36]], align 64
 110
 111       subroutine test_xvf16ger2nn()
 112       use, intrinsic :: mma
 113       implicit none
 114       vector(unsigned(1)) vu10, vu11
 115       __vector_quad :: cq
 116       call mma_xvf16ger2nn(cq, vu10, vu11)
 117       end subroutine test_xvf16ger2nn
 118
 119 !CHECK-LABEL: @test_xvf16ger2nn_
 120 ! LLVMIR:         %[[VAL_40:.*]] = alloca <16 x i8>, i64 1, align 16
 121 ! LLVMIR:         %[[VAL_41:.*]] = alloca <16 x i8>, i64 1, align 16
 122 ! LLVMIR:         %[[VAL_42:.*]] = alloca <512 x i1>, i64 1, align 64
 123 ! LLVMIR:         %[[VAL_43:.*]] = load <16 x i8>, ptr %[[VAL_41]], align 16
 124 ! LLVMIR:         %[[VAL_44:.*]] = load <16 x i8>, ptr %[[VAL_40]], align 16
 125 ! LLVMIR:         %[[VAL_45:.*]] = load <512 x i1>, ptr %[[VAL_42]], align 64
 126 ! LLVMIR:         %[[VAL_46:.*]] = call <512 x i1> @llvm.ppc.mma.xvf16ger2nn(<512 x i1> %[[VAL_45]], <16 x i8> %[[VAL_43]], <16 x i8> %[[VAL_44]])
 127 ! LLVMIR:         store <512 x i1> %[[VAL_46]], ptr %[[VAL_42]], align 64
 128
 129       subroutine test_xvf16ger2np()
 130       use, intrinsic :: mma
 131       implicit none
 132       vector(unsigned(1)) vu10, vu11
 133       __vector_quad :: cq
 134       call mma_xvf16ger2np(cq, vu10, vu11)
 135       end subroutine test_xvf16ger2np
 136
 137 !CHECK-LABEL: @test_xvf16ger2np_
 138 ! LLVMIR:         %[[VAL_47:.*]] = alloca <16 x i8>, i64 1, align 16
 139 ! LLVMIR:         %[[VAL_48:.*]] = alloca <16 x i8>, i64 1, align 16
 140 ! LLVMIR:         %[[VAL_49:.*]] = alloca <512 x i1>, i64 1, align 64
 141 ! LLVMIR:         %[[VAL_50:.*]] = load <16 x i8>, ptr %[[VAL_48]], align 16
 142 ! LLVMIR:         %[[VAL_51:.*]] = load <16 x i8>, ptr %[[VAL_47]], align 16
 143 ! LLVMIR:         %[[VAL_52:.*]] = load <512 x i1>, ptr %[[VAL_49]], align 64
 144 ! LLVMIR:         %[[VAL_53:.*]] = call <512 x i1> @llvm.ppc.mma.xvf16ger2np(<512 x i1> %[[VAL_52]], <16 x i8> %[[VAL_50]], <16 x i8> %[[VAL_51]])
 145 ! LLVMIR:         store <512 x i1> %[[VAL_53]], ptr %[[VAL_49]], align 64
 146
 147       subroutine test_xvf16ger2pn()
 148       use, intrinsic :: mma
 149       implicit none
 150       vector(unsigned(1)) vu10, vu11
 151       __vector_quad :: cq
 152       call mma_xvf16ger2pn(cq, vu10, vu11)
 153       end subroutine test_xvf16ger2pn
 154
 155 !CHECK-LABEL: @test_xvf16ger2pn_
 156 ! LLVMIR:         %[[VAL_54:.*]] = alloca <16 x i8>, i64 1, align 16
 157 ! LLVMIR:         %[[VAL_55:.*]] = alloca <16 x i8>, i64 1, align 16
 158 ! LLVMIR:         %[[VAL_56:.*]] = alloca <512 x i1>, i64 1, align 64
 159 ! LLVMIR:         %[[VAL_57:.*]] = load <16 x i8>, ptr %[[VAL_55]], align 16
 160 ! LLVMIR:         %[[VAL_58:.*]] = load <16 x i8>, ptr %[[VAL_54]], align 16
 161 ! LLVMIR:         %[[VAL_59:.*]] = load <512 x i1>, ptr %[[VAL_56]], align 64
 162 ! LLVMIR:         %[[VAL_60:.*]] = call <512 x i1> @llvm.ppc.mma.xvf16ger2pn(<512 x i1> %[[VAL_59]], <16 x i8> %[[VAL_57]], <16 x i8> %[[VAL_58]])
 163 ! LLVMIR:         store <512 x i1> %[[VAL_60]], ptr %[[VAL_56]], align 64
 164
 165       subroutine test_xvf16ger2pp()
 166       use, intrinsic :: mma
 167       implicit none
 168       vector(unsigned(1)) vu10, vu11
 169       __vector_quad :: cq
 170       call mma_xvf16ger2pp(cq, vu10, vu11)
 171       end subroutine test_xvf16ger2pp
 172
 173 !CHECK-LABEL: @test_xvf16ger2pp_
 174 ! LLVMIR:         %[[VAL_61:.*]] = alloca <16 x i8>, i64 1, align 16
 175 ! LLVMIR:         %[[VAL_62:.*]] = alloca <16 x i8>, i64 1, align 16
 176 ! LLVMIR:         %[[VAL_63:.*]] = alloca <512 x i1>, i64 1, align 64
 177 ! LLVMIR:         %[[VAL_64:.*]] = load <16 x i8>, ptr %[[VAL_62]], align 16
 178 ! LLVMIR:         %[[VAL_65:.*]] = load <16 x i8>, ptr %[[VAL_61]], align 16
 179 ! LLVMIR:         %[[VAL_66:.*]] = load <512 x i1>, ptr %[[VAL_63]], align 64
 180 ! LLVMIR:         %[[VAL_67:.*]] = call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %[[VAL_66]], <16 x i8> %[[VAL_64]], <16 x i8> %[[VAL_65]])
 181 ! LLVMIR:         store <512 x i1> %[[VAL_67]], ptr %[[VAL_63]], align 64
 182
 183       subroutine test_xvf32ger_u1()
 184       use, intrinsic :: mma
 185       implicit none
 186       vector(unsigned(1)) vu10, vu11
 187       __vector_quad :: cq
 188       call mma_xvf32ger(cq, vu10, vu11)
 189       end subroutine test_xvf32ger_u1
 190
 191 !CHECK-LABEL: @test_xvf32ger_u1_
 192 ! LLVMIR:         %[[VAL_68:.*]] = alloca <16 x i8>, i64 1, align 16
 193 ! LLVMIR:         %[[VAL_69:.*]] = alloca <16 x i8>, i64 1, align 16
 194 ! LLVMIR:         %[[VAL_70:.*]] = alloca <512 x i1>, i64 1, align 64
 195 ! LLVMIR:         %[[VAL_71:.*]] = load <16 x i8>, ptr %[[VAL_69]], align 16
 196 ! LLVMIR:         %[[VAL_72:.*]] = load <16 x i8>, ptr %[[VAL_68]], align 16
 197 ! LLVMIR:         %[[VAL_73:.*]] = call <512 x i1> @llvm.ppc.mma.xvf32ger(<16 x i8> %[[VAL_71]], <16 x i8> %[[VAL_72]])
 198 ! LLVMIR:         store <512 x i1> %[[VAL_73]], ptr %[[VAL_70]], align 64
 199
 200
 201       subroutine test_xvf32ger_r4()
 202       use, intrinsic :: mma
 203       implicit none
 204       vector(real(4)) vr40, vr41
 205       __vector_quad :: cq
 206       call mma_xvf32ger(cq, vr40, vr41)
 207       end subroutine test_xvf32ger_r4
 208
 209 !CHECK-LABEL: @test_xvf32ger_r4_
 210 ! LLVMIR:         %[[VAL_74:.*]] = alloca <4 x float>, i64 1, align 16
 211 ! LLVMIR:         %[[VAL_75:.*]] = alloca <4 x float>, i64 1, align 16
 212 ! LLVMIR:         %[[VAL_76:.*]] = alloca <512 x i1>, i64 1, align 64
 213 ! LLVMIR:         %[[VAL_77:.*]] = load <4 x float>, ptr %[[VAL_75]], align 16
 214 ! LLVMIR:         %[[VAL_78:.*]] = load <4 x float>, ptr %[[VAL_74]], align 16
 215 ! LLVMIR:         %[[VAL_79:.*]] = bitcast <4 x float> %[[VAL_77]] to <16 x i8>
 216 ! LLVMIR:         %[[VAL_80:.*]] = bitcast <4 x float> %[[VAL_78]] to <16 x i8>
 217 ! LLVMIR:         %[[VAL_81:.*]] = call <512 x i1> @llvm.ppc.mma.xvf32ger(<16 x i8> %[[VAL_79]], <16 x i8> %[[VAL_80]])
 218 ! LLVMIR:         store <512 x i1> %[[VAL_81]], ptr %[[VAL_76]], align 64
 219
 220       subroutine test_xvf32gernn_u1()
 221       use, intrinsic :: mma
 222       implicit none
 223       vector(unsigned(1)) vu10, vu11
 224       __vector_quad :: cq
 225       call mma_xvf32gernn(cq, vu10, vu11)
 226       end subroutine test_xvf32gernn_u1
 227
 228 !CHECK-LABEL: @test_xvf32gernn_u1_
 229 ! LLVMIR:         %[[VAL_82:.*]] = alloca <16 x i8>, i64 1, align 16
 230 ! LLVMIR:         %[[VAL_83:.*]] = alloca <16 x i8>, i64 1, align 16
 231 ! LLVMIR:         %[[VAL_84:.*]] = alloca <512 x i1>, i64 1, align 64
 232 ! LLVMIR:         %[[VAL_85:.*]] = load <16 x i8>, ptr %[[VAL_83]], align 16
 233 ! LLVMIR:         %[[VAL_86:.*]] = load <16 x i8>, ptr %[[VAL_82]], align 16
 234 ! LLVMIR:         %[[VAL_87:.*]] = load <512 x i1>, ptr %[[VAL_84]], align 64
 235 ! LLVMIR:         %[[VAL_88:.*]] = call <512 x i1> @llvm.ppc.mma.xvf32gernn(<512 x i1> %[[VAL_87]], <16 x i8> %[[VAL_85]], <16 x i8> %[[VAL_86]])
 236 ! LLVMIR:         store <512 x i1> %[[VAL_88]], ptr %[[VAL_84]], align 64
 237
 238       subroutine test_xvf32gernn_r4()
 239       use, intrinsic :: mma
 240       implicit none
 241       vector(real(4)) vr40, vr41
 242       __vector_quad :: cq
 243       call mma_xvf32gernn(cq, vr40, vr41)
 244       end subroutine test_xvf32gernn_r4
 245
 246 !CHECK-LABEL: @test_xvf32gernn_r4_
 247 ! LLVMIR:         %[[VAL_89:.*]] = alloca <4 x float>, i64 1, align 16
 248 ! LLVMIR:         %[[VAL_90:.*]] = alloca <4 x float>, i64 1, align 16
 249 ! LLVMIR:         %[[VAL_91:.*]] = alloca <512 x i1>, i64 1, align 64
 250 ! LLVMIR:         %[[VAL_92:.*]] = load <4 x float>, ptr %[[VAL_90]], align 16
 251 ! LLVMIR:         %[[VAL_93:.*]] = load <4 x float>, ptr %[[VAL_89]], align 16
 252 ! LLVMIR:         %[[VAL_94:.*]] = load <512 x i1>, ptr %[[VAL_91]], align 64
 253 ! LLVMIR:         %[[VAL_95:.*]] = bitcast <4 x float> %[[VAL_92]] to <16 x i8>
 254 ! LLVMIR:         %[[VAL_96:.*]] = bitcast <4 x float> %[[VAL_93]] to <16 x i8>
 255 ! LLVMIR:         %[[VAL_97:.*]] = call <512 x i1> @llvm.ppc.mma.xvf32gernn(<512 x i1> %[[VAL_94]], <16 x i8> %[[VAL_95]], <16 x i8> %[[VAL_96]])
 256 ! LLVMIR:         store <512 x i1> %[[VAL_97]], ptr %[[VAL_91]], align 64
 257
 258       subroutine test_xvf32gernp_u1()
 259       use, intrinsic :: mma
 260       implicit none
 261       vector(unsigned(1)) vu10, vu11
 262       __vector_quad :: cq
 263       call mma_xvf32gernp(cq, vu10, vu11)
 264       end subroutine test_xvf32gernp_u1
 265
 266 !CHECK-LABEL: @test_xvf32gernp_u1_
 267 ! LLVMIR:         %[[VAL_98:.*]] = alloca <16 x i8>, i64 1, align 16
 268 ! LLVMIR:         %[[VAL_99:.*]] = alloca <16 x i8>, i64 1, align 16
 269 ! LLVMIR:         %[[VAL_100:.*]] = alloca <512 x i1>, i64 1, align 64
 270 ! LLVMIR:         %[[VAL_101:.*]] = load <16 x i8>, ptr %[[VAL_99]], align 16
 271 ! LLVMIR:         %[[VAL_102:.*]] = load <16 x i8>, ptr %[[VAL_98]], align 16
 272 ! LLVMIR:         %[[VAL_103:.*]] = load <512 x i1>, ptr %[[VAL_100]], align 64
 273 ! LLVMIR:         %[[VAL_104:.*]] = call <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1> %[[VAL_103]], <16 x i8> %[[VAL_101]], <16 x i8> %[[VAL_102]])
 274 ! LLVMIR:         store <512 x i1> %[[VAL_104]], ptr %[[VAL_100]], align 64
 275
 276       subroutine test_xvf32gernp_r4()
 277       use, intrinsic :: mma
 278       implicit none
 279       vector(real(4)) vr40, vr41
 280       __vector_quad :: cq
 281       call mma_xvf32gernp(cq, vr40, vr41)
 282       end subroutine test_xvf32gernp_r4
 283
 284 !CHECK-LABEL: @test_xvf32gernp_r4_
 285 ! LLVMIR:         %[[VAL_105:.*]] = alloca <4 x float>, i64 1, align 16
 286 ! LLVMIR:         %[[VAL_106:.*]] = alloca <4 x float>, i64 1, align 16
 287 ! LLVMIR:         %[[VAL_107:.*]] = alloca <512 x i1>, i64 1, align 64
 288 ! LLVMIR:         %[[VAL_108:.*]] = load <4 x float>, ptr %[[VAL_106]], align 16
 289 ! LLVMIR:         %[[VAL_109:.*]] = load <4 x float>, ptr %[[VAL_105]], align 16
 290 ! LLVMIR:         %[[VAL_110:.*]] = load <512 x i1>, ptr %[[VAL_107]], align 64
 291 ! LLVMIR:         %[[VAL_111:.*]] = bitcast <4 x float> %[[VAL_108]] to <16 x i8>
 292 ! LLVMIR:         %[[VAL_112:.*]] = bitcast <4 x float> %[[VAL_109]] to <16 x i8>
 293 ! LLVMIR:         %[[VAL_113:.*]] = call <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1> %[[VAL_110]], <16 x i8> %[[VAL_111]], <16 x i8> %[[VAL_112]])
 294 ! LLVMIR:         store <512 x i1> %[[VAL_113]], ptr %[[VAL_107]], align 64
 295
 296       subroutine test_xvf32gerpn_u1()
 297       use, intrinsic :: mma
 298       implicit none
 299       vector(unsigned(1)) vu10, vu11
 300       __vector_quad :: cq
 301       call mma_xvf32gerpn(cq, vu10, vu11)
 302       end subroutine test_xvf32gerpn_u1
 303
 304 !CHECK-LABEL: @test_xvf32gerpn_u1_
 305 ! LLVMIR:         %[[VAL_114:.*]] = alloca <16 x i8>, i64 1, align 16
 306 ! LLVMIR:         %[[VAL_115:.*]] = alloca <16 x i8>, i64 1, align 16
 307 ! LLVMIR:         %[[VAL_116:.*]] = alloca <512 x i1>, i64 1, align 64
 308 ! LLVMIR:         %[[VAL_117:.*]] = load <16 x i8>, ptr %[[VAL_115]], align 16
 309 ! LLVMIR:         %[[VAL_118:.*]] = load <16 x i8>, ptr %[[VAL_114]], align 16
 310 ! LLVMIR:         %[[VAL_119:.*]] = load <512 x i1>, ptr %[[VAL_116]], align 64
 311 ! LLVMIR:         %[[VAL_120:.*]] = call <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1> %[[VAL_119]], <16 x i8> %[[VAL_117]], <16 x i8> %[[VAL_118]])
 312 ! LLVMIR:         store <512 x i1> %[[VAL_120]], ptr %[[VAL_116]], align 64
 313
 314       subroutine test_xvf32gerpn_r4()
 315       use, intrinsic :: mma
 316       implicit none
 317       vector(real(4)) vr40, vr41
 318       __vector_quad :: cq
 319       call mma_xvf32gerpn(cq, vr40, vr41)
 320       end subroutine test_xvf32gerpn_r4
 321
 322 !CHECK-LABEL: @test_xvf32gerpn_r4_
 323 ! LLVMIR:         %[[VAL_121:.*]] = alloca <4 x float>, i64 1, align 16
 324 ! LLVMIR:         %[[VAL_122:.*]] = alloca <4 x float>, i64 1, align 16
 325 ! LLVMIR:         %[[VAL_123:.*]] = alloca <512 x i1>, i64 1, align 64
 326 ! LLVMIR:         %[[VAL_124:.*]] = load <4 x float>, ptr %[[VAL_122]], align 16
 327 ! LLVMIR:         %[[VAL_125:.*]] = load <4 x float>, ptr %[[VAL_121]], align 16
 328 ! LLVMIR:         %[[VAL_126:.*]] = load <512 x i1>, ptr %[[VAL_123]], align 64
 329 ! LLVMIR:         %[[VAL_127:.*]] = bitcast <4 x float> %[[VAL_124]] to <16 x i8>
 330 ! LLVMIR:         %[[VAL_128:.*]] = bitcast <4 x float> %[[VAL_125]] to <16 x i8>
 331 ! LLVMIR:         %[[VAL_129:.*]] = call <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1> %[[VAL_126]], <16 x i8> %[[VAL_127]], <16 x i8> %[[VAL_128]])
 332 ! LLVMIR:         store <512 x i1> %[[VAL_129]], ptr %[[VAL_123]], align 64
 333
 334       subroutine test_xvf32gerpp_u1()
 335       use, intrinsic :: mma
 336       implicit none
 337       vector(unsigned(1)) vu10, vu11
 338       __vector_quad :: cq
 339       call mma_xvf32gerpp(cq, vu10, vu11)
 340       end subroutine test_xvf32gerpp_u1
 341
 342 !CHECK-LABEL: @test_xvf32gerpp_u1_
 343 ! LLVMIR:         %[[VAL_130:.*]] = alloca <16 x i8>, i64 1, align 16
 344 ! LLVMIR:         %[[VAL_131:.*]] = alloca <16 x i8>, i64 1, align 16
 345 ! LLVMIR:         %[[VAL_132:.*]] = alloca <512 x i1>, i64 1, align 64
 346 ! LLVMIR:         %[[VAL_133:.*]] = load <16 x i8>, ptr %[[VAL_131]], align 16
 347 ! LLVMIR:         %[[VAL_134:.*]] = load <16 x i8>, ptr %[[VAL_130]], align 16
 348 ! LLVMIR:         %[[VAL_135:.*]] = load <512 x i1>, ptr %[[VAL_132]], align 64
 349 ! LLVMIR:         %[[VAL_136:.*]] = call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %[[VAL_135]], <16 x i8> %[[VAL_133]], <16 x i8> %[[VAL_134]])
 350 ! LLVMIR:         store <512 x i1> %[[VAL_136]], ptr %[[VAL_132]], align 64
 351
 352
 353       subroutine test_xvf32gerpp_r4()
 354       use, intrinsic :: mma
 355       implicit none
 356       vector(real(4)) vr40, vr41
 357       __vector_quad :: cq
 358       call mma_xvf32gerpp(cq, vr40, vr41)
 359       end subroutine test_xvf32gerpp_r4
 360
 361 !CHECK-LABEL: @test_xvf32gerpp_r4_
 362 ! LLVMIR:         %[[VAL_137:.*]] = alloca <4 x float>, i64 1, align 16
 363 ! LLVMIR:         %[[VAL_138:.*]] = alloca <4 x float>, i64 1, align 16
 364 ! LLVMIR:         %[[VAL_139:.*]] = alloca <512 x i1>, i64 1, align 64
 365 ! LLVMIR:         %[[VAL_140:.*]] = load <4 x float>, ptr %[[VAL_138]], align 16
 366 ! LLVMIR:         %[[VAL_141:.*]] = load <4 x float>, ptr %[[VAL_137]], align 16
 367 ! LLVMIR:         %[[VAL_142:.*]] = load <512 x i1>, ptr %[[VAL_139]], align 64
 368 ! LLVMIR:         %[[VAL_143:.*]] = bitcast <4 x float> %[[VAL_140]] to <16 x i8>
 369 ! LLVMIR:         %[[VAL_144:.*]] = bitcast <4 x float> %[[VAL_141]] to <16 x i8>
 370 ! LLVMIR:         %[[VAL_145:.*]] = call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %[[VAL_142]], <16 x i8> %[[VAL_143]], <16 x i8> %[[VAL_144]])
 371 ! LLVMIR:         store <512 x i1> %[[VAL_145]], ptr %[[VAL_139]], align 64
 372
 373       subroutine test_xvf64ger_u1()
 374       use, intrinsic :: mma
 375       implicit none
 376       vector(unsigned(1)) vu10
 377       __vector_quad :: cq
 378       __vector_pair :: cp
 379       call mma_xvf64ger(cq, cp, vu10)
 380       end subroutine test_xvf64ger_u1
 381
 382 !CHECK-LABEL: @test_xvf64ger_u1_
 383 ! LLVMIR:         %[[VAL_146:.*]] = alloca <16 x i8>, i64 1, align 16
 384 ! LLVMIR:         %[[VAL_147:.*]] = alloca <512 x i1>, i64 1, align 64
 385 ! LLVMIR:         %[[VAL_148:.*]] = alloca <256 x i1>, i64 1, align 32
 386 ! LLVMIR:         %[[VAL_149:.*]] = load <256 x i1>, ptr %[[VAL_148]], align 32
 387 ! LLVMIR:         %[[VAL_150:.*]] = load <16 x i8>, ptr %[[VAL_146]], align 16
 388 ! LLVMIR:         %[[VAL_151:.*]] = call <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1> %[[VAL_149]], <16 x i8> %[[VAL_150]])
 389 ! LLVMIR:         store <512 x i1> %[[VAL_151]], ptr %[[VAL_147]], align 64
 390
 391       subroutine test_xvf64ger_r8()
 392       use, intrinsic :: mma
 393       implicit none
 394       vector(real(8)) vr80
 395       __vector_quad :: cq
 396       __vector_pair :: cp
 397       call mma_xvf64ger(cq, cp, vr80)
 398       end subroutine test_xvf64ger_r8
 399
 400 !CHECK-LABEL: @test_xvf64ger_r8_
 401 ! LLVMIR:         %[[VAL_152:.*]] = alloca <2 x double>, i64 1, align 16
 402 ! LLVMIR:         %[[VAL_153:.*]] = alloca <512 x i1>, i64 1, align 64
 403 ! LLVMIR:         %[[VAL_154:.*]] = alloca <256 x i1>, i64 1, align 32
 404 ! LLVMIR:         %[[VAL_155:.*]] = load <256 x i1>, ptr %[[VAL_154]], align 32
 405 ! LLVMIR:         %[[VAL_156:.*]] = load <2 x double>, ptr %[[VAL_152]], align 16
 406 ! LLVMIR:         %[[VAL_157:.*]] = bitcast <2 x double> %[[VAL_156]] to <16 x i8>
 407 ! LLVMIR:         %[[VAL_158:.*]] = call <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1> %[[VAL_155]], <16 x i8> %[[VAL_157]])
 408 ! LLVMIR:         store <512 x i1> %[[VAL_158]], ptr %[[VAL_153]], align 64
 409
 410
 411       subroutine test_xvf64gernn_u1()
 412       use, intrinsic :: mma
 413       implicit none
 414       vector(unsigned(1)) vu10
 415       __vector_quad :: cq
 416       __vector_pair :: cp
 417       call mma_xvf64gernn(cq, cp, vu10)
 418       end subroutine test_xvf64gernn_u1
 419
 420 !CHECK-LABEL: @test_xvf64gernn_u1_
 421 ! LLVMIR:         %[[VAL_159:.*]] = alloca <16 x i8>, i64 1, align 16
 422 ! LLVMIR:         %[[VAL_160:.*]] = alloca <512 x i1>, i64 1, align 64
 423 ! LLVMIR:         %[[VAL_161:.*]] = alloca <256 x i1>, i64 1, align 32
 424 ! LLVMIR:         %[[VAL_162:.*]] = load <256 x i1>, ptr %[[VAL_161]], align 32
 425 ! LLVMIR:         %[[VAL_163:.*]] = load <16 x i8>, ptr %[[VAL_159]], align 16
 426 ! LLVMIR:         %[[VAL_164:.*]] = load <512 x i1>, ptr %[[VAL_160]], align 64
 427 ! LLVMIR:         %[[VAL_165:.*]] = call <512 x i1> @llvm.ppc.mma.xvf64gernn(<512 x i1> %[[VAL_164]], <256 x i1> %[[VAL_162]], <16 x i8> %[[VAL_163]])
 428 ! LLVMIR:         store <512 x i1> %[[VAL_165]], ptr %[[VAL_160]], align 64
 429
 430
 431       subroutine test_xvf64gernn_r8()
 432       use, intrinsic :: mma
 433       implicit none
 434       vector(real(8)) vr80
 435       __vector_quad :: cq
 436       __vector_pair :: cp
 437       call mma_xvf64gernn(cq, cp, vr80)
 438       end subroutine test_xvf64gernn_r8
 439
 440 !CHECK-LABEL: @test_xvf64gernn_r8_
 441 ! LLVMIR:         %[[VAL_166:.*]] = alloca <2 x double>, i64 1, align 16
 442 ! LLVMIR:         %[[VAL_167:.*]] = alloca <512 x i1>, i64 1, align 64
 443 ! LLVMIR:         %[[VAL_168:.*]] = alloca <256 x i1>, i64 1, align 32
 444 ! LLVMIR:         %[[VAL_169:.*]] = load <256 x i1>, ptr %[[VAL_168]], align 32
 445 ! LLVMIR:         %[[VAL_170:.*]] = load <2 x double>, ptr %[[VAL_166]], align 16
 446 ! LLVMIR:         %[[VAL_171:.*]] = load <512 x i1>, ptr %[[VAL_167]], align 64
 447 ! LLVMIR:         %[[VAL_172:.*]] = bitcast <2 x double> %[[VAL_170]] to <16 x i8>
 448 ! LLVMIR:         %[[VAL_173:.*]] = call <512 x i1> @llvm.ppc.mma.xvf64gernn(<512 x i1> %[[VAL_171]], <256 x i1> %[[VAL_169]], <16 x i8> %[[VAL_172]])
 449 ! LLVMIR:         store <512 x i1> %[[VAL_173]], ptr %[[VAL_167]], align 64
 450
 451       subroutine test_xvf64gernp_u1()
 452       use, intrinsic :: mma
 453       implicit none
 454       vector(unsigned(1)) vu10
 455       __vector_quad :: cq
 456       __vector_pair :: cp
 457       call mma_xvf64gernp(cq, cp, vu10)
 458       end subroutine test_xvf64gernp_u1
 459
 460 !CHECK-LABEL: @test_xvf64gernp_u1_
 461 ! LLVMIR:         %[[VAL_174:.*]] = alloca <16 x i8>, i64 1, align 16
 462 ! LLVMIR:         %[[VAL_175:.*]] = alloca <512 x i1>, i64 1, align 64
 463 ! LLVMIR:         %[[VAL_176:.*]] = alloca <256 x i1>, i64 1, align 32
 464 ! LLVMIR:         %[[VAL_177:.*]] = load <256 x i1>, ptr %[[VAL_176]], align 32
 465 ! LLVMIR:         %[[VAL_178:.*]] = load <16 x i8>, ptr %[[VAL_174]], align 16
 466 ! LLVMIR:         %[[VAL_179:.*]] = load <512 x i1>, ptr %[[VAL_175]], align 64
 467 ! LLVMIR:         %[[VAL_180:.*]] = call <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1> %[[VAL_179]], <256 x i1> %[[VAL_177]], <16 x i8> %[[VAL_178]])
 468 ! LLVMIR:         store <512 x i1> %[[VAL_180]], ptr %[[VAL_175]], align 64
 469
 470       subroutine test_xvf64gernp_r8()
 471       use, intrinsic :: mma
 472       implicit none
 473       vector(unsigned(1)) vr80
 474       __vector_quad :: cq
 475       __vector_pair :: cp
 476       call mma_xvf64gernp(cq, cp, vr80)
 477       end subroutine test_xvf64gernp_r8
 478
 479 !CHECK-LABEL: @test_xvf64gernp_r8_
 480 ! LLVMIR:         %[[VAL_181:.*]] = alloca <16 x i8>, i64 1, align 16
 481 ! LLVMIR:         %[[VAL_182:.*]] = alloca <512 x i1>, i64 1, align 64
 482 ! LLVMIR:         %[[VAL_183:.*]] = alloca <256 x i1>, i64 1, align 32
 483 ! LLVMIR:         %[[VAL_184:.*]] = load <256 x i1>, ptr %[[VAL_183]], align 32
 484 ! LLVMIR:         %[[VAL_185:.*]] = load <16 x i8>, ptr %[[VAL_181]], align 16
 485 ! LLVMIR:         %[[VAL_186:.*]] = load <512 x i1>, ptr %[[VAL_182]], align 64
 486 ! LLVMIR:         %[[VAL_187:.*]] = call <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1> %[[VAL_186]], <256 x i1> %[[VAL_184]], <16 x i8> %[[VAL_185]])
 487 ! LLVMIR:         store <512 x i1> %[[VAL_187]], ptr %[[VAL_182]], align 64
 488
 489       subroutine test_xvf64gerpn_u1()
 490       use, intrinsic :: mma
 491       implicit none
 492       vector(unsigned(1)) vu10
 493       __vector_quad :: cq
 494       __vector_pair :: cp
 495       call mma_xvf64gerpn(cq, cp, vu10)
 496       end subroutine test_xvf64gerpn_u1
 497
 498 !CHECK-LABEL: @test_xvf64gerpn_u1_
 499 ! LLVMIR:         %[[VAL_188:.*]] = alloca <16 x i8>, i64 1, align 16
 500 ! LLVMIR:         %[[VAL_189:.*]] = alloca <512 x i1>, i64 1, align 64
 501 ! LLVMIR:         %[[VAL_190:.*]] = alloca <256 x i1>, i64 1, align 32
 502 ! LLVMIR:         %[[VAL_191:.*]] = load <256 x i1>, ptr %[[VAL_190]], align 32
 503 ! LLVMIR:         %[[VAL_192:.*]] = load <16 x i8>, ptr %[[VAL_188]], align 16
 504 ! LLVMIR:         %[[VAL_193:.*]] = load <512 x i1>, ptr %[[VAL_189]], align 64
 505 ! LLVMIR:         %[[VAL_194:.*]] = call <512 x i1> @llvm.ppc.mma.xvf64gerpn(<512 x i1> %[[VAL_193]], <256 x i1> %[[VAL_191]], <16 x i8> %[[VAL_192]])
 506 ! LLVMIR:         store <512 x i1> %[[VAL_194]], ptr %[[VAL_189]], align 64
 507
 508       subroutine test_xvf64gerpn_r8()
 509       use, intrinsic :: mma
 510       implicit none
 511       vector(real(8)) vr80
 512       __vector_quad :: cq
 513       __vector_pair :: cp
 514       call mma_xvf64gerpn(cq, cp, vr80)
 515       end subroutine test_xvf64gerpn_r8
 516
 517 !CHECK-LABEL: @test_xvf64gerpn_r8_
 518 ! LLVMIR:         %[[VAL_195:.*]] = alloca <2 x double>, i64 1, align 16
 519 ! LLVMIR:         %[[VAL_196:.*]] = alloca <512 x i1>, i64 1, align 64
 520 ! LLVMIR:         %[[VAL_197:.*]] = alloca <256 x i1>, i64 1, align 32
 521 ! LLVMIR:         %[[VAL_198:.*]] = load <256 x i1>, ptr %[[VAL_197]], align 32
 522 ! LLVMIR:         %[[VAL_199:.*]] = load <2 x double>, ptr %[[VAL_195]], align 16
 523 ! LLVMIR:         %[[VAL_200:.*]] = load <512 x i1>, ptr %[[VAL_196]], align 64
 524 ! LLVMIR:         %[[VAL_201:.*]] = bitcast <2 x double> %[[VAL_199]] to <16 x i8>
 525 ! LLVMIR:         %[[VAL_202:.*]] = call <512 x i1> @llvm.ppc.mma.xvf64gerpn(<512 x i1> %[[VAL_200]], <256 x i1> %[[VAL_198]], <16 x i8> %[[VAL_201]])
 526 ! LLVMIR:         store <512 x i1> %[[VAL_202]], ptr %[[VAL_196]], align 64
 527
 528       subroutine test_xvf64gerpp_u1()
 529       use, intrinsic :: mma
 530       implicit none
 531       vector(unsigned(1)) vu10
 532       __vector_quad :: cq
 533       __vector_pair :: cp
 534       call mma_xvf64gerpp(cq, cp, vu10)
 535       end subroutine test_xvf64gerpp_u1
 536
 537 !CHECK-LABEL: @test_xvf64gerpp_u1_
 538 ! LLVMIR:         %[[VAL_203:.*]] = alloca <16 x i8>, i64 1, align 16
 539 ! LLVMIR:         %[[VAL_204:.*]] = alloca <512 x i1>, i64 1, align 64
 540 ! LLVMIR:         %[[VAL_205:.*]] = alloca <256 x i1>, i64 1, align 32
 541 ! LLVMIR:         %[[VAL_206:.*]] = load <256 x i1>, ptr %[[VAL_205]], align 32
 542 ! LLVMIR:         %[[VAL_207:.*]] = load <16 x i8>, ptr %[[VAL_203]], align 16
 543 ! LLVMIR:         %[[VAL_208:.*]] = load <512 x i1>, ptr %[[VAL_204]], align 64
 544 ! LLVMIR:         %[[VAL_209:.*]] = call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %[[VAL_208]], <256 x i1> %[[VAL_206]], <16 x i8> %[[VAL_207]])
 545 ! LLVMIR:         store <512 x i1> %[[VAL_209]], ptr %[[VAL_204]], align 64
 546
 547
 548       subroutine test_xvf64gerpp_r8()
 549       use, intrinsic :: mma
 550       implicit none
 551       vector(real(8)) vr80
 552       __vector_quad :: cq
 553       __vector_pair :: cp
 554       call mma_xvf64gerpp(cq, cp, vr80)
 555       end subroutine test_xvf64gerpp_r8
 556
 557 !CHECK-LABEL: @test_xvf64gerpp_r8_
 558 ! LLVMIR:         %[[VAL_210:.*]] = alloca <2 x double>, i64 1, align 16
 559 ! LLVMIR:         %[[VAL_211:.*]] = alloca <512 x i1>, i64 1, align 64
 560 ! LLVMIR:         %[[VAL_212:.*]] = alloca <256 x i1>, i64 1, align 32
 561 ! LLVMIR:         %[[VAL_213:.*]] = load <256 x i1>, ptr %[[VAL_212]], align 32
 562 ! LLVMIR:         %[[VAL_214:.*]] = load <2 x double>, ptr %[[VAL_210]], align 16
 563 ! LLVMIR:         %[[VAL_215:.*]] = load <512 x i1>, ptr %[[VAL_211]], align 64
 564 ! LLVMIR:         %[[VAL_216:.*]] = bitcast <2 x double> %[[VAL_214]] to <16 x i8>
 565 ! LLVMIR:         %[[VAL_217:.*]] = call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %[[VAL_215]], <256 x i1> %[[VAL_213]], <16 x i8> %[[VAL_216]])
 566 ! LLVMIR:         store <512 x i1> %[[VAL_217]], ptr %[[VAL_211]], align 64
 567
 568       subroutine test_xvi16ger2_u1()
 569       use, intrinsic :: mma
 570       implicit none
 571       vector(unsigned(1)) vu10, vu11
 572       __vector_quad :: cq
 573       call mma_xvi16ger2(cq, vu10, vu11)
 574       end subroutine test_xvi16ger2_u1
 575
 576 !CHECK-LABEL: @test_xvi16ger2_u1_
 577 ! LLVMIR:         %[[VAL_218:.*]] = alloca <16 x i8>, i64 1, align 16
 578 ! LLVMIR:         %[[VAL_219:.*]] = alloca <16 x i8>, i64 1, align 16
 579 ! LLVMIR:         %[[VAL_220:.*]] = alloca <512 x i1>, i64 1, align 64
 580 ! LLVMIR:         %[[VAL_221:.*]] = load <16 x i8>, ptr %[[VAL_219]], align 16
 581 ! LLVMIR:         %[[VAL_222:.*]] = load <16 x i8>, ptr %[[VAL_218]], align 16
 582 ! LLVMIR:         %[[VAL_223:.*]] = call <512 x i1> @llvm.ppc.mma.xvi16ger2(<16 x i8> %[[VAL_221]], <16 x i8> %[[VAL_222]])
 583 ! LLVMIR:         store <512 x i1> %[[VAL_223]], ptr %[[VAL_220]], align 64
 584
 585       subroutine test_xvi16ger2_i2()
 586       use, intrinsic :: mma
 587       implicit none
 588       vector(integer(2)) vi20, vi21
 589       __vector_quad :: cq
 590       call mma_xvi16ger2(cq, vi20, vi21)
 591       end subroutine test_xvi16ger2_i2
 592
 593 !CHECK-LABEL: @test_xvi16ger2_i2_
 594 ! LLVMIR:         %[[VAL_224:.*]] = alloca <8 x i16>, i64 1, align 16
 595 ! LLVMIR:         %[[VAL_225:.*]] = alloca <8 x i16>, i64 1, align 16
 596 ! LLVMIR:         %[[VAL_226:.*]] = alloca <512 x i1>, i64 1, align 64
 597 ! LLVMIR:         %[[VAL_227:.*]] = load <8 x i16>, ptr %[[VAL_225]], align 16
 598 ! LLVMIR:         %[[VAL_228:.*]] = load <8 x i16>, ptr %[[VAL_224]], align 16
 599 ! LLVMIR:         %[[VAL_229:.*]] = bitcast <8 x i16> %[[VAL_227]] to <16 x i8>
 600 ! LLVMIR:         %[[VAL_230:.*]] = bitcast <8 x i16> %[[VAL_228]] to <16 x i8>
 601 ! LLVMIR:         %[[VAL_231:.*]] = call <512 x i1> @llvm.ppc.mma.xvi16ger2(<16 x i8> %[[VAL_229]], <16 x i8> %[[VAL_230]])
 602 ! LLVMIR:         store <512 x i1> %[[VAL_231]], ptr %[[VAL_226]], align 64
 603
 604       subroutine test_xvi16ger2pp_u1()
 605       use, intrinsic :: mma
 606       implicit none
 607       vector(unsigned(1)) vu10, vu11
 608       __vector_quad :: cq
 609       call mma_xvi16ger2pp(cq, vu10, vu11)
 610       end subroutine test_xvi16ger2pp_u1
 611
 612 !CHECK-LABEL: @test_xvi16ger2pp_u1_
 613 ! LLVMIR:         %[[VAL_232:.*]] = alloca <16 x i8>, i64 1, align 16
 614 ! LLVMIR:         %[[VAL_233:.*]] = alloca <16 x i8>, i64 1, align 16
 615 ! LLVMIR:         %[[VAL_234:.*]] = alloca <512 x i1>, i64 1, align 64
 616 ! LLVMIR:         %[[VAL_235:.*]] = load <16 x i8>, ptr %[[VAL_233]], align 16
 617 ! LLVMIR:         %[[VAL_236:.*]] = load <16 x i8>, ptr %[[VAL_232]], align 16
 618 ! LLVMIR:         %[[VAL_237:.*]] = load <512 x i1>, ptr %[[VAL_234]], align 64
 619 ! LLVMIR:         %[[VAL_238:.*]] = call <512 x i1> @llvm.ppc.mma.xvi16ger2pp(<512 x i1> %[[VAL_237]], <16 x i8> %[[VAL_235]], <16 x i8> %[[VAL_236]])
 620 ! LLVMIR:         store <512 x i1> %[[VAL_238]], ptr %[[VAL_234]], align 64
 621
 622       subroutine test_xvi16ger2pp_i2()
 623       use, intrinsic :: mma
 624       implicit none
 625       vector(integer(2)) vi20, vi21
 626       __vector_quad :: cq
 627       call mma_xvi16ger2pp(cq, vi20, vi21)
 628       end subroutine test_xvi16ger2pp_i2
 629
 630 !CHECK-LABEL: @test_xvi16ger2pp_i2_
 631 ! LLVMIR:         %[[VAL_239:.*]] = alloca <8 x i16>, i64 1, align 16
 632 ! LLVMIR:         %[[VAL_240:.*]] = alloca <8 x i16>, i64 1, align 16
 633 ! LLVMIR:         %[[VAL_241:.*]] = alloca <512 x i1>, i64 1, align 64
 634 ! LLVMIR:         %[[VAL_242:.*]] = load <8 x i16>, ptr %[[VAL_240]], align 16
 635 ! LLVMIR:         %[[VAL_243:.*]] = load <8 x i16>, ptr %[[VAL_239]], align 16
 636 ! LLVMIR:         %[[VAL_244:.*]] = load <512 x i1>, ptr %[[VAL_241]], align 64
 637 ! LLVMIR:         %[[VAL_245:.*]] = bitcast <8 x i16> %[[VAL_242]] to <16 x i8>
 638 ! LLVMIR:         %[[VAL_246:.*]] = bitcast <8 x i16> %[[VAL_243]] to <16 x i8>
 639 ! LLVMIR:         %[[VAL_247:.*]] = call <512 x i1> @llvm.ppc.mma.xvi16ger2pp(<512 x i1> %[[VAL_244]], <16 x i8> %[[VAL_245]], <16 x i8> %[[VAL_246]])
 640 ! LLVMIR:         store <512 x i1> %[[VAL_247]], ptr %[[VAL_241]], align 64
 641
 642       subroutine test_xvi16ger2s_u1()
 643       use, intrinsic :: mma
 644       implicit none
 645       vector(unsigned(1)) vu10, vu11
 646       __vector_quad :: cq
 647       call mma_xvi16ger2s(cq, vu10, vu11)
 648       end subroutine test_xvi16ger2s_u1
 649
 650 !CHECK-LABEL:  @test_xvi16ger2s_u1_
 651 ! LLVMIR:         %[[VAL_248:.*]] = alloca <16 x i8>, i64 1, align 16
 652 ! LLVMIR:         %[[VAL_249:.*]] = alloca <16 x i8>, i64 1, align 16
 653 ! LLVMIR:         %[[VAL_250:.*]] = alloca <512 x i1>, i64 1, align 64
 654 ! LLVMIR:         %[[VAL_251:.*]] = load <16 x i8>, ptr %[[VAL_249]], align 16
 655 ! LLVMIR:         %[[VAL_252:.*]] = load <16 x i8>, ptr %[[VAL_248]], align 16
 656 ! LLVMIR:         %[[VAL_253:.*]] = call <512 x i1> @llvm.ppc.mma.xvi16ger2s(<16 x i8> %[[VAL_251]], <16 x i8> %[[VAL_252]])
 657 ! LLVMIR:         store <512 x i1> %[[VAL_253]], ptr %[[VAL_250]], align 64
 658
 659       subroutine test_xvi16ger2s_i2()
 660       use, intrinsic :: mma
 661       implicit none
 662       vector(integer(2)) vi20, vi21
 663       __vector_quad :: cq
 664       call mma_xvi16ger2s(cq, vi20, vi21)
 665       end subroutine test_xvi16ger2s_i2
 666
 667 !CHECK-LABEL:  @test_xvi16ger2s_i2_
 668 ! LLVMIR:         %[[VAL_254:.*]] = alloca <8 x i16>, i64 1, align 16
 669 ! LLVMIR:         %[[VAL_255:.*]] = alloca <8 x i16>, i64 1, align 16
 670 ! LLVMIR:         %[[VAL_256:.*]] = alloca <512 x i1>, i64 1, align 64
 671 ! LLVMIR:         %[[VAL_257:.*]] = load <8 x i16>, ptr %[[VAL_255]], align 16
 672 ! LLVMIR:         %[[VAL_258:.*]] = load <8 x i16>, ptr %[[VAL_254]], align 16
 673 ! LLVMIR:         %[[VAL_259:.*]] = bitcast <8 x i16> %[[VAL_257]] to <16 x i8>
 674 ! LLVMIR:         %[[VAL_260:.*]] = bitcast <8 x i16> %[[VAL_258]] to <16 x i8>
 675 ! LLVMIR:         %[[VAL_261:.*]] = call <512 x i1> @llvm.ppc.mma.xvi16ger2s(<16 x i8> %[[VAL_259]], <16 x i8> %[[VAL_260]])
 676 ! LLVMIR:         store <512 x i1> %[[VAL_261]], ptr %[[VAL_256]], align 64
 677
 678       subroutine test_xvi16ger2spp_u1()
 679       use, intrinsic :: mma
 680       implicit none
 681       vector(unsigned(1)) vu10, vu11
 682       __vector_quad :: cq
 683       call mma_xvi16ger2spp(cq, vu10, vu11)
 684       end subroutine test_xvi16ger2spp_u1
 685
 686 !CHECK-LABEL:  @test_xvi16ger2spp_u1_
 687 ! LLVMIR:         %[[VAL_262:.*]] = alloca <16 x i8>, i64 1, align 16
 688 ! LLVMIR:         %[[VAL_263:.*]] = alloca <16 x i8>, i64 1, align 16
 689 ! LLVMIR:         %[[VAL_264:.*]] = alloca <512 x i1>, i64 1, align 64
 690 ! LLVMIR:         %[[VAL_265:.*]] = load <16 x i8>, ptr %[[VAL_263]], align 16
 691 ! LLVMIR:         %[[VAL_266:.*]] = load <16 x i8>, ptr %[[VAL_262]], align 16
 692 ! LLVMIR:         %[[VAL_267:.*]] = load <512 x i1>, ptr %[[VAL_264]], align 64
 693 ! LLVMIR:         %[[VAL_268:.*]] = call <512 x i1> @llvm.ppc.mma.xvi16ger2spp(<512 x i1> %[[VAL_267]], <16 x i8> %[[VAL_265]], <16 x i8> %[[VAL_266]])
 694 ! LLVMIR:         store <512 x i1> %[[VAL_268]], ptr %[[VAL_264]], align 64
 695
 696       subroutine test_xvi16ger2spp_i2()
 697       use, intrinsic :: mma
 698       implicit none
 699       vector(integer(2)) vi20, vi21
 700       __vector_quad :: cq
 701       call mma_xvi16ger2spp(cq, vi20, vi21)
 702       end subroutine test_xvi16ger2spp_i2
 703
 704 !CHECK-LABEL:  @test_xvi16ger2spp_i2_
 705 ! LLVMIR:         %[[VAL_269:.*]] = alloca <8 x i16>, i64 1, align 16
 706 ! LLVMIR:         %[[VAL_270:.*]] = alloca <8 x i16>, i64 1, align 16
 707 ! LLVMIR:         %[[VAL_271:.*]] = alloca <512 x i1>, i64 1, align 64
 708 ! LLVMIR:         %[[VAL_272:.*]] = load <8 x i16>, ptr %[[VAL_270]], align 16
 709 ! LLVMIR:         %[[VAL_273:.*]] = load <8 x i16>, ptr %[[VAL_269]], align 16
 710 ! LLVMIR:         %[[VAL_274:.*]] = load <512 x i1>, ptr %[[VAL_271]], align 64
 711 ! LLVMIR:         %[[VAL_275:.*]] = bitcast <8 x i16> %[[VAL_272]] to <16 x i8>
 712 ! LLVMIR:         %[[VAL_276:.*]] = bitcast <8 x i16> %[[VAL_273]] to <16 x i8>
 713 ! LLVMIR:         %[[VAL_277:.*]] = call <512 x i1> @llvm.ppc.mma.xvi16ger2spp(<512 x i1> %[[VAL_274]], <16 x i8> %[[VAL_275]], <16 x i8> %[[VAL_276]])
 714 ! LLVMIR:         store <512 x i1> %[[VAL_277]], ptr %[[VAL_271]], align 64
 715
 716       subroutine test_xvi4ger8()
 717       use, intrinsic :: mma
 718       implicit none
 719       vector(unsigned(1)) vu10, vu11
 720       __vector_quad :: cq
 721       call mma_xvi4ger8(cq, vu10, vu11)
 722       end subroutine test_xvi4ger8
 723
 724 !CHECK-LABEL:  @test_xvi4ger8_
 725 ! LLVMIR:         %[[VAL_278:.*]] = alloca <16 x i8>, i64 1, align 16
 726 ! LLVMIR:         %[[VAL_279:.*]] = alloca <16 x i8>, i64 1, align 16
 727 ! LLVMIR:         %[[VAL_280:.*]] = alloca <512 x i1>, i64 1, align 64
 728 ! LLVMIR:         %[[VAL_281:.*]] = load <16 x i8>, ptr %[[VAL_279]], align 16
 729 ! LLVMIR:         %[[VAL_282:.*]] = load <16 x i8>, ptr %[[VAL_278]], align 16
 730 ! LLVMIR:         %[[VAL_283:.*]] = call <512 x i1> @llvm.ppc.mma.xvi4ger8(<16 x i8> %[[VAL_281]], <16 x i8> %[[VAL_282]])
 731 ! LLVMIR:         store <512 x i1> %[[VAL_283]], ptr %[[VAL_280]], align 64
 732
 733       subroutine test_xvi4ger8pp()
 734       use, intrinsic :: mma
 735       implicit none
 736       vector(unsigned(1)) vu10, vu11
 737       __vector_quad :: cq
 738       call mma_xvi4ger8pp(cq, vu10, vu11)
 739       end subroutine test_xvi4ger8pp
 740
 741 !CHECK-LABEL:  @test_xvi4ger8pp_
 742 ! LLVMIR:         %[[VAL_284:.*]] = alloca <16 x i8>, i64 1, align 16
 743 ! LLVMIR:         %[[VAL_285:.*]] = alloca <16 x i8>, i64 1, align 16
 744 ! LLVMIR:         %[[VAL_286:.*]] = alloca <512 x i1>, i64 1, align 64
 745 ! LLVMIR:         %[[VAL_287:.*]] = load <16 x i8>, ptr %[[VAL_285]], align 16
 746 ! LLVMIR:         %[[VAL_288:.*]] = load <16 x i8>, ptr %[[VAL_284]], align 16
 747 ! LLVMIR:         %[[VAL_289:.*]] = load <512 x i1>, ptr %[[VAL_286]], align 64
 748 ! LLVMIR:         %[[VAL_290:.*]] = call <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1> %[[VAL_289]], <16 x i8> %[[VAL_287]], <16 x i8> %[[VAL_288]])
 749 ! LLVMIR:         store <512 x i1> %[[VAL_290]], ptr %[[VAL_286]], align 64
 750
 751       subroutine test_xvi8ger4_u1()
 752       use, intrinsic :: mma
 753       implicit none
 754       vector(unsigned(1)) vu10, vu11
 755       __vector_quad :: cq
 756       call mma_xvi8ger4(cq, vu10, vu11)
 757       end subroutine test_xvi8ger4_u1
 758
 759 !CHECK-LABEL: @test_xvi8ger4_u1_
 760 ! LLVMIR:         %[[VAL_291:.*]] = alloca <16 x i8>, i64 1, align 16
 761 ! LLVMIR:         %[[VAL_292:.*]] = alloca <16 x i8>, i64 1, align 16
 762 ! LLVMIR:         %[[VAL_293:.*]] = alloca <512 x i1>, i64 1, align 64
 763 ! LLVMIR:         %[[VAL_294:.*]] = load <16 x i8>, ptr %[[VAL_292]], align 16
 764 ! LLVMIR:         %[[VAL_295:.*]] = load <16 x i8>, ptr %[[VAL_291]], align 16
 765 ! LLVMIR:         %[[VAL_296:.*]] = call <512 x i1> @llvm.ppc.mma.xvi8ger4(<16 x i8> %[[VAL_294]], <16 x i8> %[[VAL_295]])
 766 ! LLVMIR:         store <512 x i1> %[[VAL_296]], ptr %[[VAL_293]], align 64
 767
 768
 769       subroutine test_xvi8ger4_i1()
 770       use, intrinsic :: mma
 771       implicit none
 772       vector(integer(1)) vi10, vi11
 773       __vector_quad :: cq
 774       call mma_xvi8ger4(cq, vi10, vi11)
 775       end subroutine test_xvi8ger4_i1
 776
 777 !CHECK-LABEL: @test_xvi8ger4_i1_
 778 ! LLVMIR:         %[[VAL_297:.*]] = alloca <16 x i8>, i64 1, align 16
 779 ! LLVMIR:         %[[VAL_298:.*]] = alloca <16 x i8>, i64 1, align 16
 780 ! LLVMIR:         %[[VAL_299:.*]] = alloca <512 x i1>, i64 1, align 64
 781 ! LLVMIR:         %[[VAL_300:.*]] = load <16 x i8>, ptr %[[VAL_298]], align 16
 782 ! LLVMIR:         %[[VAL_301:.*]] = load <16 x i8>, ptr %[[VAL_297]], align 16
 783 ! LLVMIR:         %[[VAL_302:.*]] = call <512 x i1> @llvm.ppc.mma.xvi8ger4(<16 x i8> %[[VAL_300]], <16 x i8> %[[VAL_301]])
 784 ! LLVMIR:         store <512 x i1> %[[VAL_302]], ptr %[[VAL_299]], align 64
 785
 786       subroutine test_xvi8ger4pp_u1()
 787       use, intrinsic :: mma
 788       implicit none
 789       vector(unsigned(1)) vu10, vu11
 790       __vector_quad :: cq
 791       call mma_xvi8ger4pp(cq, vu10, vu11)
 792       end subroutine test_xvi8ger4pp_u1
 793
 794 !CHECK-LABEL: @test_xvi8ger4pp_u1_
 795 ! LLVMIR:         %[[VAL_303:.*]] = alloca <16 x i8>, i64 1, align 16
 796 ! LLVMIR:         %[[VAL_304:.*]] = alloca <16 x i8>, i64 1, align 16
 797 ! LLVMIR:         %[[VAL_305:.*]] = alloca <512 x i1>, i64 1, align 64
 798 ! LLVMIR:         %[[VAL_306:.*]] = load <16 x i8>, ptr %[[VAL_304]], align 16
 799 ! LLVMIR:         %[[VAL_307:.*]] = load <16 x i8>, ptr %[[VAL_303]], align 16
 800 ! LLVMIR:         %[[VAL_308:.*]] = load <512 x i1>, ptr %[[VAL_305]], align 64
 801 ! LLVMIR:         %[[VAL_309:.*]] = call <512 x i1> @llvm.ppc.mma.xvi8ger4pp(<512 x i1> %[[VAL_308]], <16 x i8> %[[VAL_306]], <16 x i8> %[[VAL_307]])
 802 ! LLVMIR:         store <512 x i1> %[[VAL_309]], ptr %[[VAL_305]], align 64
 803
 804       subroutine test_xvi8ger4pp_i1()
 805       use, intrinsic :: mma
 806       implicit none
 807       vector(integer(1)) vi10, vi11
 808       __vector_quad :: cq
 809       call mma_xvi8ger4pp(cq, vi10, vi11)
 810       end subroutine test_xvi8ger4pp_i1
 811
 812 !CHECK-LABEL:  @test_xvi8ger4pp_i1_
 813 ! LLVMIR:         %[[VAL_310:.*]] = alloca <16 x i8>, i64 1, align 16
 814 ! LLVMIR:         %[[VAL_311:.*]] = alloca <16 x i8>, i64 1, align 16
 815 ! LLVMIR:         %[[VAL_312:.*]] = alloca <512 x i1>, i64 1, align 64
 816 ! LLVMIR:         %[[VAL_313:.*]] = load <16 x i8>, ptr %[[VAL_311]], align 16
 817 ! LLVMIR:         %[[VAL_314:.*]] = load <16 x i8>, ptr %[[VAL_310]], align 16
 818 ! LLVMIR:         %[[VAL_315:.*]] = load <512 x i1>, ptr %[[VAL_312]], align 64
 819 ! LLVMIR:         %[[VAL_316:.*]] = call <512 x i1> @llvm.ppc.mma.xvi8ger4pp(<512 x i1> %[[VAL_315]], <16 x i8> %[[VAL_313]], <16 x i8> %[[VAL_314]])
 820 ! LLVMIR:         store <512 x i1> %[[VAL_316]], ptr %[[VAL_312]], align 64
 821
 822       subroutine test_xvi8ger4spp_u1()
 823       use, intrinsic :: mma
 824       implicit none
 825       vector(unsigned(1)) vu10, vu11
 826       __vector_quad :: cq
 827       call mma_xvi8ger4spp(cq, vu10, vu11)
 828       end subroutine test_xvi8ger4spp_u1
 829
 830 !CHECK-LABEL: @test_xvi8ger4spp_u1_
 831 ! LLVMIR:         %[[VAL_317:.*]] = alloca <16 x i8>, i64 1, align 16
 832 ! LLVMIR:         %[[VAL_318:.*]] = alloca <16 x i8>, i64 1, align 16
 833 ! LLVMIR:         %[[VAL_319:.*]] = alloca <512 x i1>, i64 1, align 64
 834 ! LLVMIR:         %[[VAL_320:.*]] = load <16 x i8>, ptr %[[VAL_318]], align 16
 835 ! LLVMIR:         %[[VAL_321:.*]] = load <16 x i8>, ptr %[[VAL_317]], align 16
 836 ! LLVMIR:         %[[VAL_322:.*]] = load <512 x i1>, ptr %[[VAL_319]], align 64
 837 ! LLVMIR:         %[[VAL_323:.*]] = call <512 x i1> @llvm.ppc.mma.xvi8ger4spp(<512 x i1> %[[VAL_322]], <16 x i8> %[[VAL_320]], <16 x i8> %[[VAL_321]])
 838 ! LLVMIR:         store <512 x i1> %[[VAL_323]], ptr %[[VAL_319]], align 64
 839
 840       subroutine test_xvi8ger4spp_i1()
 841       use, intrinsic :: mma
 842       implicit none
 843       vector(integer(1)) vi10, vi11
 844       __vector_quad :: cq
 845       call mma_xvi8ger4spp(cq, vi10, vi11)
 846       end subroutine test_xvi8ger4spp_i1
 847
 848 !CHECK-LABEL: @test_xvi8ger4spp_i1_
 849 ! LLVMIR:         %[[VAL_324:.*]] = alloca <16 x i8>, i64 1, align 16
 850 ! LLVMIR:         %[[VAL_325:.*]] = alloca <16 x i8>, i64 1, align 16
 851 ! LLVMIR:         %[[VAL_326:.*]] = alloca <512 x i1>, i64 1, align 64
 852 ! LLVMIR:         %[[VAL_327:.*]] = load <16 x i8>, ptr %[[VAL_325]], align 16
 853 ! LLVMIR:         %[[VAL_328:.*]] = load <16 x i8>, ptr %[[VAL_324]], align 16
 854 ! LLVMIR:         %[[VAL_329:.*]] = load <512 x i1>, ptr %[[VAL_326]], align 64
 855 ! LLVMIR:         %[[VAL_330:.*]] = call <512 x i1> @llvm.ppc.mma.xvi8ger4spp(<512 x i1> %[[VAL_329]], <16 x i8> %[[VAL_327]], <16 x i8> %[[VAL_328]])
 856 ! LLVMIR:         store <512 x i1> %[[VAL_330]], ptr %[[VAL_326]], align 64