flang/test/Lower/PowerPC/ppc-vec-perm-elem-order.f90

   1 ! RUN: %flang_fc1 -flang-experimental-hlfir -emit-llvm %s -fno-ppc-native-vector-element-order -triple ppc64le-unknwon-linux -o - | FileCheck --check-prefixes="LLVMIR" %s
   2 ! REQUIRES: target=powerpc{{.*}}
   3
   4 !----------------
   5 ! vec_perm
   6 !----------------
   7
   8 ! CHECK-LABEL: vec_perm_test_i1
   9 subroutine vec_perm_test_i1(arg1, arg2, arg3)
  10   vector(integer(1)) :: arg1, arg2, r
  11   vector(unsigned(1)) :: arg3
  12   r = vec_perm(arg1, arg2, arg3)
  13
  14 ! LLVMIR: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16
  15 ! LLVMIR: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16
  16 ! LLVMIR: %[[arg3:.*]] = load <16 x i8>, ptr %{{.*}}, align 16
  17 ! LLVMIR: %[[barg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32>
  18 ! LLVMIR: %[[barg2:.*]] = bitcast <16 x i8> %[[arg2]] to <4 x i32>
  19 ! LLVMIR: %[[call:.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> %[[barg1]], <4 x i32> %[[barg2]], <16 x i8> %[[arg3]])
  20 ! LLVMIR: %[[bcall:.*]] = bitcast <4 x i32> %[[call]] to <16 x i8>
  21 ! LLVMIR: store <16 x i8> %[[bcall]], ptr %{{.*}}, align 16
  22 end subroutine vec_perm_test_i1
  23
  24 !----------------
  25 ! vec_permi
  26 !----------------
  27
  28 ! CHECK-LABEL: vec_permi_test_i8i2
  29 subroutine vec_permi_test_i8i2(arg1, arg2, arg3)
  30   vector(integer(8)) :: arg1, arg2, r
  31   r = vec_permi(arg1, arg2, 2_2)
  32
  33 ! LLVMIR: %[[arg1:.*]] = load <2 x i64>, ptr %{{.*}}, align 16
  34 ! LLVMIR: %[[arg2:.*]] = load <2 x i64>, ptr %{{.*}}, align 16
  35 ! LLVMIR: %[[shuf:.*]] = shufflevector <2 x i64> %[[arg1]], <2 x i64> %[[arg2]], <2 x i32> <i32 3, i32 0>
  36 ! LLVMIR: store <2 x i64> %[[shuf]], ptr %{{.*}}, align 16
  37 end subroutine vec_permi_test_i8i2