lldb/source/Plugins/ABI/X86/ABIX86.cpp

   1 //===-- ABIX86.cpp --------------------------------------------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 #include "ABIMacOSX_i386.h"
  10 #include "ABISysV_i386.h"
  11 #include "ABISysV_x86_64.h"
  12 #include "ABIWindows_x86_64.h"
  13 #include "ABIX86.h"
  14 #include "lldb/Core/PluginManager.h"
  15 #include "lldb/Target/Process.h"
  16 #include <optional>
  17
  18 using namespace lldb;
  19 using namespace lldb_private;
  20
  21 LLDB_PLUGIN_DEFINE(ABIX86)
  22
  23 void ABIX86::Initialize() {
  24   ABIMacOSX_i386::Initialize();
  25   ABISysV_i386::Initialize();
  26   ABISysV_x86_64::Initialize();
  27   ABIWindows_x86_64::Initialize();
  28 }
  29
  30 void ABIX86::Terminate() {
  31   ABIMacOSX_i386::Terminate();
  32   ABISysV_i386::Terminate();
  33   ABISysV_x86_64::Terminate();
  34   ABIWindows_x86_64::Terminate();
  35 }
  36
  37 namespace {
  38 enum RegKind {
  39   GPR32,
  40   GPR16,
  41   GPR8h,
  42   GPR8,
  43   MM,
  44   YMM_YMMh,
  45   YMM_XMM,
  46
  47   RegKindCount
  48 };
  49 }
  50
  51 struct RegData {
  52   RegKind subreg_kind;
  53   llvm::StringRef subreg_name;
  54   std::optional<uint32_t> base_index;
  55 };
  56
  57 static void
  58 addPartialRegisters(std::vector<DynamicRegisterInfo::Register> &regs,
  59                     llvm::ArrayRef<RegData *> subregs, uint32_t base_size,
  60                     lldb::Encoding encoding, lldb::Format format,
  61                     uint32_t subreg_size, uint32_t subreg_offset = 0) {
  62   for (const RegData *subreg : subregs) {
  63     assert(subreg);
  64     uint32_t base_index = *subreg->base_index;
  65     DynamicRegisterInfo::Register &full_reg = regs[base_index];
  66     if (full_reg.byte_size != base_size)
  67       continue;
  68
  69     lldb_private::DynamicRegisterInfo::Register new_reg{
  70         lldb_private::ConstString(subreg->subreg_name),
  71         lldb_private::ConstString(),
  72         lldb_private::ConstString("supplementary registers"),
  73         subreg_size,
  74         LLDB_INVALID_INDEX32,
  75         encoding,
  76         format,
  77         LLDB_INVALID_REGNUM,
  78         LLDB_INVALID_REGNUM,
  79         LLDB_INVALID_REGNUM,
  80         LLDB_INVALID_REGNUM,
  81         {base_index},
  82         {},
  83         subreg_offset};
  84
  85     addSupplementaryRegister(regs, new_reg);
  86   }
  87 }
  88
  89 static void
  90 addCombinedRegisters(std::vector<DynamicRegisterInfo::Register> &regs,
  91                      llvm::ArrayRef<RegData *> subregs1,
  92                      llvm::ArrayRef<RegData *> subregs2, uint32_t base_size,
  93                      lldb::Encoding encoding, lldb::Format format) {
  94   for (auto it : llvm::zip(subregs1, subregs2)) {
  95     RegData *regdata1, *regdata2;
  96     std::tie(regdata1, regdata2) = it;
  97     assert(regdata1);
  98     assert(regdata2);
  99
 100     // verify that we've got matching target registers
 101     if (regdata1->subreg_name != regdata2->subreg_name)
 102       continue;
 103
 104     uint32_t base_index1 = *regdata1->base_index;
 105     uint32_t base_index2 = *regdata2->base_index;
 106     if (regs[base_index1].byte_size != base_size ||
 107         regs[base_index2].byte_size != base_size)
 108       continue;
 109
 110     lldb_private::DynamicRegisterInfo::Register new_reg{
 111         lldb_private::ConstString(regdata1->subreg_name),
 112         lldb_private::ConstString(),
 113         lldb_private::ConstString("supplementary registers"),
 114         base_size * 2,
 115         LLDB_INVALID_INDEX32,
 116         encoding,
 117         format,
 118         LLDB_INVALID_REGNUM,
 119         LLDB_INVALID_REGNUM,
 120         LLDB_INVALID_REGNUM,
 121         LLDB_INVALID_REGNUM,
 122         {base_index1, base_index2},
 123         {}};
 124
 125     addSupplementaryRegister(regs, new_reg);
 126   }
 127 }
 128
 129 typedef llvm::SmallDenseMap<llvm::StringRef, llvm::SmallVector<RegData, 4>, 64>
 130     BaseRegToRegsMap;
 131
 132 #define GPRh(l)                                                                \
 133   {                                                                            \
 134     is64bit ? BaseRegToRegsMap::value_type("r" l "x",                          \
 135                                            {{GPR32, "e" l "x", std::nullopt},  \
 136                                             {GPR16, l "x", std::nullopt},      \
 137                                             {GPR8h, l "h", std::nullopt},      \
 138                                             {GPR8, l "l", std::nullopt}})      \
 139             : BaseRegToRegsMap::value_type("e" l "x",                          \
 140                                            {{GPR16, l "x", std::nullopt},      \
 141                                             {GPR8h, l "h", std::nullopt},      \
 142                                             {GPR8, l "l", std::nullopt}})      \
 143   }
 144
 145 #define GPR(r16)                                                               \
 146   {                                                                            \
 147     is64bit ? BaseRegToRegsMap::value_type("r" r16,                            \
 148                                            {{GPR32, "e" r16, std::nullopt},    \
 149                                             {GPR16, r16, std::nullopt},        \
 150                                             {GPR8, r16 "l", std::nullopt}})    \
 151             : BaseRegToRegsMap::value_type(                                    \
 152                   "e" r16,                                                     \
 153                   {{GPR16, r16, std::nullopt}, {GPR8, r16 "l", std::nullopt}}) \
 154   }
 155
 156 #define GPR64(n)                                                               \
 157   {                                                                            \
 158     BaseRegToRegsMap::value_type("r" #n, {{GPR32, "r" #n "d", std::nullopt},   \
 159                                           {GPR16, "r" #n "w", std::nullopt},   \
 160                                           {GPR8, "r" #n "l", std::nullopt}})   \
 161   }
 162
 163 #define STMM(n)                                                                \
 164   { BaseRegToRegsMap::value_type("st" #n, {{MM, "mm" #n, std::nullopt}}) }
 165
 166 #define YMM(n)                                                                 \
 167   {BaseRegToRegsMap::value_type("ymm" #n "h",                                  \
 168                                 {{YMM_YMMh, "ymm" #n, std::nullopt}})},        \
 169   {                                                                            \
 170     BaseRegToRegsMap::value_type("xmm" #n,                                     \
 171                                  {{YMM_XMM, "ymm" #n, std::nullopt}})          \
 172   }
 173
 174 BaseRegToRegsMap makeBaseRegMap(bool is64bit) {
 175   BaseRegToRegsMap out{
 176       {// GPRs common to amd64 & i386
 177        GPRh("a"), GPRh("b"), GPRh("c"), GPRh("d"), GPR("si"), GPR("di"),
 178        GPR("bp"), GPR("sp"),
 179
 180        // ST/MM registers
 181        STMM(0), STMM(1), STMM(2), STMM(3), STMM(4), STMM(5), STMM(6), STMM(7),
 182
 183        // lower YMM registers (common to amd64 & i386)
 184        YMM(0), YMM(1), YMM(2), YMM(3), YMM(4), YMM(5), YMM(6), YMM(7)}};
 185
 186   if (is64bit) {
 187     BaseRegToRegsMap amd64_regs{{// GPRs specific to amd64
 188                                  GPR64(8), GPR64(9), GPR64(10), GPR64(11),
 189                                  GPR64(12), GPR64(13), GPR64(14), GPR64(15),
 190
 191                                  // higher YMM registers (specific to amd64)
 192                                  YMM(8), YMM(9), YMM(10), YMM(11), YMM(12),
 193                                  YMM(13), YMM(14), YMM(15)}};
 194     out.insert(amd64_regs.begin(), amd64_regs.end());
 195   }
 196
 197   return out;
 198 }
 199
 200 void ABIX86::AugmentRegisterInfo(
 201     std::vector<DynamicRegisterInfo::Register> &regs) {
 202   MCBasedABI::AugmentRegisterInfo(regs);
 203
 204   ProcessSP process_sp = GetProcessSP();
 205   if (!process_sp)
 206     return;
 207
 208   uint32_t gpr_base_size =
 209       process_sp->GetTarget().GetArchitecture().GetAddressByteSize();
 210
 211   // primary map from a base register to its subregisters
 212   BaseRegToRegsMap base_reg_map = makeBaseRegMap(gpr_base_size == 8);
 213   // set used for fast matching of register names to subregisters
 214   llvm::SmallDenseSet<llvm::StringRef, 64> subreg_name_set;
 215   // convenience array providing access to all subregisters of given kind,
 216   // sorted by base register index
 217   std::array<llvm::SmallVector<RegData *, 16>, RegKindCount> subreg_by_kind;
 218
 219   // prepare the set of all known subregisters
 220   for (const auto &x : base_reg_map) {
 221     for (const auto &subreg : x.second)
 222       subreg_name_set.insert(subreg.subreg_name);
 223   }
 224
 225   // iterate over all registers
 226   for (const auto &x : llvm::enumerate(regs)) {
 227     llvm::StringRef reg_name = x.value().name.GetStringRef();
 228     // abort if at least one sub-register is already present
 229     if (llvm::is_contained(subreg_name_set, reg_name))
 230       return;
 231
 232     auto found = base_reg_map.find(reg_name);
 233     if (found == base_reg_map.end())
 234       continue;
 235
 236     for (auto &subreg : found->second) {
 237       // fill in base register indices
 238       subreg.base_index = x.index();
 239       // fill subreg_by_kind map-array
 240       subreg_by_kind[static_cast<size_t>(subreg.subreg_kind)].push_back(
 241           &subreg);
 242     }
 243   }
 244
 245   // now add registers by kind
 246   addPartialRegisters(regs, subreg_by_kind[GPR32], gpr_base_size, eEncodingUint,
 247                       eFormatHex, 4);
 248   addPartialRegisters(regs, subreg_by_kind[GPR16], gpr_base_size, eEncodingUint,
 249                       eFormatHex, 2);
 250   addPartialRegisters(regs, subreg_by_kind[GPR8h], gpr_base_size, eEncodingUint,
 251                       eFormatHex, 1, 1);
 252   addPartialRegisters(regs, subreg_by_kind[GPR8], gpr_base_size, eEncodingUint,
 253                       eFormatHex, 1);
 254
 255   addPartialRegisters(regs, subreg_by_kind[MM], 10, eEncodingUint, eFormatHex,
 256                       8);
 257
 258   addCombinedRegisters(regs, subreg_by_kind[YMM_XMM], subreg_by_kind[YMM_YMMh],
 259                        16, eEncodingVector, eFormatVectorOfUInt8);
 260 }