lldb/source/Plugins/Architecture/Arm/ArchitectureArm.cpp

   1 //===-- ArchitectureArm.cpp -----------------------------------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 #include "Plugins/Architecture/Arm/ArchitectureArm.h"
  10 #include "Plugins/Process/Utility/ARMDefines.h"
  11 #include "Plugins/Process/Utility/InstructionUtils.h"
  12 #include "lldb/Core/PluginManager.h"
  13 #include "lldb/Target/RegisterContext.h"
  14 #include "lldb/Target/Thread.h"
  15 #include "lldb/Utility/ArchSpec.h"
  16
  17 using namespace lldb_private;
  18 using namespace lldb;
  19
  20 LLDB_PLUGIN_DEFINE(ArchitectureArm)
  21
  22 void ArchitectureArm::Initialize() {
  23   PluginManager::RegisterPlugin(GetPluginNameStatic(),
  24                                 "Arm-specific algorithms",
  25                                 &ArchitectureArm::Create);
  26 }
  27
  28 void ArchitectureArm::Terminate() {
  29   PluginManager::UnregisterPlugin(&ArchitectureArm::Create);
  30 }
  31
  32 std::unique_ptr<Architecture> ArchitectureArm::Create(const ArchSpec &arch) {
  33   if (arch.GetMachine() != llvm::Triple::arm)
  34     return nullptr;
  35   return std::unique_ptr<Architecture>(new ArchitectureArm());
  36 }
  37
  38 void ArchitectureArm::OverrideStopInfo(Thread &thread) const {
  39   // We need to check if we are stopped in Thumb mode in a IT instruction and
  40   // detect if the condition doesn't pass. If this is the case it means we
  41   // won't actually execute this instruction. If this happens we need to clear
  42   // the stop reason to no thread plans think we are stopped for a reason and
  43   // the plans should keep going.
  44   //
  45   // We do this because when single stepping many ARM processes, debuggers
  46   // often use the BVR/BCR registers that says "stop when the PC is not equal
  47   // to its current value". This method of stepping means we can end up
  48   // stopping on instructions inside an if/then block that wouldn't get
  49   // executed. By fixing this we can stop the debugger from seeming like you
  50   // stepped through both the "if" _and_ the "else" clause when source level
  51   // stepping because the debugger stops regardless due to the BVR/BCR
  52   // triggering a stop.
  53   //
  54   // It also means we can set breakpoints on instructions inside an if/then
  55   // block and correctly skip them if we use the BKPT instruction. The ARM and
  56   // Thumb BKPT instructions are unconditional even when executed in a Thumb IT
  57   // block.
  58   //
  59   // If your debugger inserts software traps in ARM/Thumb code, it will need to
  60   // use 16 and 32 bit instruction for 16 and 32 bit thumb instructions
  61   // respectively. If your debugger inserts a 16 bit thumb trap on top of a 32
  62   // bit thumb instruction for an opcode that is inside an if/then, it will
  63   // change the it/then to conditionally execute your
  64   // 16 bit trap and then cause your program to crash if it executes the
  65   // trailing 16 bits (the second half of the 32 bit thumb instruction you
  66   // partially overwrote).
  67
  68   RegisterContextSP reg_ctx_sp(thread.GetRegisterContext());
  69   if (!reg_ctx_sp)
  70     return;
  71
  72   const uint32_t cpsr = reg_ctx_sp->GetFlags(0);
  73   if (cpsr == 0)
  74     return;
  75
  76   // Read the J and T bits to get the ISETSTATE
  77   const uint32_t J = Bit32(cpsr, 24);
  78   const uint32_t T = Bit32(cpsr, 5);
  79   const uint32_t ISETSTATE = J << 1 | T;
  80   if (ISETSTATE == 0) {
  81 // NOTE: I am pretty sure we want to enable the code below
  82 // that detects when we stop on an instruction in ARM mode that is conditional
  83 // and the condition doesn't pass. This can happen if you set a breakpoint on
  84 // an instruction that is conditional. We currently will _always_ stop on the
  85 // instruction which is bad. You can also run into this while single stepping
  86 // and you could appear to run code in the "if" and in the "else" clause
  87 // because it would stop at all of the conditional instructions in both. In
  88 // such cases, we really don't want to stop at this location.
  89 // I will check with the lldb-dev list first before I enable this.
  90 #if 0
  91     // ARM mode: check for condition on instruction
  92     const addr_t pc = reg_ctx_sp->GetPC();
  93     Status error;
  94     // If we fail to read the opcode we will get UINT64_MAX as the result in
  95     // "opcode" which we can use to detect if we read a valid opcode.
  96     const uint64_t opcode = thread.GetProcess()->ReadUnsignedIntegerFromMemory(pc, 4, UINT64_MAX, error);
  97     if (opcode <= UINT32_MAX)
  98     {
  99         const uint32_t condition = Bits32((uint32_t)opcode, 31, 28);
 100         if (!ARMConditionPassed(condition, cpsr))
 101         {
 102             // We ARE stopped on an ARM instruction whose condition doesn't
 103             // pass so this instruction won't get executed. Regardless of why
 104             // it stopped, we need to clear the stop info
 105             thread.SetStopInfo (StopInfoSP());
 106         }
 107     }
 108 #endif
 109   } else if (ISETSTATE == 1) {
 110     // Thumb mode
 111     const uint32_t ITSTATE = Bits32(cpsr, 15, 10) << 2 | Bits32(cpsr, 26, 25);
 112     if (ITSTATE != 0) {
 113       const uint32_t condition = Bits32(ITSTATE, 7, 4);
 114       if (!ARMConditionPassed(condition, cpsr)) {
 115         // We ARE stopped in a Thumb IT instruction on an instruction whose
 116         // condition doesn't pass so this instruction won't get executed.
 117         // Regardless of why it stopped, we need to clear the stop info
 118         thread.SetStopInfo(StopInfoSP());
 119       }
 120     }
 121   }
 122 }
 123
 124 addr_t ArchitectureArm::GetCallableLoadAddress(addr_t code_addr,
 125                                                AddressClass addr_class) const {
 126   bool is_alternate_isa = false;
 127
 128   switch (addr_class) {
 129   case AddressClass::eData:
 130   case AddressClass::eDebug:
 131     return LLDB_INVALID_ADDRESS;
 132   case AddressClass::eCodeAlternateISA:
 133     is_alternate_isa = true;
 134     break;
 135   default: break;
 136   }
 137
 138   if ((code_addr & 2u) || is_alternate_isa)
 139     return code_addr | 1u;
 140   return code_addr;
 141 }
 142
 143 addr_t ArchitectureArm::GetOpcodeLoadAddress(addr_t opcode_addr,
 144                                              AddressClass addr_class) const {
 145   switch (addr_class) {
 146   case AddressClass::eData:
 147   case AddressClass::eDebug:
 148     return LLDB_INVALID_ADDRESS;
 149   default: break;
 150   }
 151   return opcode_addr & ~(1ull);
 152 }