lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.cpp

   1 //===-- NativeRegisterContextLinux_arm.cpp --------------------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 #if defined(__arm__) || defined(__arm64__) || defined(__aarch64__)
  10
  11 #include "NativeRegisterContextLinux_arm.h"
  12
  13 #include "Plugins/Process/Linux/NativeProcessLinux.h"
  14 #include "Plugins/Process/Linux/Procfs.h"
  15 #include "Plugins/Process/POSIX/ProcessPOSIXLog.h"
  16 #include "Plugins/Process/Utility/RegisterInfoPOSIX_arm.h"
  17 #include "lldb/Host/HostInfo.h"
  18 #include "lldb/Utility/DataBufferHeap.h"
  19 #include "lldb/Utility/Log.h"
  20 #include "lldb/Utility/RegisterValue.h"
  21 #include "lldb/Utility/Status.h"
  22
  23 #include <elf.h>
  24 #include <sys/uio.h>
  25
  26 #define REG_CONTEXT_SIZE (GetGPRSize() + sizeof(m_fpr))
  27
  28 #ifndef PTRACE_GETVFPREGS
  29 #define PTRACE_GETVFPREGS 27
  30 #define PTRACE_SETVFPREGS 28
  31 #endif
  32 #ifndef PTRACE_GETHBPREGS
  33 #define PTRACE_GETHBPREGS 29
  34 #define PTRACE_SETHBPREGS 30
  35 #endif
  36 #if !defined(PTRACE_TYPE_ARG3)
  37 #define PTRACE_TYPE_ARG3 void *
  38 #endif
  39 #if !defined(PTRACE_TYPE_ARG4)
  40 #define PTRACE_TYPE_ARG4 void *
  41 #endif
  42
  43 using namespace lldb;
  44 using namespace lldb_private;
  45 using namespace lldb_private::process_linux;
  46
  47 #if defined(__arm__)
  48
  49 std::unique_ptr<NativeRegisterContextLinux>
  50 NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux(
  51     const ArchSpec &target_arch, NativeThreadLinux &native_thread) {
  52   return std::make_unique<NativeRegisterContextLinux_arm>(target_arch,
  53                                                            native_thread);
  54 }
  55
  56 llvm::Expected<ArchSpec>
  57 NativeRegisterContextLinux::DetermineArchitecture(lldb::tid_t tid) {
  58   return HostInfo::GetArchitecture();
  59 }
  60
  61 #endif // defined(__arm__)
  62
  63 NativeRegisterContextLinux_arm::NativeRegisterContextLinux_arm(
  64     const ArchSpec &target_arch, NativeThreadProtocol &native_thread)
  65     : NativeRegisterContextRegisterInfo(native_thread,
  66                                         new RegisterInfoPOSIX_arm(target_arch)),
  67       NativeRegisterContextLinux(native_thread) {
  68   assert(target_arch.GetMachine() == llvm::Triple::arm);
  69
  70   ::memset(&m_fpr, 0, sizeof(m_fpr));
  71   ::memset(&m_gpr_arm, 0, sizeof(m_gpr_arm));
  72   ::memset(&m_hwp_regs, 0, sizeof(m_hwp_regs));
  73   ::memset(&m_hbr_regs, 0, sizeof(m_hbr_regs));
  74
  75   // 16 is just a maximum value, query hardware for actual watchpoint count
  76   m_max_hwp_supported = 16;
  77   m_max_hbp_supported = 16;
  78   m_refresh_hwdebug_info = true;
  79 }
  80
  81 RegisterInfoPOSIX_arm &NativeRegisterContextLinux_arm::GetRegisterInfo() const {
  82   return static_cast<RegisterInfoPOSIX_arm &>(*m_register_info_interface_up);
  83 }
  84
  85 uint32_t NativeRegisterContextLinux_arm::GetRegisterSetCount() const {
  86   return GetRegisterInfo().GetRegisterSetCount();
  87 }
  88
  89 uint32_t NativeRegisterContextLinux_arm::GetUserRegisterCount() const {
  90   uint32_t count = 0;
  91   for (uint32_t set_index = 0; set_index < GetRegisterSetCount(); ++set_index)
  92     count += GetRegisterSet(set_index)->num_registers;
  93   return count;
  94 }
  95
  96 const RegisterSet *
  97 NativeRegisterContextLinux_arm::GetRegisterSet(uint32_t set_index) const {
  98   return GetRegisterInfo().GetRegisterSet(set_index);
  99 }
 100
 101 Status
 102 NativeRegisterContextLinux_arm::ReadRegister(const RegisterInfo *reg_info,
 103                                              RegisterValue &reg_value) {
 104   Status error;
 105
 106   if (!reg_info) {
 107     error = Status::FromErrorString("reg_info NULL");
 108     return error;
 109   }
 110
 111   const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
 112
 113   if (IsFPR(reg)) {
 114     error = ReadFPR();
 115     if (error.Fail())
 116       return error;
 117   } else {
 118     uint32_t full_reg = reg;
 119     bool is_subreg = reg_info->invalidate_regs &&
 120                      (reg_info->invalidate_regs[0] != LLDB_INVALID_REGNUM);
 121
 122     if (is_subreg) {
 123       // Read the full aligned 64-bit register.
 124       full_reg = reg_info->invalidate_regs[0];
 125     }
 126
 127     error = ReadRegisterRaw(full_reg, reg_value);
 128
 129     if (error.Success()) {
 130       // If our read was not aligned (for ah,bh,ch,dh), shift our returned
 131       // value one byte to the right.
 132       if (is_subreg && (reg_info->byte_offset & 0x1))
 133         reg_value.SetUInt64(reg_value.GetAsUInt64() >> 8);
 134
 135       // If our return byte size was greater than the return value reg size,
 136       // then use the type specified by reg_info rather than the uint64_t
 137       // default
 138       if (reg_value.GetByteSize() > reg_info->byte_size)
 139         reg_value.SetType(*reg_info);
 140     }
 141     return error;
 142   }
 143
 144   // Get pointer to m_fpr variable and set the data from it.
 145   uint32_t fpr_offset = CalculateFprOffset(reg_info);
 146   assert(fpr_offset < sizeof m_fpr);
 147   uint8_t *src = (uint8_t *)&m_fpr + fpr_offset;
 148   switch (reg_info->byte_size) {
 149   case 2:
 150     reg_value.SetUInt16(*(uint16_t *)src);
 151     break;
 152   case 4:
 153     reg_value.SetUInt32(*(uint32_t *)src);
 154     break;
 155   case 8:
 156     reg_value.SetUInt64(*(uint64_t *)src);
 157     break;
 158   case 16:
 159     reg_value.SetBytes(src, 16, GetByteOrder());
 160     break;
 161   default:
 162     assert(false && "Unhandled data size.");
 163     error = Status::FromErrorStringWithFormat("unhandled byte size: %" PRIu32,
 164                                               reg_info->byte_size);
 165     break;
 166   }
 167
 168   return error;
 169 }
 170
 171 Status
 172 NativeRegisterContextLinux_arm::WriteRegister(const RegisterInfo *reg_info,
 173                                               const RegisterValue &reg_value) {
 174   if (!reg_info)
 175     return Status::FromErrorString("reg_info NULL");
 176
 177   const uint32_t reg_index = reg_info->kinds[lldb::eRegisterKindLLDB];
 178   if (reg_index == LLDB_INVALID_REGNUM)
 179     return Status::FromErrorStringWithFormat(
 180         "no lldb regnum for %s",
 181         reg_info && reg_info->name ? reg_info->name : "<unknown register>");
 182
 183   if (IsGPR(reg_index))
 184     return WriteRegisterRaw(reg_index, reg_value);
 185
 186   if (IsFPR(reg_index)) {
 187     // Get pointer to m_fpr variable and set the data to it.
 188     uint32_t fpr_offset = CalculateFprOffset(reg_info);
 189     assert(fpr_offset < sizeof m_fpr);
 190     uint8_t *dst = (uint8_t *)&m_fpr + fpr_offset;
 191     ::memcpy(dst, reg_value.GetBytes(), reg_info->byte_size);
 192
 193     return WriteFPR();
 194   }
 195
 196   return Status::FromErrorString(
 197       "failed - register wasn't recognized to be a GPR or an FPR, "
 198       "write strategy unknown");
 199 }
 200
 201 Status NativeRegisterContextLinux_arm::ReadAllRegisterValues(
 202     lldb::WritableDataBufferSP &data_sp) {
 203   Status error;
 204
 205   data_sp.reset(new DataBufferHeap(REG_CONTEXT_SIZE, 0));
 206   error = ReadGPR();
 207   if (error.Fail())
 208     return error;
 209
 210   error = ReadFPR();
 211   if (error.Fail())
 212     return error;
 213
 214   uint8_t *dst = data_sp->GetBytes();
 215   ::memcpy(dst, &m_gpr_arm, GetGPRSize());
 216   dst += GetGPRSize();
 217   ::memcpy(dst, &m_fpr, sizeof(m_fpr));
 218
 219   return error;
 220 }
 221
 222 Status NativeRegisterContextLinux_arm::WriteAllRegisterValues(
 223     const lldb::DataBufferSP &data_sp) {
 224   Status error;
 225
 226   if (!data_sp) {
 227     error = Status::FromErrorStringWithFormat(
 228         "NativeRegisterContextLinux_arm::%s invalid data_sp provided",
 229         __FUNCTION__);
 230     return error;
 231   }
 232
 233   if (data_sp->GetByteSize() != REG_CONTEXT_SIZE) {
 234     error = Status::FromErrorStringWithFormat(
 235         "NativeRegisterContextLinux_arm::%s data_sp contained mismatched "
 236         "data size, expected %" PRIu64 ", actual %" PRIu64,
 237         __FUNCTION__, (uint64_t)REG_CONTEXT_SIZE, data_sp->GetByteSize());
 238     return error;
 239   }
 240
 241   const uint8_t *src = data_sp->GetBytes();
 242   if (src == nullptr) {
 243     error = Status::FromErrorStringWithFormat(
 244         "NativeRegisterContextLinux_arm::%s "
 245         "DataBuffer::GetBytes() returned a null "
 246         "pointer",
 247         __FUNCTION__);
 248     return error;
 249   }
 250   ::memcpy(&m_gpr_arm, src, GetRegisterInfoInterface().GetGPRSize());
 251
 252   error = WriteGPR();
 253   if (error.Fail())
 254     return error;
 255
 256   src += GetRegisterInfoInterface().GetGPRSize();
 257   ::memcpy(&m_fpr, src, sizeof(m_fpr));
 258
 259   error = WriteFPR();
 260   if (error.Fail())
 261     return error;
 262
 263   return error;
 264 }
 265
 266 bool NativeRegisterContextLinux_arm::IsGPR(unsigned reg) const {
 267   if (GetRegisterInfo().GetRegisterSetFromRegisterIndex(reg) ==
 268       RegisterInfoPOSIX_arm::GPRegSet)
 269     return true;
 270   return false;
 271 }
 272
 273 bool NativeRegisterContextLinux_arm::IsFPR(unsigned reg) const {
 274   if (GetRegisterInfo().GetRegisterSetFromRegisterIndex(reg) ==
 275       RegisterInfoPOSIX_arm::FPRegSet)
 276     return true;
 277   return false;
 278 }
 279
 280 uint32_t NativeRegisterContextLinux_arm::NumSupportedHardwareBreakpoints() {
 281   Log *log = GetLog(POSIXLog::Breakpoints);
 282
 283   LLDB_LOGF(log, "NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
 284
 285   Status error;
 286
 287   // Read hardware breakpoint and watchpoint information.
 288   error = ReadHardwareDebugInfo();
 289
 290   if (error.Fail())
 291     return 0;
 292
 293   LLDB_LOG(log, "{0}", m_max_hbp_supported);
 294   return m_max_hbp_supported;
 295 }
 296
 297 uint32_t
 298 NativeRegisterContextLinux_arm::SetHardwareBreakpoint(lldb::addr_t addr,
 299                                                       size_t size) {
 300   Log *log = GetLog(POSIXLog::Breakpoints);
 301   LLDB_LOG(log, "addr: {0:x}, size: {1:x}", addr, size);
 302
 303   // Read hardware breakpoint and watchpoint information.
 304   Status error = ReadHardwareDebugInfo();
 305
 306   if (error.Fail())
 307     return LLDB_INVALID_INDEX32;
 308
 309   uint32_t control_value = 0, bp_index = 0;
 310
 311   // Setup address and control values.
 312   // Use size to get a hint of arm vs thumb modes.
 313   switch (size) {
 314   case 2:
 315     control_value = (0x3 << 5) | 7;
 316     addr &= ~1;
 317     break;
 318   case 4:
 319     control_value = (0xfu << 5) | 7;
 320     addr &= ~3;
 321     break;
 322   default:
 323     return LLDB_INVALID_INDEX32;
 324   }
 325
 326   // Iterate over stored breakpoints and find a free bp_index
 327   bp_index = LLDB_INVALID_INDEX32;
 328   for (uint32_t i = 0; i < m_max_hbp_supported; i++) {
 329     if ((m_hbr_regs[i].control & 1) == 0) {
 330       bp_index = i; // Mark last free slot
 331     } else if (m_hbr_regs[i].address == addr) {
 332       return LLDB_INVALID_INDEX32; // We do not support duplicate breakpoints.
 333     }
 334   }
 335
 336   if (bp_index == LLDB_INVALID_INDEX32)
 337     return LLDB_INVALID_INDEX32;
 338
 339   // Update breakpoint in local cache
 340   m_hbr_regs[bp_index].real_addr = addr;
 341   m_hbr_regs[bp_index].address = addr;
 342   m_hbr_regs[bp_index].control = control_value;
 343
 344   // PTRACE call to set corresponding hardware breakpoint register.
 345   error = WriteHardwareDebugRegs(eDREGTypeBREAK, bp_index);
 346
 347   if (error.Fail()) {
 348     m_hbr_regs[bp_index].address = 0;
 349     m_hbr_regs[bp_index].control &= ~1;
 350
 351     return LLDB_INVALID_INDEX32;
 352   }
 353
 354   return bp_index;
 355 }
 356
 357 bool NativeRegisterContextLinux_arm::ClearHardwareBreakpoint(uint32_t hw_idx) {
 358   Log *log = GetLog(POSIXLog::Breakpoints);
 359   LLDB_LOG(log, "hw_idx: {0}", hw_idx);
 360
 361   // Read hardware breakpoint and watchpoint information.
 362   Status error = ReadHardwareDebugInfo();
 363
 364   if (error.Fail())
 365     return false;
 366
 367   if (hw_idx >= m_max_hbp_supported)
 368     return false;
 369
 370   // Create a backup we can revert to in case of failure.
 371   lldb::addr_t tempAddr = m_hbr_regs[hw_idx].address;
 372   uint32_t tempControl = m_hbr_regs[hw_idx].control;
 373
 374   m_hbr_regs[hw_idx].control &= ~1;
 375   m_hbr_regs[hw_idx].address = 0;
 376
 377   // PTRACE call to clear corresponding hardware breakpoint register.
 378   error = WriteHardwareDebugRegs(eDREGTypeBREAK, hw_idx);
 379
 380   if (error.Fail()) {
 381     m_hbr_regs[hw_idx].control = tempControl;
 382     m_hbr_regs[hw_idx].address = tempAddr;
 383
 384     return false;
 385   }
 386
 387   return true;
 388 }
 389
 390 Status NativeRegisterContextLinux_arm::GetHardwareBreakHitIndex(
 391     uint32_t &bp_index, lldb::addr_t trap_addr) {
 392   Log *log = GetLog(POSIXLog::Breakpoints);
 393
 394   LLDB_LOGF(log, "NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
 395
 396   lldb::addr_t break_addr;
 397
 398   for (bp_index = 0; bp_index < m_max_hbp_supported; ++bp_index) {
 399     break_addr = m_hbr_regs[bp_index].address;
 400
 401     if ((m_hbr_regs[bp_index].control & 0x1) && (trap_addr == break_addr)) {
 402       m_hbr_regs[bp_index].hit_addr = trap_addr;
 403       return Status();
 404     }
 405   }
 406
 407   bp_index = LLDB_INVALID_INDEX32;
 408   return Status();
 409 }
 410
 411 Status NativeRegisterContextLinux_arm::ClearAllHardwareBreakpoints() {
 412   Log *log = GetLog(POSIXLog::Breakpoints);
 413
 414   LLDB_LOGF(log, "NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
 415
 416   Status error;
 417
 418   // Read hardware breakpoint and watchpoint information.
 419   error = ReadHardwareDebugInfo();
 420
 421   if (error.Fail())
 422     return error;
 423
 424   lldb::addr_t tempAddr = 0;
 425   uint32_t tempControl = 0;
 426
 427   for (uint32_t i = 0; i < m_max_hbp_supported; i++) {
 428     if (m_hbr_regs[i].control & 0x01) {
 429       // Create a backup we can revert to in case of failure.
 430       tempAddr = m_hbr_regs[i].address;
 431       tempControl = m_hbr_regs[i].control;
 432
 433       // Clear breakpoints in local cache
 434       m_hbr_regs[i].control &= ~1;
 435       m_hbr_regs[i].address = 0;
 436
 437       // Ptrace call to update hardware debug registers
 438       error = WriteHardwareDebugRegs(eDREGTypeBREAK, i);
 439
 440       if (error.Fail()) {
 441         m_hbr_regs[i].control = tempControl;
 442         m_hbr_regs[i].address = tempAddr;
 443
 444         return error;
 445       }
 446     }
 447   }
 448
 449   return Status();
 450 }
 451
 452 uint32_t NativeRegisterContextLinux_arm::NumSupportedHardwareWatchpoints() {
 453   Log *log = GetLog(POSIXLog::Watchpoints);
 454
 455   // Read hardware breakpoint and watchpoint information.
 456   Status error = ReadHardwareDebugInfo();
 457
 458   if (error.Fail())
 459     return 0;
 460
 461   LLDB_LOG(log, "{0}", m_max_hwp_supported);
 462   return m_max_hwp_supported;
 463 }
 464
 465 uint32_t NativeRegisterContextLinux_arm::SetHardwareWatchpoint(
 466     lldb::addr_t addr, size_t size, uint32_t watch_flags) {
 467   Log *log = GetLog(POSIXLog::Watchpoints);
 468   LLDB_LOG(log, "addr: {0:x}, size: {1:x} watch_flags: {2:x}", addr, size,
 469            watch_flags);
 470
 471   // Read hardware breakpoint and watchpoint information.
 472   Status error = ReadHardwareDebugInfo();
 473
 474   if (error.Fail())
 475     return LLDB_INVALID_INDEX32;
 476
 477   uint32_t control_value = 0, wp_index = 0, addr_word_offset = 0, byte_mask = 0;
 478   lldb::addr_t real_addr = addr;
 479
 480   // Check if we are setting watchpoint other than read/write/access Also
 481   // update watchpoint flag to match Arm write-read bit configuration.
 482   switch (watch_flags) {
 483   case 1:
 484     watch_flags = 2;
 485     break;
 486   case 2:
 487     watch_flags = 1;
 488     break;
 489   case 3:
 490     break;
 491   default:
 492     return LLDB_INVALID_INDEX32;
 493   }
 494
 495   // Can't watch zero bytes
 496   // Can't watch more than 4 bytes per WVR/WCR pair
 497
 498   if (size == 0 || size > 4)
 499     return LLDB_INVALID_INDEX32;
 500
 501   // Check 4-byte alignment for hardware watchpoint target address. Below is a
 502   // hack to recalculate address and size in order to make sure we can watch
 503   // non 4-byte aligned addresses as well.
 504   if (addr & 0x03) {
 505     uint8_t watch_mask = (addr & 0x03) + size;
 506
 507     if (watch_mask > 0x04)
 508       return LLDB_INVALID_INDEX32;
 509     else if (watch_mask <= 0x02)
 510       size = 2;
 511     else
 512       size = 4;
 513
 514     addr = addr & (~0x03);
 515   }
 516
 517   // We can only watch up to four bytes that follow a 4 byte aligned address
 518   // per watchpoint register pair, so make sure we can properly encode this.
 519   addr_word_offset = addr % 4;
 520   byte_mask = ((1u << size) - 1u) << addr_word_offset;
 521
 522   // Check if we need multiple watchpoint register
 523   if (byte_mask > 0xfu)
 524     return LLDB_INVALID_INDEX32;
 525
 526   // Setup control value
 527   // Make the byte_mask into a valid Byte Address Select mask
 528   control_value = byte_mask << 5;
 529
 530   // Turn on appropriate watchpoint flags read or write
 531   control_value |= (watch_flags << 3);
 532
 533   // Enable this watchpoint and make it stop in privileged or user mode;
 534   control_value |= 7;
 535
 536   // Make sure bits 1:0 are clear in our address
 537   addr &= ~((lldb::addr_t)3);
 538
 539   // Iterate over stored watchpoints and find a free wp_index
 540   wp_index = LLDB_INVALID_INDEX32;
 541   for (uint32_t i = 0; i < m_max_hwp_supported; i++) {
 542     if ((m_hwp_regs[i].control & 1) == 0) {
 543       wp_index = i; // Mark last free slot
 544     } else if (m_hwp_regs[i].address == addr) {
 545       return LLDB_INVALID_INDEX32; // We do not support duplicate watchpoints.
 546     }
 547   }
 548
 549   if (wp_index == LLDB_INVALID_INDEX32)
 550     return LLDB_INVALID_INDEX32;
 551
 552   // Update watchpoint in local cache
 553   m_hwp_regs[wp_index].real_addr = real_addr;
 554   m_hwp_regs[wp_index].address = addr;
 555   m_hwp_regs[wp_index].control = control_value;
 556
 557   // PTRACE call to set corresponding watchpoint register.
 558   error = WriteHardwareDebugRegs(eDREGTypeWATCH, wp_index);
 559
 560   if (error.Fail()) {
 561     m_hwp_regs[wp_index].address = 0;
 562     m_hwp_regs[wp_index].control &= ~1;
 563
 564     return LLDB_INVALID_INDEX32;
 565   }
 566
 567   return wp_index;
 568 }
 569
 570 bool NativeRegisterContextLinux_arm::ClearHardwareWatchpoint(
 571     uint32_t wp_index) {
 572   Log *log = GetLog(POSIXLog::Watchpoints);
 573   LLDB_LOG(log, "wp_index: {0}", wp_index);
 574
 575   // Read hardware breakpoint and watchpoint information.
 576   Status error = ReadHardwareDebugInfo();
 577
 578   if (error.Fail())
 579     return false;
 580
 581   if (wp_index >= m_max_hwp_supported)
 582     return false;
 583
 584   // Create a backup we can revert to in case of failure.
 585   lldb::addr_t tempAddr = m_hwp_regs[wp_index].address;
 586   uint32_t tempControl = m_hwp_regs[wp_index].control;
 587
 588   // Update watchpoint in local cache
 589   m_hwp_regs[wp_index].control &= ~1;
 590   m_hwp_regs[wp_index].address = 0;
 591
 592   // Ptrace call to update hardware debug registers
 593   error = WriteHardwareDebugRegs(eDREGTypeWATCH, wp_index);
 594
 595   if (error.Fail()) {
 596     m_hwp_regs[wp_index].control = tempControl;
 597     m_hwp_regs[wp_index].address = tempAddr;
 598
 599     return false;
 600   }
 601
 602   return true;
 603 }
 604
 605 Status NativeRegisterContextLinux_arm::ClearAllHardwareWatchpoints() {
 606   // Read hardware breakpoint and watchpoint information.
 607   Status error = ReadHardwareDebugInfo();
 608
 609   if (error.Fail())
 610     return error;
 611
 612   lldb::addr_t tempAddr = 0;
 613   uint32_t tempControl = 0;
 614
 615   for (uint32_t i = 0; i < m_max_hwp_supported; i++) {
 616     if (m_hwp_regs[i].control & 0x01) {
 617       // Create a backup we can revert to in case of failure.
 618       tempAddr = m_hwp_regs[i].address;
 619       tempControl = m_hwp_regs[i].control;
 620
 621       // Clear watchpoints in local cache
 622       m_hwp_regs[i].control &= ~1;
 623       m_hwp_regs[i].address = 0;
 624
 625       // Ptrace call to update hardware debug registers
 626       error = WriteHardwareDebugRegs(eDREGTypeWATCH, i);
 627
 628       if (error.Fail()) {
 629         m_hwp_regs[i].control = tempControl;
 630         m_hwp_regs[i].address = tempAddr;
 631
 632         return error;
 633       }
 634     }
 635   }
 636
 637   return Status();
 638 }
 639
 640 uint32_t NativeRegisterContextLinux_arm::GetWatchpointSize(uint32_t wp_index) {
 641   Log *log = GetLog(POSIXLog::Watchpoints);
 642   LLDB_LOG(log, "wp_index: {0}", wp_index);
 643
 644   switch ((m_hwp_regs[wp_index].control >> 5) & 0x0f) {
 645   case 0x01:
 646     return 1;
 647   case 0x03:
 648     return 2;
 649   case 0x07:
 650     return 3;
 651   case 0x0f:
 652     return 4;
 653   default:
 654     return 0;
 655   }
 656 }
 657 bool NativeRegisterContextLinux_arm::WatchpointIsEnabled(uint32_t wp_index) {
 658   Log *log = GetLog(POSIXLog::Watchpoints);
 659   LLDB_LOG(log, "wp_index: {0}", wp_index);
 660
 661   if ((m_hwp_regs[wp_index].control & 0x1) == 0x1)
 662     return true;
 663   else
 664     return false;
 665 }
 666
 667 Status
 668 NativeRegisterContextLinux_arm::GetWatchpointHitIndex(uint32_t &wp_index,
 669                                                       lldb::addr_t trap_addr) {
 670   Log *log = GetLog(POSIXLog::Watchpoints);
 671   LLDB_LOG(log, "wp_index: {0}, trap_addr: {1:x}", wp_index, trap_addr);
 672
 673   uint32_t watch_size;
 674   lldb::addr_t watch_addr;
 675
 676   for (wp_index = 0; wp_index < m_max_hwp_supported; ++wp_index) {
 677     watch_size = GetWatchpointSize(wp_index);
 678     watch_addr = m_hwp_regs[wp_index].address;
 679
 680     if (WatchpointIsEnabled(wp_index) && trap_addr >= watch_addr &&
 681         trap_addr < watch_addr + watch_size) {
 682       m_hwp_regs[wp_index].hit_addr = trap_addr;
 683       return Status();
 684     }
 685   }
 686
 687   wp_index = LLDB_INVALID_INDEX32;
 688   return Status();
 689 }
 690
 691 lldb::addr_t
 692 NativeRegisterContextLinux_arm::GetWatchpointAddress(uint32_t wp_index) {
 693   Log *log = GetLog(POSIXLog::Watchpoints);
 694   LLDB_LOG(log, "wp_index: {0}", wp_index);
 695
 696   if (wp_index >= m_max_hwp_supported)
 697     return LLDB_INVALID_ADDRESS;
 698
 699   if (WatchpointIsEnabled(wp_index))
 700     return m_hwp_regs[wp_index].real_addr;
 701   else
 702     return LLDB_INVALID_ADDRESS;
 703 }
 704
 705 lldb::addr_t
 706 NativeRegisterContextLinux_arm::GetWatchpointHitAddress(uint32_t wp_index) {
 707   Log *log = GetLog(POSIXLog::Watchpoints);
 708   LLDB_LOG(log, "wp_index: {0}", wp_index);
 709
 710   if (wp_index >= m_max_hwp_supported)
 711     return LLDB_INVALID_ADDRESS;
 712
 713   if (WatchpointIsEnabled(wp_index))
 714     return m_hwp_regs[wp_index].hit_addr;
 715   else
 716     return LLDB_INVALID_ADDRESS;
 717 }
 718
 719 Status NativeRegisterContextLinux_arm::ReadHardwareDebugInfo() {
 720   Status error;
 721
 722   if (!m_refresh_hwdebug_info) {
 723     return Status();
 724   }
 725
 726   unsigned int cap_val;
 727
 728   error = NativeProcessLinux::PtraceWrapper(PTRACE_GETHBPREGS, m_thread.GetID(),
 729                                             nullptr, &cap_val,
 730                                             sizeof(unsigned int));
 731
 732   if (error.Fail())
 733     return error;
 734
 735   m_max_hwp_supported = (cap_val >> 8) & 0xff;
 736   m_max_hbp_supported = cap_val & 0xff;
 737   m_refresh_hwdebug_info = false;
 738
 739   return error;
 740 }
 741
 742 Status NativeRegisterContextLinux_arm::WriteHardwareDebugRegs(int hwbType,
 743                                                               int hwb_index) {
 744   Status error;
 745
 746   lldb::addr_t *addr_buf;
 747   uint32_t *ctrl_buf;
 748
 749   if (hwbType == eDREGTypeWATCH) {
 750     addr_buf = &m_hwp_regs[hwb_index].address;
 751     ctrl_buf = &m_hwp_regs[hwb_index].control;
 752
 753     error = NativeProcessLinux::PtraceWrapper(
 754         PTRACE_SETHBPREGS, m_thread.GetID(),
 755         (PTRACE_TYPE_ARG3)(intptr_t) - ((hwb_index << 1) + 1), addr_buf,
 756         sizeof(unsigned int));
 757
 758     if (error.Fail())
 759       return error;
 760
 761     error = NativeProcessLinux::PtraceWrapper(
 762         PTRACE_SETHBPREGS, m_thread.GetID(),
 763         (PTRACE_TYPE_ARG3)(intptr_t) - ((hwb_index << 1) + 2), ctrl_buf,
 764         sizeof(unsigned int));
 765   } else {
 766     addr_buf = &m_hbr_regs[hwb_index].address;
 767     ctrl_buf = &m_hbr_regs[hwb_index].control;
 768
 769     error = NativeProcessLinux::PtraceWrapper(
 770         PTRACE_SETHBPREGS, m_thread.GetID(),
 771         (PTRACE_TYPE_ARG3)(intptr_t)((hwb_index << 1) + 1), addr_buf,
 772         sizeof(unsigned int));
 773
 774     if (error.Fail())
 775       return error;
 776
 777     error = NativeProcessLinux::PtraceWrapper(
 778         PTRACE_SETHBPREGS, m_thread.GetID(),
 779         (PTRACE_TYPE_ARG3)(intptr_t)((hwb_index << 1) + 2), ctrl_buf,
 780         sizeof(unsigned int));
 781   }
 782
 783   return error;
 784 }
 785
 786 uint32_t NativeRegisterContextLinux_arm::CalculateFprOffset(
 787     const RegisterInfo *reg_info) const {
 788   return reg_info->byte_offset - GetGPRSize();
 789 }
 790
 791 Status NativeRegisterContextLinux_arm::DoReadRegisterValue(
 792     uint32_t offset, const char *reg_name, uint32_t size,
 793     RegisterValue &value) {
 794   // PTRACE_PEEKUSER don't work in the aarch64 linux kernel used on android
 795   // devices (always return "Bad address"). To avoid using PTRACE_PEEKUSER we
 796   // read out the full GPR register set instead. This approach is about 4 times
 797   // slower but the performance overhead is negligible in comparison to
 798   // processing time in lldb-server.
 799   assert(offset % 4 == 0 && "Try to write a register with unaligned offset");
 800   if (offset + sizeof(uint32_t) > sizeof(m_gpr_arm))
 801     return Status::FromErrorString(
 802         "Register isn't fit into the size of the GPR area");
 803
 804   Status error = ReadGPR();
 805   if (error.Fail())
 806     return error;
 807
 808   value.SetUInt32(m_gpr_arm[offset / sizeof(uint32_t)]);
 809   return Status();
 810 }
 811
 812 Status NativeRegisterContextLinux_arm::DoWriteRegisterValue(
 813     uint32_t offset, const char *reg_name, const RegisterValue &value) {
 814   // PTRACE_POKEUSER don't work in the aarch64 linux kernel used on android
 815   // devices (always return "Bad address"). To avoid using PTRACE_POKEUSER we
 816   // read out the full GPR register set, modify the requested register and
 817   // write it back. This approach is about 4 times slower but the performance
 818   // overhead is negligible in comparison to processing time in lldb-server.
 819   assert(offset % 4 == 0 && "Try to write a register with unaligned offset");
 820   if (offset + sizeof(uint32_t) > sizeof(m_gpr_arm))
 821     return Status::FromErrorString(
 822         "Register isn't fit into the size of the GPR area");
 823
 824   Status error = ReadGPR();
 825   if (error.Fail())
 826     return error;
 827
 828   uint32_t reg_value = value.GetAsUInt32();
 829   // As precaution for an undefined behavior encountered while setting PC we
 830   // will clear thumb bit of new PC if we are already in thumb mode; that is
 831   // CPSR thumb mode bit is set.
 832   if (offset / sizeof(uint32_t) == gpr_pc_arm) {
 833     // Check if we are already in thumb mode and thumb bit of current PC is
 834     // read out to be zero and thumb bit of next PC is read out to be one.
 835     if ((m_gpr_arm[gpr_cpsr_arm] & 0x20) && !(m_gpr_arm[gpr_pc_arm] & 0x01) &&
 836         (value.GetAsUInt32() & 0x01)) {
 837       reg_value &= (~1ull);
 838     }
 839   }
 840
 841   m_gpr_arm[offset / sizeof(uint32_t)] = reg_value;
 842   return WriteGPR();
 843 }
 844
 845 Status NativeRegisterContextLinux_arm::ReadGPR() {
 846 #ifdef __arm__
 847   return NativeRegisterContextLinux::ReadGPR();
 848 #else  // __aarch64__
 849   struct iovec ioVec;
 850   ioVec.iov_base = GetGPRBuffer();
 851   ioVec.iov_len = GetGPRSize();
 852
 853   return ReadRegisterSet(&ioVec, GetGPRSize(), NT_PRSTATUS);
 854 #endif // __arm__
 855 }
 856
 857 Status NativeRegisterContextLinux_arm::WriteGPR() {
 858 #ifdef __arm__
 859   return NativeRegisterContextLinux::WriteGPR();
 860 #else  // __aarch64__
 861   struct iovec ioVec;
 862   ioVec.iov_base = GetGPRBuffer();
 863   ioVec.iov_len = GetGPRSize();
 864
 865   return WriteRegisterSet(&ioVec, GetGPRSize(), NT_PRSTATUS);
 866 #endif // __arm__
 867 }
 868
 869 Status NativeRegisterContextLinux_arm::ReadFPR() {
 870 #ifdef __arm__
 871   return NativeProcessLinux::PtraceWrapper(PTRACE_GETVFPREGS, m_thread.GetID(),
 872                                            nullptr, GetFPRBuffer(),
 873                                            GetFPRSize());
 874 #else  // __aarch64__
 875   struct iovec ioVec;
 876   ioVec.iov_base = GetFPRBuffer();
 877   ioVec.iov_len = GetFPRSize();
 878
 879   return ReadRegisterSet(&ioVec, GetFPRSize(), NT_ARM_VFP);
 880 #endif // __arm__
 881 }
 882
 883 Status NativeRegisterContextLinux_arm::WriteFPR() {
 884 #ifdef __arm__
 885   return NativeProcessLinux::PtraceWrapper(PTRACE_SETVFPREGS, m_thread.GetID(),
 886                                            nullptr, GetFPRBuffer(),
 887                                            GetFPRSize());
 888 #else  // __aarch64__
 889   struct iovec ioVec;
 890   ioVec.iov_base = GetFPRBuffer();
 891   ioVec.iov_len = GetFPRSize();
 892
 893   return WriteRegisterSet(&ioVec, GetFPRSize(), NT_ARM_VFP);
 894 #endif // __arm__
 895 }
 896
 897 #endif // defined(__arm__) || defined(__arm64__) || defined(__aarch64__)