lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h

   1 //===-- NativeRegisterContextLinux_arm64.h ---------------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 #if defined(__arm64__) || defined(__aarch64__)
  10
  11 #ifndef lldb_NativeRegisterContextLinux_arm64_h
  12 #define lldb_NativeRegisterContextLinux_arm64_h
  13
  14 #include "Plugins/Process/Linux/NativeRegisterContextLinux.h"
  15 #include "Plugins/Process/Utility/LinuxPTraceDefines_arm64sve.h"
  16 #include "Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.h"
  17 #include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h"
  18
  19 #include <asm/ptrace.h>
  20
  21 namespace lldb_private {
  22 namespace process_linux {
  23
  24 class NativeProcessLinux;
  25
  26 class NativeRegisterContextLinux_arm64
  27     : public NativeRegisterContextLinux,
  28       public NativeRegisterContextDBReg_arm64 {
  29 public:
  30   NativeRegisterContextLinux_arm64(
  31       const ArchSpec &target_arch, NativeThreadProtocol &native_thread,
  32       std::unique_ptr<RegisterInfoPOSIX_arm64> register_info_up);
  33
  34   uint32_t GetRegisterSetCount() const override;
  35
  36   uint32_t GetUserRegisterCount() const override;
  37
  38   const RegisterSet *GetRegisterSet(uint32_t set_index) const override;
  39
  40   Status ReadRegister(const RegisterInfo *reg_info,
  41                       RegisterValue &reg_value) override;
  42
  43   Status WriteRegister(const RegisterInfo *reg_info,
  44                        const RegisterValue &reg_value) override;
  45
  46   Status ReadAllRegisterValues(lldb::WritableDataBufferSP &data_sp) override;
  47
  48   Status WriteAllRegisterValues(const lldb::DataBufferSP &data_sp) override;
  49
  50   void InvalidateAllRegisters() override;
  51
  52   std::vector<uint32_t>
  53   GetExpeditedRegisters(ExpeditedRegs expType) const override;
  54
  55   bool RegisterOffsetIsDynamic() const override { return true; }
  56
  57   llvm::Expected<MemoryTaggingDetails>
  58   GetMemoryTaggingDetails(int32_t type) override;
  59
  60 protected:
  61   Status ReadGPR() override;
  62
  63   Status WriteGPR() override;
  64
  65   Status ReadFPR() override;
  66
  67   Status WriteFPR() override;
  68
  69   void *GetGPRBuffer() override { return &m_gpr_arm64; }
  70
  71   // GetGPRBufferSize returns sizeof arm64 GPR ptrace buffer, it is different
  72   // from GetGPRSize which returns sizeof RegisterInfoPOSIX_arm64::GPR.
  73   size_t GetGPRBufferSize() { return sizeof(m_gpr_arm64); }
  74
  75   void *GetFPRBuffer() override { return &m_fpr; }
  76
  77   size_t GetFPRSize() override { return sizeof(m_fpr); }
  78
  79   lldb::addr_t FixWatchpointHitAddress(lldb::addr_t hit_addr) override;
  80
  81 private:
  82   bool m_gpr_is_valid;
  83   bool m_fpu_is_valid;
  84   bool m_sve_buffer_is_valid;
  85   bool m_mte_ctrl_is_valid;
  86   bool m_zt_buffer_is_valid;
  87   bool m_fpmr_is_valid;
  88
  89   bool m_sve_header_is_valid;
  90   bool m_za_buffer_is_valid;
  91   bool m_za_header_is_valid;
  92   bool m_pac_mask_is_valid;
  93   bool m_tls_is_valid;
  94   size_t m_tls_size;
  95
  96   struct user_pt_regs m_gpr_arm64; // 64-bit general purpose registers.
  97
  98   RegisterInfoPOSIX_arm64::FPU
  99       m_fpr; // floating-point registers including extended register sets.
 100
 101   SVEState m_sve_state = SVEState::Unknown;
 102   struct sve::user_sve_header m_sve_header;
 103   std::vector<uint8_t> m_sve_ptrace_payload;
 104
 105   sve::user_za_header m_za_header;
 106   std::vector<uint8_t> m_za_ptrace_payload;
 107
 108   bool m_refresh_hwdebug_info;
 109
 110   struct user_pac_mask {
 111     uint64_t data_mask;
 112     uint64_t insn_mask;
 113   };
 114
 115   struct user_pac_mask m_pac_mask;
 116
 117   uint64_t m_mte_ctrl_reg;
 118
 119   struct sme_pseudo_regs {
 120     uint64_t ctrl_reg;
 121     uint64_t svg_reg;
 122   };
 123
 124   struct sme_pseudo_regs m_sme_pseudo_regs;
 125
 126   struct tls_regs {
 127     uint64_t tpidr_reg;
 128     // Only valid when SME is present.
 129     uint64_t tpidr2_reg;
 130   };
 131
 132   struct tls_regs m_tls_regs;
 133
 134   // SME2's ZT is a 512 bit register.
 135   std::array<uint8_t, 64> m_zt_reg;
 136
 137   uint64_t m_fpmr_reg;
 138
 139   bool IsGPR(unsigned reg) const;
 140
 141   bool IsFPR(unsigned reg) const;
 142
 143   Status ReadAllSVE();
 144
 145   Status WriteAllSVE();
 146
 147   Status ReadSVEHeader();
 148
 149   Status WriteSVEHeader();
 150
 151   Status ReadPAuthMask();
 152
 153   Status ReadMTEControl();
 154
 155   Status WriteMTEControl();
 156
 157   Status ReadTLS();
 158
 159   Status WriteTLS();
 160
 161   Status ReadSMESVG();
 162
 163   Status ReadZAHeader();
 164
 165   Status ReadZA();
 166
 167   Status WriteZA();
 168
 169   // No WriteZAHeader because writing only the header will disable ZA.
 170   // Instead use WriteZA and ensure you have the correct ZA buffer size set
 171   // beforehand if you wish to disable it.
 172
 173   Status ReadZT();
 174
 175   Status WriteZT();
 176
 177   // SVCR is a pseudo register and we do not allow writes to it.
 178   Status ReadSMEControl();
 179
 180   Status ReadFPMR();
 181
 182   Status WriteFPMR();
 183
 184   bool IsSVE(unsigned reg) const;
 185   bool IsSME(unsigned reg) const;
 186   bool IsPAuth(unsigned reg) const;
 187   bool IsMTE(unsigned reg) const;
 188   bool IsTLS(unsigned reg) const;
 189   bool IsFPMR(unsigned reg) const;
 190
 191   uint64_t GetSVERegVG() { return m_sve_header.vl / 8; }
 192
 193   void SetSVERegVG(uint64_t vg) { m_sve_header.vl = vg * 8; }
 194
 195   void *GetSVEHeader() { return &m_sve_header; }
 196
 197   void *GetZAHeader() { return &m_za_header; }
 198
 199   size_t GetZAHeaderSize() { return sizeof(m_za_header); }
 200
 201   void *GetPACMask() { return &m_pac_mask; }
 202
 203   void *GetMTEControl() { return &m_mte_ctrl_reg; }
 204
 205   void *GetTLSBuffer() { return &m_tls_regs; }
 206
 207   void *GetSMEPseudoBuffer() { return &m_sme_pseudo_regs; }
 208
 209   void *GetZTBuffer() { return m_zt_reg.data(); }
 210
 211   void *GetSVEBuffer() { return m_sve_ptrace_payload.data(); }
 212
 213   void *GetFPMRBuffer() { return &m_fpmr_reg; }
 214
 215   size_t GetSVEHeaderSize() { return sizeof(m_sve_header); }
 216
 217   size_t GetPACMaskSize() { return sizeof(m_pac_mask); }
 218
 219   size_t GetSVEBufferSize() { return m_sve_ptrace_payload.size(); }
 220
 221   unsigned GetSVERegSet();
 222
 223   void *GetZABuffer() { return m_za_ptrace_payload.data(); };
 224
 225   size_t GetZABufferSize() { return m_za_ptrace_payload.size(); }
 226
 227   size_t GetMTEControlSize() { return sizeof(m_mte_ctrl_reg); }
 228
 229   size_t GetTLSBufferSize() { return m_tls_size; }
 230
 231   size_t GetSMEPseudoBufferSize() { return sizeof(m_sme_pseudo_regs); }
 232
 233   size_t GetZTBufferSize() { return m_zt_reg.size(); }
 234
 235   size_t GetFPMRBufferSize() { return sizeof(m_fpmr_reg); }
 236
 237   llvm::Error ReadHardwareDebugInfo() override;
 238
 239   llvm::Error WriteHardwareDebugRegs(DREGType hwbType) override;
 240
 241   uint32_t CalculateFprOffset(const RegisterInfo *reg_info) const;
 242
 243   RegisterInfoPOSIX_arm64 &GetRegisterInfo() const;
 244
 245   void ConfigureRegisterContext();
 246
 247   uint32_t CalculateSVEOffset(const RegisterInfo *reg_info) const;
 248
 249   Status CacheAllRegisters(uint32_t &cached_size);
 250 };
 251
 252 } // namespace process_linux
 253 } // namespace lldb_private
 254
 255 #endif // #ifndef lldb_NativeRegisterContextLinux_arm64_h
 256
 257 #endif // defined (__arm64__) || defined (__aarch64__)