llvm/docs/AMDGPU/gfx10_fx_operand.rst

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   8 .. _amdgpu_synid_gfx10_fx_operand:
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  10 FX Operand
  11 ==========
  12
  13 This is a *f32* or *f16* operand depending on instruction modifiers:
  14
  15 * Operand size is controlled by :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
  16 * Location of the 16-bit operand is controlled by :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.