[X86] Improve F16C CVT schedules on SNB/HSW/BDW
[llvm-project.git] / llvm / docs / AMDGPU / gfx8_soffset_32c2a9.rst
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10 soffset
11 =======
13 An unsigned byte offset, which is added to the base address to get the memory address.
15 *Size:* 1 dword.
17 *Operands:* :ref:`m0<amdgpu_synid_m0>`, :ref:`uimm20<amdgpu_synid_uimm20>`